mes_v12_0.c | Explore in Territory

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include <linux/module.h>
#include "amdgpu.h"
#include "soc15_common.h"
#include "soc21.h"
#include "gc/gc_12_0_0_offset.h"
#include "gc/gc_12_0_0_sh_mask.h"
#include "gc/gc_11_0_0_default.h"
#include "v12_structs.h"
#include "mes_v12_api_def.h"

MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;

static int mes_v12_0_hw_init(void *handle);
static int mes_v12_0_hw_fini(void *handle);
static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);

#define MES_EOP_SIZE …

static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
{ … }

static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
{ … }

static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
{ … }

static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = …;

static const char *mes_v12_0_opcodes[] = …;

static const char *mes_v12_0_misc_opcodes[] = …;

static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
{ … }

static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
{ … }

static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
						    void *pkt, int size,
						    int api_status_off)
{ … }

static int convert_to_mes_queue_type(int queue_type)
{ … }

static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
				  struct mes_add_queue_input *input)
{ … }

static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
				     struct mes_remove_queue_input *input)
{ … }

static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
				      struct mes_map_legacy_queue_input *input)
{ … }

static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
			struct mes_unmap_legacy_queue_input *input)
{ … }

static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
				  struct mes_suspend_gang_input *input)
{ … }

static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
				 struct mes_resume_gang_input *input)
{ … }

static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes)
{ … }

static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
			     struct mes_misc_op_input *input)
{ … }

static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes)
{ … }

static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes)
{ … }

static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
{ … }


static void mes_v12_0_enable_unmapped_doorbell_handling(
		struct amdgpu_mes *mes, bool enable)
{ … }

static const struct amdgpu_mes_funcs mes_v12_0_funcs = …;

static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
					   enum admgpu_mes_pipe pipe)
{ … }

static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
						enum admgpu_mes_pipe pipe)
{ … }

static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
					 enum admgpu_mes_pipe pipe)
{ … }

static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
{ … }

static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
{ … }

/* This function is for backdoor MES firmware */
static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
				    enum admgpu_mes_pipe pipe, bool prime_icache)
{ … }

static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
				      enum admgpu_mes_pipe pipe)
{ … }

static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
{ … }

static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
{ … }

static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
{ … }

static int mes_v12_0_queue_init(struct amdgpu_device *adev,
				enum admgpu_mes_pipe pipe)
{ … }

static int mes_v12_0_ring_init(struct amdgpu_device *adev)
{ … }

static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
{ … }

static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
				 enum admgpu_mes_pipe pipe)
{ … }

static int mes_v12_0_sw_init(void *handle)
{ … }

static int mes_v12_0_sw_fini(void *handle)
{ … }

static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
{ … }

static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
{ … }

static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
{ … }

static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
{ … }

static int mes_v12_0_hw_init(void *handle)
{ … }

static int mes_v12_0_hw_fini(void *handle)
{ … }

static int mes_v12_0_suspend(void *handle)
{ … }

static int mes_v12_0_resume(void *handle)
{ … }

static int mes_v12_0_early_init(void *handle)
{ … }

static int mes_v12_0_late_init(void *handle)
{ … }

static const struct amd_ip_funcs mes_v12_0_ip_funcs = …;

const struct amdgpu_ip_block_version mes_v12_0_ip_block = …;
linux/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
