#ifndef _thm_14_0_2_OFFSET_HEADER
#define _thm_14_0_2_OFFSET_HEADER
#define regTHM_TCON_CUR_TMP …
#define regTHM_TCON_CUR_TMP_BASE_IDX …
#define regTHM_TCON_HTC …
#define regTHM_TCON_HTC_BASE_IDX …
#define regTHM_TCON_THERM_TRIP …
#define regTHM_TCON_THERM_TRIP_BASE_IDX …
#define regTHM_CTF_DELAY …
#define regTHM_CTF_DELAY_BASE_IDX …
#define regTHM_GPIO_PROCHOT_CTRL …
#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX …
#define regTHM_GPIO_THERMTRIP_CTRL …
#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX …
#define regTHM_GPIO_PWM_CTRL …
#define regTHM_GPIO_PWM_CTRL_BASE_IDX …
#define regTHM_GPIO_TACHIN_CTRL …
#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX …
#define regTHM_GPIO_PUMPOUT_CTRL …
#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX …
#define regTHM_GPIO_PUMPIN_CTRL …
#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX …
#define regTHM_THERMAL_INT_ENA …
#define regTHM_THERMAL_INT_ENA_BASE_IDX …
#define regTHM_THERMAL_INT_CTRL …
#define regTHM_THERMAL_INT_CTRL_BASE_IDX …
#define regTHM_THERMAL_INT_STATUS …
#define regTHM_THERMAL_INT_STATUS_BASE_IDX …
#define regTHM_SW_TEMP …
#define regTHM_SW_TEMP_BASE_IDX …
#define regCG_MULT_THERMAL_CTRL …
#define regCG_MULT_THERMAL_CTRL_BASE_IDX …
#define regCG_MULT_THERMAL_STATUS …
#define regCG_MULT_THERMAL_STATUS_BASE_IDX …
#define regCG_THERMAL_RANGE …
#define regCG_THERMAL_RANGE_BASE_IDX …
#define regCG_FDO_CTRL0 …
#define regCG_FDO_CTRL0_BASE_IDX …
#define regCG_FDO_CTRL1 …
#define regCG_FDO_CTRL1_BASE_IDX …
#define regCG_FDO_CTRL2 …
#define regCG_FDO_CTRL2_BASE_IDX …
#define regCG_TACH_CTRL …
#define regCG_TACH_CTRL_BASE_IDX …
#define regCG_TACH_STATUS …
#define regCG_TACH_STATUS_BASE_IDX …
#define regCG_THERMAL_STATUS …
#define regCG_THERMAL_STATUS_BASE_IDX …
#define regCG_PUMP_CTRL0 …
#define regCG_PUMP_CTRL0_BASE_IDX …
#define regCG_PUMP_CTRL1 …
#define regCG_PUMP_CTRL1_BASE_IDX …
#define regCG_PUMP_CTRL2 …
#define regCG_PUMP_CTRL2_BASE_IDX …
#define regCG_PUMP_TACH_CTRL …
#define regCG_PUMP_TACH_CTRL_BASE_IDX …
#define regCG_PUMP_TACH_STATUS …
#define regCG_PUMP_TACH_STATUS_BASE_IDX …
#define regCG_PUMP_STATUS …
#define regCG_PUMP_STATUS_BASE_IDX …
#define regTHM_TCON_LOCAL2 …
#define regTHM_TCON_LOCAL2_BASE_IDX …
#define regTHM_TCON_LOCAL3 …
#define regTHM_TCON_LOCAL3_BASE_IDX …
#define regTHM_TCON_LOCAL4 …
#define regTHM_TCON_LOCAL4_BASE_IDX …
#define regTHM_TCON_LOCAL5 …
#define regTHM_TCON_LOCAL5_BASE_IDX …
#define regTHM_TCON_LOCAL6 …
#define regTHM_TCON_LOCAL6_BASE_IDX …
#define regTHM_TCON_LOCAL7 …
#define regTHM_TCON_LOCAL7_BASE_IDX …
#define regTHM_TCON_LOCAL8 …
#define regTHM_TCON_LOCAL8_BASE_IDX …
#define regTHM_TCON_LOCAL9 …
#define regTHM_TCON_LOCAL9_BASE_IDX …
#define regTHM_TCON_LOCAL10 …
#define regTHM_TCON_LOCAL10_BASE_IDX …
#define regTHM_TCON_LOCAL11 …
#define regTHM_TCON_LOCAL11_BASE_IDX …
#define regTHM_TCON_LOCAL12 …
#define regTHM_TCON_LOCAL12_BASE_IDX …
#define regTHM_TCON_LOCAL13 …
#define regTHM_TCON_LOCAL13_BASE_IDX …
#define regTHM_TCON_LOCAL14 …
#define regTHM_TCON_LOCAL14_BASE_IDX …
#define regTHM_TCON_LOCAL15 …
#define regTHM_TCON_LOCAL15_BASE_IDX …
#define regTHM_BACO_CNTL …
#define regTHM_BACO_CNTL_BASE_IDX …
#define regTHM_BACO_TIMING0 …
#define regTHM_BACO_TIMING0_BASE_IDX …
#define regTHM_BACO_TIMING1 …
#define regTHM_BACO_TIMING1_BASE_IDX …
#define regTHM_BACO_TIMING2 …
#define regTHM_BACO_TIMING2_BASE_IDX …
#define regTHM_BACO_TIMING …
#define regTHM_BACO_TIMING_BASE_IDX …
#define regXTAL_CNTL …
#define regXTAL_CNTL_BASE_IDX …
#define regTHM_PWRMGT …
#define regTHM_PWRMGT_BASE_IDX …
#define regSMUSBI_SBIREGADDR …
#define regSMUSBI_SBIREGADDR_BASE_IDX …
#define regSMUSBI_SBIREGDATA …
#define regSMUSBI_SBIREGDATA_BASE_IDX …
#define regSMUSBI_ERRATA_STAT_REG …
#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX …
#define regSMUSBI_SBICTRL …
#define regSMUSBI_SBICTRL_BASE_IDX …
#define regSMUSBI_CKNBIRESET …
#define regSMUSBI_CKNBIRESET_BASE_IDX …
#define regSMUSBI_TIMING …
#define regSMUSBI_TIMING_BASE_IDX …
#define regSMUSBI_HS_TIMING …
#define regSMUSBI_HS_TIMING_BASE_IDX …
#define regSBTSI_REMOTE_TEMP …
#define regSBTSI_REMOTE_TEMP_BASE_IDX …
#define regSBRMI_CONTROL …
#define regSBRMI_CONTROL_BASE_IDX …
#define regSBRMI_COMMAND …
#define regSBRMI_COMMAND_BASE_IDX …
#define regSBRMI_WRITE_DATA0 …
#define regSBRMI_WRITE_DATA0_BASE_IDX …
#define regSBRMI_WRITE_DATA1 …
#define regSBRMI_WRITE_DATA1_BASE_IDX …
#define regSBRMI_WRITE_DATA2 …
#define regSBRMI_WRITE_DATA2_BASE_IDX …
#define regSBRMI_READ_DATA0 …
#define regSBRMI_READ_DATA0_BASE_IDX …
#define regSBRMI_READ_DATA1 …
#define regSBRMI_READ_DATA1_BASE_IDX …
#define regSBRMI_CORE_EN_NUMBER …
#define regSBRMI_CORE_EN_NUMBER_BASE_IDX …
#define regSBRMI_CORE_EN_STATUS0 …
#define regSBRMI_CORE_EN_STATUS0_BASE_IDX …
#define regSBRMI_CORE_EN_STATUS1 …
#define regSBRMI_CORE_EN_STATUS1_BASE_IDX …
#define regSBRMI_APIC_STATUS0 …
#define regSBRMI_APIC_STATUS0_BASE_IDX …
#define regSBRMI_APIC_STATUS1 …
#define regSBRMI_APIC_STATUS1_BASE_IDX …
#define regSBRMI_MCE_STATUS0 …
#define regSBRMI_MCE_STATUS0_BASE_IDX …
#define regSBRMI_MCE_STATUS1 …
#define regSBRMI_MCE_STATUS1_BASE_IDX …
#define regSMBUS_CNTL0 …
#define regSMBUS_CNTL0_BASE_IDX …
#define regSMBUS_CNTL1 …
#define regSMBUS_CNTL1_BASE_IDX …
#define regSMBUS_BLKWR_CMD_CTRL0 …
#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX …
#define regSMBUS_BLKWR_CMD_CTRL1 …
#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX …
#define regSMBUS_BLKRD_CMD_CTRL0 …
#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX …
#define regSMBUS_BLKRD_CMD_CTRL1 …
#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX …
#define regSMBUS_TIMING_CNTL0 …
#define regSMBUS_TIMING_CNTL0_BASE_IDX …
#define regSMBUS_TIMING_CNTL1 …
#define regSMBUS_TIMING_CNTL1_BASE_IDX …
#define regSMBUS_TIMING_CNTL2 …
#define regSMBUS_TIMING_CNTL2_BASE_IDX …
#define regSMBUS_TRIGGER_CNTL …
#define regSMBUS_TRIGGER_CNTL_BASE_IDX …
#define regSMBUS_UDID_CNTL0 …
#define regSMBUS_UDID_CNTL0_BASE_IDX …
#define regSMBUS_UDID_CNTL1 …
#define regSMBUS_UDID_CNTL1_BASE_IDX …
#define regSMBUS_UDID_CNTL2 …
#define regSMBUS_UDID_CNTL2_BASE_IDX …
#define regSMUSBI_SMBUS …
#define regSMUSBI_SMBUS_BASE_IDX …
#define regSMUSBI_ALERT …
#define regSMUSBI_ALERT_BASE_IDX …
#define regSMBUS_BACO_DUMMY …
#define regSMBUS_BACO_DUMMY_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE0_LOW …
#define regSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE0_HIGH …
#define regSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE1_LOW …
#define regSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE1_HIGH …
#define regSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE2_LOW …
#define regSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE2_HIGH …
#define regSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE3_LOW …
#define regSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE3_HIGH …
#define regSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE4_LOW …
#define regSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX …
#define regSMBUS_BACO_ADDR_RANGE4_HIGH …
#define regSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX …
#endif