linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.


#ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__
#define __DML_TOP_DISPLAY_CFG_TYPES_H__

#include "dml2_external_lib_deps.h"

#define DML2_MAX_PLANES
#define DML2_MAX_DCN_PIPES
#define DML2_MAX_MCACHES

enum dml2_swizzle_mode {};

enum dml2_source_format_class {};

enum dml2_rotation_angle {};

enum dml2_output_format_class {};

enum dml2_output_encoder_class {};

enum dml2_output_link_dp_rate {};

enum dml2_uclk_pstate_change_strategy {};

enum dml2_svp_mode_override {};

enum dml2_refresh_from_mall_mode_override {};

enum dml2_odm_mode {};

enum dml2_scaling_transform {};

enum dml2_dsc_enable_option {};

enum dml2_pstate_support_method {};

enum dml2_tdlut_addressing_mode {};

enum dml2_tdlut_width_mode {};

enum dml2_twait_budgeting_setting {};

struct dml2_get_cursor_dlg_reg{};

/// @brief Surface Parameters
struct dml2_surface_cfg {};


struct dml2_composition_cfg {};

struct dml2_timing_cfg {};

struct dml2_link_output_cfg {};

struct dml2_writeback_cfg {};

struct dml2_plane_parameters {};

struct dml2_stream_parameters {};

struct dml2_display_cfg {};

struct dml2_pipe_configuration_descriptor {};

struct dml2_plane_mcache_configuration_descriptor {};

#endif