dcn10_hubp.h | Explore in Territory

/* Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_MEM_INPUT_DCN10_H__
#define __DC_MEM_INPUT_DCN10_H__

#include "hubp.h"

#define TO_DCN10_HUBP(hubp) …

/* Register address initialization macro for all ASICs (including those with reduced functionality) */
#define HUBP_REG_LIST_DCN(id) …

/* Register address initialization macro for ASICs with VM */
#define HUBP_REG_LIST_DCN_VM(id) …

#define HUBP_REG_LIST_DCN10(id) …

#define HUBP_COMMON_REG_VARIABLE_LIST …

#define HUBP_SF(reg_name, field_name, post_fix) …

/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
/*1.x, 2.x, and 3.x*/
#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh) …
/*2.x and 1.x only*/
#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) …

/*2.x and 1.x only*/
#define HUBP_MASK_SH_LIST_DCN(mask_sh) …

/* Mask/shift struct generation macro for ASICs with VM */
#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh) …

#define HUBP_MASK_SH_LIST_DCN10(mask_sh) …

#define DCN_HUBP_REG_FIELD_BASE_LIST(type) …

#define DCN_HUBP_REG_FIELD_LIST(type) …

struct dcn_mi_registers { … };

struct dcn_mi_shift { … };

struct dcn_mi_mask { … };

struct dcn_hubp_state { … };

struct dcn10_hubp { … };

void hubp1_program_surface_config(
	struct hubp *hubp,
	enum surface_pixel_format format,
	union dc_tiling_info *tiling_info,
	struct plane_size *plane_size,
	enum dc_rotation_angle rotation,
	struct dc_plane_dcc_param *dcc,
	bool horizontal_mirror,
	unsigned int compat_level);

void hubp1_program_deadline(
		struct hubp *hubp,
		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);

void hubp1_program_requestor(
		struct hubp *hubp,
		struct _vcs_dpi_display_rq_regs_st *rq_regs);

void hubp1_program_pixel_format(
	struct hubp *hubp,
	enum surface_pixel_format format);

void hubp1_program_size(
	struct hubp *hubp,
	enum surface_pixel_format format,
	const struct plane_size *plane_size,
	struct dc_plane_dcc_param *dcc);

void hubp1_program_rotation(
	struct hubp *hubp,
	enum dc_rotation_angle rotation,
	bool horizontal_mirror);

void hubp1_program_tiling(
	struct hubp *hubp,
	const union dc_tiling_info *info,
	const enum surface_pixel_format pixel_format);

void hubp1_dcc_control(struct hubp *hubp,
		bool enable,
		enum hubp_ind_block_size independent_64b_blks);

bool hubp1_program_surface_flip_and_addr(
	struct hubp *hubp,
	const struct dc_plane_address *address,
	bool flip_immediate);

bool hubp1_is_flip_pending(struct hubp *hubp);

void hubp1_cursor_set_attributes(
		struct hubp *hubp,
		const struct dc_cursor_attributes *attr);

void hubp1_cursor_set_position(
		struct hubp *hubp,
		const struct dc_cursor_position *pos,
		const struct dc_cursor_mi_param *param);

void hubp1_set_blank(struct hubp *hubp, bool blank);

void min_set_viewport(struct hubp *hubp,
		const struct rect *viewport,
		const struct rect *viewport_c);

void hubp1_clk_cntl(struct hubp *hubp, bool enable);
void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

void dcn10_hubp_construct(
	struct dcn10_hubp *hubp1,
	struct dc_context *ctx,
	uint32_t inst,
	const struct dcn_mi_registers *hubp_regs,
	const struct dcn_mi_shift *hubp_shift,
	const struct dcn_mi_mask *hubp_mask);

void hubp1_read_state(struct hubp *hubp);
void hubp1_clear_underflow(struct hubp *hubp);

enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);

void hubp1_vready_workaround(struct hubp *hubp,
		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);

void hubp1_init(struct hubp *hubp);
void hubp1_read_state_common(struct hubp *hubp);
bool hubp1_in_blank(struct hubp *hubp);
void hubp1_soft_reset(struct hubp *hubp, bool reset);

void hubp1_set_flip_int(struct hubp *hubp);

#endif
linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
