// SPDX-License-Identifier: MIT // // Copyright 2024 Advanced Micro Devices, Inc. #ifndef _DCN401_RESOURCE_H_ #define _DCN401_RESOURCE_H_ #include "core_types.h" #include "dcn32/dcn32_resource.h" #include "dcn401/dcn401_hubp.h" #define TO_DCN401_RES_POOL(pool) … struct dcn401_resource_pool { … }; struct resource_pool *dcn401_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc); enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state); bool dcn401_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate); void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); /* Following are definitions for run time init of reg offsets */ /* HUBP */ #define HUBP_REG_LIST_DCN401_RI(id) … /* ABM */ #define ABM_DCN401_REG_LIST_RI(id) … /* VPG */ #define VPG_DCN401_REG_LIST_RI(id) … /* Stream encoder */ #define SE_DCN4_01_REG_LIST_RI(id) … /* Link encoder */ #define LE_DCN401_REG_LIST_RI(id) … /* DPP */ #define DPP_REG_LIST_DCN401_COMMON_RI(id) … /* OPP */ #define OPP_REG_LIST_DCN401_RI(id) … /* DSC */ #define DSC_REG_LIST_DCN401_RI(id) … /* MPC */ #define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst) … #define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst) … #define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst) … /* OPTC */ #define OPTC_COMMON_REG_LIST_DCN401_RI(inst) … /* HUBBUB */ #define HUBBUB_REG_LIST_DCN4_01_RI(id) … /* DCCG */ #define DCCG_REG_LIST_DCN401_RI() … #endif /* _DCN401_RESOURCE_H_ */
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