// SPDX-License-Identifier: MIT // // Copyright 2024 Advanced Micro Devices, Inc. #ifndef __DCN401_CLK_MGR_H_ #define __DCN401_CLK_MGR_H_ #define DCN401_CLK_MGR_MAX_SEQUENCE_SIZE … dcn401_clk_mgr_block_sequence_params; enum dcn401_clk_mgr_block_sequence_func { … }; struct dcn401_clk_mgr_block_sequence { … }; struct dcn401_clk_mgr { … }; void dcn401_init_clocks(struct clk_mgr *clk_mgr_base); struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx, struct dccg *dccg); void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr); #endif /* __DCN401_CLK_MGR_H_ */