// SPDX-License-Identifier: MIT // // Copyright 2024 Advanced Micro Devices, Inc. #ifndef _dcn_4_1_0_OFFSET_HEADER #define _dcn_4_1_0_OFFSET_HEADER // addressBlock: dcn_dcec_dccg_dccg_dfs_dispdec // base address: 0x0 #define regDENTIST_DISPCLK_CNTL … #define regDENTIST_DISPCLK_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dccg_dccg_dispdec // base address: 0x0 #define regPHYPLLA_PIXCLK_RESYNC_CNTL … #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regPHYPLLB_PIXCLK_RESYNC_CNTL … #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regPHYPLLC_PIXCLK_RESYNC_CNTL … #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regPHYPLLD_PIXCLK_RESYNC_CNTL … #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regDP_DTO_DBUF_EN … #define regDP_DTO_DBUF_EN_BASE_IDX … #define regDSCCLK3_DTO_PARAM … #define regDSCCLK3_DTO_PARAM_BASE_IDX … #define regDSCCLK4_DTO_PARAM … #define regDSCCLK4_DTO_PARAM_BASE_IDX … #define regDSCCLK5_DTO_PARAM … #define regDSCCLK5_DTO_PARAM_BASE_IDX … #define regDPREFCLK_CGTT_BLK_CTRL_REG … #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL4 … #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX … #define regDPSTREAMCLK_CNTL … #define regDPSTREAMCLK_CNTL_BASE_IDX … #define regREFCLK_CGTT_BLK_CTRL_REG … #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regPHYPLLE_PIXCLK_RESYNC_CNTL … #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regDCCG_GLOBAL_FGCG_REP_CNTL … #define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX … #define regSYMCLKG_CLOCK_ENABLE … #define regSYMCLKG_CLOCK_ENABLE_BASE_IDX … #define regDPREFCLK_CNTL … #define regDPREFCLK_CNTL_BASE_IDX … #define regAOMCLK0_CNTL … #define regAOMCLK0_CNTL_BASE_IDX … #define regAOMCLK1_CNTL … #define regAOMCLK1_CNTL_BASE_IDX … #define regAOMCLK2_CNTL … #define regAOMCLK2_CNTL_BASE_IDX … #define regDCCG_AUDIO_DTO2_PHASE … #define regDCCG_AUDIO_DTO2_PHASE_BASE_IDX … #define regDCCG_AUDIO_DTO2_MODULO … #define regDCCG_AUDIO_DTO2_MODULO_BASE_IDX … #define regDCE_VERSION … #define regDCE_VERSION_BASE_IDX … #define regPHYPLLG_PIXCLK_RESYNC_CNTL … #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regSYMCLK32_SE_CNTL … #define regSYMCLK32_SE_CNTL_BASE_IDX … #define regSYMCLK32_LE_CNTL … #define regSYMCLK32_LE_CNTL_BASE_IDX … #define regDTBCLK_P_CNTL … #define regDTBCLK_P_CNTL_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL5 … #define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX … #define regDSCCLK0_DTO_PARAM … #define regDSCCLK0_DTO_PARAM_BASE_IDX … #define regDSCCLK1_DTO_PARAM … #define regDSCCLK1_DTO_PARAM_BASE_IDX … #define regDSCCLK2_DTO_PARAM … #define regDSCCLK2_DTO_PARAM_BASE_IDX … #define regOTG_PIXEL_RATE_DIV … #define regOTG_PIXEL_RATE_DIV_BASE_IDX … #define regMILLISECOND_TIME_BASE_DIV … #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX … #define regDISPCLK_FREQ_CHANGE_CNTL … #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX … #define regDC_MEM_GLOBAL_PWR_REQ_CNTL … #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL … #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX … #define regDISPCLK_CGTT_BLK_CTRL_REG … #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regSOCCLK_CGTT_BLK_CTRL_REG … #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regDCCG_CAC_STATUS … #define regDCCG_CAC_STATUS_BASE_IDX … #define regPIXCLK1_RESYNC_CNTL … #define regPIXCLK1_RESYNC_CNTL_BASE_IDX … #define regPIXCLK2_RESYNC_CNTL … #define regPIXCLK2_RESYNC_CNTL_BASE_IDX … #define regPIXCLK0_RESYNC_CNTL … #define regPIXCLK0_RESYNC_CNTL_BASE_IDX … #define regMICROSECOND_TIME_BASE_DIV … #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL2 … #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX … #define regSYMCLK_CGTT_BLK_CTRL_REG … #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regPHYPLLF_PIXCLK_RESYNC_CNTL … #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … #define regDCCG_DISP_CNTL_REG … #define regDCCG_DISP_CNTL_REG_BASE_IDX … #define regOTG0_PIXEL_RATE_CNTL … #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO0_PHASE … #define regDP_DTO0_PHASE_BASE_IDX … #define regDP_DTO0_MODULO … #define regDP_DTO0_MODULO_BASE_IDX … #define regOTG0_PHYPLL_PIXEL_RATE_CNTL … #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regOTG1_PIXEL_RATE_CNTL … #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO1_PHASE … #define regDP_DTO1_PHASE_BASE_IDX … #define regDP_DTO1_MODULO … #define regDP_DTO1_MODULO_BASE_IDX … #define regOTG1_PHYPLL_PIXEL_RATE_CNTL … #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regOTG2_PIXEL_RATE_CNTL … #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO2_PHASE … #define regDP_DTO2_PHASE_BASE_IDX … #define regDP_DTO2_MODULO … #define regDP_DTO2_MODULO_BASE_IDX … #define regOTG2_PHYPLL_PIXEL_RATE_CNTL … #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regOTG3_PIXEL_RATE_CNTL … #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO3_PHASE … #define regDP_DTO3_PHASE_BASE_IDX … #define regDP_DTO3_MODULO … #define regDP_DTO3_MODULO_BASE_IDX … #define regOTG3_PHYPLL_PIXEL_RATE_CNTL … #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regOTG4_PIXEL_RATE_CNTL … #define regOTG4_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO4_PHASE … #define regDP_DTO4_PHASE_BASE_IDX … #define regDP_DTO4_MODULO … #define regDP_DTO4_MODULO_BASE_IDX … #define regOTG4_PHYPLL_PIXEL_RATE_CNTL … #define regOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regOTG5_PIXEL_RATE_CNTL … #define regOTG5_PIXEL_RATE_CNTL_BASE_IDX … #define regDP_DTO5_PHASE … #define regDP_DTO5_PHASE_BASE_IDX … #define regDP_DTO5_MODULO … #define regDP_DTO5_MODULO_BASE_IDX … #define regOTG5_PHYPLL_PIXEL_RATE_CNTL … #define regOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define regDPPCLK_CGTT_BLK_CTRL_REG … #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regDPPCLK0_DTO_PARAM … #define regDPPCLK0_DTO_PARAM_BASE_IDX … #define regDPPCLK1_DTO_PARAM … #define regDPPCLK1_DTO_PARAM_BASE_IDX … #define regDPPCLK2_DTO_PARAM … #define regDPPCLK2_DTO_PARAM_BASE_IDX … #define regDPPCLK3_DTO_PARAM … #define regDPPCLK3_DTO_PARAM_BASE_IDX … #define regDPPCLK4_DTO_PARAM … #define regDPPCLK4_DTO_PARAM_BASE_IDX … #define regDPPCLK5_DTO_PARAM … #define regDPPCLK5_DTO_PARAM_BASE_IDX … #define regDCCG_CAC_STATUS2 … #define regDCCG_CAC_STATUS2_BASE_IDX … #define regSYMCLKA_CLOCK_ENABLE … #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX … #define regSYMCLKB_CLOCK_ENABLE … #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX … #define regSYMCLKC_CLOCK_ENABLE … #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX … #define regSYMCLKD_CLOCK_ENABLE … #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX … #define regSYMCLKE_CLOCK_ENABLE … #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX … #define regSYMCLKF_CLOCK_ENABLE … #define regSYMCLKF_CLOCK_ENABLE_BASE_IDX … #define regDCCG_SOFT_RESET … #define regDCCG_SOFT_RESET_BASE_IDX … #define regDSCCLK_DTO_CTRL … #define regDSCCLK_DTO_CTRL_BASE_IDX … #define regDPPCLK_CTRL … #define regDPPCLK_CTRL_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL6 … #define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX … #define regSYMCLK_PSP_CNTL … #define regSYMCLK_PSP_CNTL_BASE_IDX … #define regDCCG_AUDIO_DTO_SOURCE … #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX … #define regDCCG_AUDIO_DTO0_PHASE … #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX … #define regDCCG_AUDIO_DTO0_MODULE … #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX … #define regDCCG_AUDIO_DTO1_PHASE … #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX … #define regDCCG_AUDIO_DTO1_MODULE … #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX … #define regDCCG_VSYNC_OTG0_LATCH_VALUE … #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … #define regDCCG_VSYNC_OTG1_LATCH_VALUE … #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … #define regDCCG_VSYNC_OTG2_LATCH_VALUE … #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX … #define regDCCG_VSYNC_OTG3_LATCH_VALUE … #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … #define regDCCG_VSYNC_OTG4_LATCH_VALUE … #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX … #define regDCCG_VSYNC_OTG5_LATCH_VALUE … #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … #define regDPPCLK_DTO_CTRL … #define regDPPCLK_DTO_CTRL_BASE_IDX … #define regDCCG_VSYNC_CNT_CTRL … #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX … #define regDCCG_VSYNC_CNT_INT_CTRL … #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX … #define regFORCE_SYMCLK_DISABLE … #define regFORCE_SYMCLK_DISABLE_BASE_IDX … #define regDCCG_TEST_CLK_SEL … #define regDCCG_TEST_CLK_SEL_BASE_IDX … #define regHDMICHARCLK0_CLOCK_CNTL … #define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX … #define regHDMICHARCLK1_CLOCK_CNTL … #define regHDMICHARCLK1_CLOCK_CNTL_BASE_IDX … #define regHDMICHARCLK2_CLOCK_CNTL … #define regHDMICHARCLK2_CLOCK_CNTL_BASE_IDX … #define regHDMICHARCLK3_CLOCK_CNTL … #define regHDMICHARCLK3_CLOCK_CNTL_BASE_IDX … #define regHDMICHARCLK4_CLOCK_CNTL … #define regHDMICHARCLK4_CLOCK_CNTL_BASE_IDX … #define regHDMICHARCLK5_CLOCK_CNTL … #define regHDMICHARCLK5_CLOCK_CNTL_BASE_IDX … #define regPHYASYMCLK_CLOCK_CNTL … #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYBSYMCLK_CLOCK_CNTL … #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYCSYMCLK_CLOCK_CNTL … #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYDSYMCLK_CLOCK_CNTL … #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYESYMCLK_CLOCK_CNTL … #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYFSYMCLK_CLOCK_CNTL … #define regPHYFSYMCLK_CLOCK_CNTL_BASE_IDX … #define regPHYGSYMCLK_CLOCK_CNTL … #define regPHYGSYMCLK_CLOCK_CNTL_BASE_IDX … #define regHDMISTREAMCLK_CNTL … #define regHDMISTREAMCLK_CNTL_BASE_IDX … #define regDCCG_GATE_DISABLE_CNTL3 … #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX … #define regHDMISTREAMCLK0_DTO_PARAM … #define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX … // base address: 0x0 // base address: 0x30 // addressBlock: dcn_dcec_dmu_fgsec_dispdec // base address: 0x0 #define regDMCUB_RBBMIF_SEC_CNTL … #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dmu_rbbmif_dispdec // base address: 0x0 #define regRBBMIF_TIMEOUT … #define regRBBMIF_TIMEOUT_BASE_IDX … #define regRBBMIF_STATUS … #define regRBBMIF_STATUS_BASE_IDX … #define regRBBMIF_STATUS_2 … #define regRBBMIF_STATUS_2_BASE_IDX … #define regRBBMIF_INT_STATUS … #define regRBBMIF_INT_STATUS_BASE_IDX … #define regRBBMIF_TIMEOUT_DIS … #define regRBBMIF_TIMEOUT_DIS_BASE_IDX … #define regRBBMIF_TIMEOUT_DIS_2 … #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX … #define regRBBMIF_STATUS_FLAG … #define regRBBMIF_STATUS_FLAG_BASE_IDX … // addressBlock: dcn_dcec_dmu_ihc_dispdec // base address: 0x0 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE … #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX … #define regDC_GPU_TIMER_START_POSITION_VSTARTUP … #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX … #define regDC_GPU_TIMER_READ … #define regDC_GPU_TIMER_READ_BASE_IDX … #define regDC_GPU_TIMER_READ_CNTL … #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX … #define regDISP_INTERRUPT_STATUS … #define regDISP_INTERRUPT_STATUS_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE … #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE2 … #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE3 … #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE4 … #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE5 … #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE6 … #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE7 … #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE8 … #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE9 … #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE10 … #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE11 … #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE12 … #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE13 … #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE14 … #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE15 … #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE16 … #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE17 … #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE18 … #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE19 … #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE20 … #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE21 … #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE22 … #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX … #define regDC_GPU_TIMER_START_POSITION_VREADY … #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX … #define regDC_GPU_TIMER_START_POSITION_FLIP … #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX … #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK … #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX … #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY … #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE23 … #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE24 … #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX … #define regDISP_INTERRUPT_STATUS_CONTINUE25 … #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX … #define regDCCG_INTERRUPT_DEST … #define regDCCG_INTERRUPT_DEST_BASE_IDX … #define regDMU_INTERRUPT_DEST … #define regDMU_INTERRUPT_DEST_BASE_IDX … #define regDMU_INTERRUPT_DEST2 … #define regDMU_INTERRUPT_DEST2_BASE_IDX … #define regDCPG_INTERRUPT_DEST … #define regDCPG_INTERRUPT_DEST_BASE_IDX … #define regDCPG_INTERRUPT_DEST2 … #define regDCPG_INTERRUPT_DEST2_BASE_IDX … #define regMMHUBBUB_INTERRUPT_DEST … #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX … #define regWB_INTERRUPT_DEST … #define regWB_INTERRUPT_DEST_BASE_IDX … #define regDCHUB_INTERRUPT_DEST … #define regDCHUB_INTERRUPT_DEST_BASE_IDX … #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST … #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX … #define regDCHUB_INTERRUPT_DEST2 … #define regDCHUB_INTERRUPT_DEST2_BASE_IDX … #define regDPP_PERFCOUNTER_INTERRUPT_DEST … #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX … #define regMPC_INTERRUPT_DEST … #define regMPC_INTERRUPT_DEST_BASE_IDX … #define regOPP_INTERRUPT_DEST … #define regOPP_INTERRUPT_DEST_BASE_IDX … #define regOPTC_INTERRUPT_DEST … #define regOPTC_INTERRUPT_DEST_BASE_IDX … #define regOTG0_INTERRUPT_DEST … #define regOTG0_INTERRUPT_DEST_BASE_IDX … #define regOTG1_INTERRUPT_DEST … #define regOTG1_INTERRUPT_DEST_BASE_IDX … #define regOTG2_INTERRUPT_DEST … #define regOTG2_INTERRUPT_DEST_BASE_IDX … #define regOTG3_INTERRUPT_DEST … #define regOTG3_INTERRUPT_DEST_BASE_IDX … #define regOTG4_INTERRUPT_DEST … #define regOTG4_INTERRUPT_DEST_BASE_IDX … #define regOTG5_INTERRUPT_DEST … #define regOTG5_INTERRUPT_DEST_BASE_IDX … #define regDIG_INTERRUPT_DEST … #define regDIG_INTERRUPT_DEST_BASE_IDX … #define regI2C_DDC_HPD_INTERRUPT_DEST … #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX … #define regHDCP_INTERRUPT_DEST … #define regHDCP_INTERRUPT_DEST_BASE_IDX … #define regDIO_INTERRUPT_DEST … #define regDIO_INTERRUPT_DEST_BASE_IDX … #define regDCIO_INTERRUPT_DEST … #define regDCIO_INTERRUPT_DEST_BASE_IDX … #define regHPD_INTERRUPT_DEST … #define regHPD_INTERRUPT_DEST_BASE_IDX … #define regAZ_INTERRUPT_DEST … #define regAZ_INTERRUPT_DEST_BASE_IDX … #define regAUX_INTERRUPT_DEST … #define regAUX_INTERRUPT_DEST_BASE_IDX … #define regDSC_INTERRUPT_DEST … #define regDSC_INTERRUPT_DEST_BASE_IDX … #define regHPO_INTERRUPT_DEST … #define regHPO_INTERRUPT_DEST_BASE_IDX … // addressBlock: dcn_dcec_dmu_dmu_misc_dispdec // base address: 0x0 #define regCC_DC_PIPE_DIS … #define regCC_DC_PIPE_DIS_BASE_IDX … #define regDMU_CLK_CNTL … #define regDMU_CLK_CNTL_BASE_IDX … #define regDMCUB_SMU_INTERRUPT_CNTL … #define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX … #define regSMU_INTERRUPT_CONTROL … #define regSMU_INTERRUPT_CONTROL_BASE_IDX … #define regDMU_MISC_ALLOW_DS_FORCE … #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX … #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG … #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG … #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX … // addressBlock: dcn_dcec_dmu_dc_pg_dispdec // base address: 0x0 #define regDOMAIN0_PG_CONFIG … #define regDOMAIN0_PG_CONFIG_BASE_IDX … #define regDOMAIN0_PG_STATUS … #define regDOMAIN0_PG_STATUS_BASE_IDX … #define regDOMAIN1_PG_CONFIG … #define regDOMAIN1_PG_CONFIG_BASE_IDX … #define regDOMAIN1_PG_STATUS … #define regDOMAIN1_PG_STATUS_BASE_IDX … #define regDOMAIN2_PG_CONFIG … #define regDOMAIN2_PG_CONFIG_BASE_IDX … #define regDOMAIN2_PG_STATUS … #define regDOMAIN2_PG_STATUS_BASE_IDX … #define regDOMAIN3_PG_CONFIG … #define regDOMAIN3_PG_CONFIG_BASE_IDX … #define regDOMAIN3_PG_STATUS … #define regDOMAIN3_PG_STATUS_BASE_IDX … #define regDOMAIN16_PG_CONFIG … #define regDOMAIN16_PG_CONFIG_BASE_IDX … #define regDOMAIN16_PG_STATUS … #define regDOMAIN16_PG_STATUS_BASE_IDX … #define regDOMAIN17_PG_CONFIG … #define regDOMAIN17_PG_CONFIG_BASE_IDX … #define regDOMAIN17_PG_STATUS … #define regDOMAIN17_PG_STATUS_BASE_IDX … #define regDOMAIN18_PG_CONFIG … #define regDOMAIN18_PG_CONFIG_BASE_IDX … #define regDOMAIN18_PG_STATUS … #define regDOMAIN18_PG_STATUS_BASE_IDX … #define regDOMAIN19_PG_CONFIG … #define regDOMAIN19_PG_CONFIG_BASE_IDX … #define regDOMAIN19_PG_STATUS … #define regDOMAIN19_PG_STATUS_BASE_IDX … #define regDOMAIN22_PG_CONFIG … #define regDOMAIN22_PG_CONFIG_BASE_IDX … #define regDOMAIN22_PG_STATUS … #define regDOMAIN22_PG_STATUS_BASE_IDX … #define regDOMAIN23_PG_CONFIG … #define regDOMAIN23_PG_CONFIG_BASE_IDX … #define regDOMAIN23_PG_STATUS … #define regDOMAIN23_PG_STATUS_BASE_IDX … #define regDOMAIN24_PG_CONFIG … #define regDOMAIN24_PG_CONFIG_BASE_IDX … #define regDOMAIN24_PG_STATUS … #define regDOMAIN24_PG_STATUS_BASE_IDX … #define regDOMAIN25_PG_CONFIG … #define regDOMAIN25_PG_CONFIG_BASE_IDX … #define regDOMAIN25_PG_STATUS … #define regDOMAIN25_PG_STATUS_BASE_IDX … #define regDCPG_INTERRUPT_STATUS … #define regDCPG_INTERRUPT_STATUS_BASE_IDX … #define regDCPG_INTERRUPT_STATUS_2 … #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX … #define regDCPG_INTERRUPT_STATUS_3 … #define regDCPG_INTERRUPT_STATUS_3_BASE_IDX … #define regDCPG_INTERRUPT_CONTROL_1 … #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX … #define regDCPG_INTERRUPT_CONTROL_2 … #define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX … #define regDCPG_INTERRUPT_CONTROL_3 … #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX … #define regDC_IP_REQUEST_CNTL … #define regDC_IP_REQUEST_CNTL_BASE_IDX … #define regDC_PGCNTL_STATUS_REG … #define regDC_PGCNTL_STATUS_REG_BASE_IDX … #define regLONO_MEM_PWR_REQ_CNTL … #define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dmu_dmcub_dispdec // base address: 0x0 #define regDMCUB_REGION0_OFFSET … #define regDMCUB_REGION0_OFFSET_BASE_IDX … #define regDMCUB_REGION0_OFFSET_HIGH … #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION1_OFFSET … #define regDMCUB_REGION1_OFFSET_BASE_IDX … #define regDMCUB_REGION1_OFFSET_HIGH … #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION2_OFFSET … #define regDMCUB_REGION2_OFFSET_BASE_IDX … #define regDMCUB_REGION2_OFFSET_HIGH … #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION4_OFFSET … #define regDMCUB_REGION4_OFFSET_BASE_IDX … #define regDMCUB_REGION4_OFFSET_HIGH … #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION5_OFFSET … #define regDMCUB_REGION5_OFFSET_BASE_IDX … #define regDMCUB_REGION5_OFFSET_HIGH … #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION6_OFFSET … #define regDMCUB_REGION6_OFFSET_BASE_IDX … #define regDMCUB_REGION6_OFFSET_HIGH … #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION7_OFFSET … #define regDMCUB_REGION7_OFFSET_BASE_IDX … #define regDMCUB_REGION7_OFFSET_HIGH … #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION0_TOP_ADDRESS … #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION1_TOP_ADDRESS … #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION2_TOP_ADDRESS … #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION4_TOP_ADDRESS … #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION5_TOP_ADDRESS … #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION6_TOP_ADDRESS … #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION7_TOP_ADDRESS … #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW0_BASE_ADDRESS … #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW1_BASE_ADDRESS … #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW2_BASE_ADDRESS … #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW3_BASE_ADDRESS … #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW4_BASE_ADDRESS … #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW5_BASE_ADDRESS … #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW6_BASE_ADDRESS … #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW7_BASE_ADDRESS … #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW0_TOP_ADDRESS … #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW1_TOP_ADDRESS … #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW2_TOP_ADDRESS … #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW3_TOP_ADDRESS … #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW4_TOP_ADDRESS … #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW5_TOP_ADDRESS … #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW6_TOP_ADDRESS … #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW7_TOP_ADDRESS … #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX … #define regDMCUB_REGION3_CW0_OFFSET … #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW0_OFFSET_HIGH … #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW1_OFFSET … #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW1_OFFSET_HIGH … #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW2_OFFSET … #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW2_OFFSET_HIGH … #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW3_OFFSET … #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW3_OFFSET_HIGH … #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW4_OFFSET … #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW4_OFFSET_HIGH … #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW5_OFFSET … #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW5_OFFSET_HIGH … #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW6_OFFSET … #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW6_OFFSET_HIGH … #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX … #define regDMCUB_REGION3_CW7_OFFSET … #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX … #define regDMCUB_REGION3_CW7_OFFSET_HIGH … #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX … #define regDMCUB_INTERRUPT_ENABLE … #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX … #define regDMCUB_INTERRUPT_ACK … #define regDMCUB_INTERRUPT_ACK_BASE_IDX … #define regDMCUB_INTERRUPT_STATUS … #define regDMCUB_INTERRUPT_STATUS_BASE_IDX … #define regDMCUB_INTERRUPT_TYPE … #define regDMCUB_INTERRUPT_TYPE_BASE_IDX … #define regDMCUB_EXT_INTERRUPT_STATUS … #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX … #define regDMCUB_EXT_INTERRUPT_CTXID … #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX … #define regDMCUB_EXT_INTERRUPT_ACK … #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX … #define regDMCUB_INST_FETCH_FAULT_ADDR … #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX … #define regDMCUB_DATA_WRITE_FAULT_ADDR … #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX … #define regDMCUB_SEC_CNTL … #define regDMCUB_SEC_CNTL_BASE_IDX … #define regDMCUB_MEM_CNTL … #define regDMCUB_MEM_CNTL_BASE_IDX … #define regDMCUB_INBOX0_BASE_ADDRESS … #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX … #define regDMCUB_INBOX0_SIZE … #define regDMCUB_INBOX0_SIZE_BASE_IDX … #define regDMCUB_INBOX0_WPTR … #define regDMCUB_INBOX0_WPTR_BASE_IDX … #define regDMCUB_INBOX0_RPTR … #define regDMCUB_INBOX0_RPTR_BASE_IDX … #define regDMCUB_INBOX1_BASE_ADDRESS … #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX … #define regDMCUB_INBOX1_SIZE … #define regDMCUB_INBOX1_SIZE_BASE_IDX … #define regDMCUB_INBOX1_WPTR … #define regDMCUB_INBOX1_WPTR_BASE_IDX … #define regDMCUB_INBOX1_RPTR … #define regDMCUB_INBOX1_RPTR_BASE_IDX … #define regDMCUB_OUTBOX0_BASE_ADDRESS … #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX … #define regDMCUB_OUTBOX0_SIZE … #define regDMCUB_OUTBOX0_SIZE_BASE_IDX … #define regDMCUB_OUTBOX0_WPTR … #define regDMCUB_OUTBOX0_WPTR_BASE_IDX … #define regDMCUB_OUTBOX0_RPTR … #define regDMCUB_OUTBOX0_RPTR_BASE_IDX … #define regDMCUB_OUTBOX1_BASE_ADDRESS … #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX … #define regDMCUB_OUTBOX1_SIZE … #define regDMCUB_OUTBOX1_SIZE_BASE_IDX … #define regDMCUB_OUTBOX1_WPTR … #define regDMCUB_OUTBOX1_WPTR_BASE_IDX … #define regDMCUB_OUTBOX1_RPTR … #define regDMCUB_OUTBOX1_RPTR_BASE_IDX … #define regDMCUB_TIMER_TRIGGER0 … #define regDMCUB_TIMER_TRIGGER0_BASE_IDX … #define regDMCUB_TIMER_TRIGGER1 … #define regDMCUB_TIMER_TRIGGER1_BASE_IDX … #define regDMCUB_TIMER_WINDOW … #define regDMCUB_TIMER_WINDOW_BASE_IDX … #define regDMCUB_SCRATCH0 … #define regDMCUB_SCRATCH0_BASE_IDX … #define regDMCUB_SCRATCH1 … #define regDMCUB_SCRATCH1_BASE_IDX … #define regDMCUB_SCRATCH2 … #define regDMCUB_SCRATCH2_BASE_IDX … #define regDMCUB_SCRATCH3 … #define regDMCUB_SCRATCH3_BASE_IDX … #define regDMCUB_SCRATCH4 … #define regDMCUB_SCRATCH4_BASE_IDX … #define regDMCUB_SCRATCH5 … #define regDMCUB_SCRATCH5_BASE_IDX … #define regDMCUB_SCRATCH6 … #define regDMCUB_SCRATCH6_BASE_IDX … #define regDMCUB_SCRATCH7 … #define regDMCUB_SCRATCH7_BASE_IDX … #define regDMCUB_SCRATCH8 … #define regDMCUB_SCRATCH8_BASE_IDX … #define regDMCUB_SCRATCH9 … #define regDMCUB_SCRATCH9_BASE_IDX … #define regDMCUB_SCRATCH10 … #define regDMCUB_SCRATCH10_BASE_IDX … #define regDMCUB_SCRATCH11 … #define regDMCUB_SCRATCH11_BASE_IDX … #define regDMCUB_SCRATCH12 … #define regDMCUB_SCRATCH12_BASE_IDX … #define regDMCUB_SCRATCH13 … #define regDMCUB_SCRATCH13_BASE_IDX … #define regDMCUB_SCRATCH14 … #define regDMCUB_SCRATCH14_BASE_IDX … #define regDMCUB_SCRATCH15 … #define regDMCUB_SCRATCH15_BASE_IDX … #define regDMCUB_SCRATCH16 … #define regDMCUB_SCRATCH16_BASE_IDX … #define regDMCUB_SCRATCH17 … #define regDMCUB_SCRATCH17_BASE_IDX … #define regDMCUB_SCRATCH18 … #define regDMCUB_SCRATCH18_BASE_IDX … #define regDMCUB_CNTL … #define regDMCUB_CNTL_BASE_IDX … #define regDMCUB_GPINT_DATAIN0 … #define regDMCUB_GPINT_DATAIN0_BASE_IDX … #define regDMCUB_GPINT_DATAIN1 … #define regDMCUB_GPINT_DATAIN1_BASE_IDX … #define regDMCUB_GPINT_DATAOUT … #define regDMCUB_GPINT_DATAOUT_BASE_IDX … #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR … #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX … #define regDMCUB_LS_WAKE_INT_ENABLE … #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX … #define regDMCUB_MEM_PWR_CNTL … #define regDMCUB_MEM_PWR_CNTL_BASE_IDX … #define regDMCUB_TIMER_CURRENT … #define regDMCUB_TIMER_CURRENT_BASE_IDX … #define regDMCUB_PROC_ID … #define regDMCUB_PROC_ID_BASE_IDX … #define regDMCUB_CNTL2 … #define regDMCUB_CNTL2_BASE_IDX … #define regDMCUB_GPINT_DATAIN2 … #define regDMCUB_GPINT_DATAIN2_BASE_IDX … #define regDMCUB_GPINT_DATAIN3 … #define regDMCUB_GPINT_DATAIN3_BASE_IDX … #define regDMCUB_GPINT_DATAIN4 … #define regDMCUB_GPINT_DATAIN4_BASE_IDX … #define regDMCUB_GPINT_DATAIN5 … #define regDMCUB_GPINT_DATAIN5_BASE_IDX … #define regDMCUB_GPINT_DATAIN6 … #define regDMCUB_GPINT_DATAIN6_BASE_IDX … #define regDMCUB_REGION3_TMR_AXI_SPACE … #define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX … #define regDMCUB_SCRATCH19 … #define regDMCUB_SCRATCH19_BASE_IDX … #define regDMCUB_SCRATCH20 … #define regDMCUB_SCRATCH20_BASE_IDX … #define regDMCUB_SCRATCH21 … #define regDMCUB_SCRATCH21_BASE_IDX … #define regDMCUB_SCRATCH22 … #define regDMCUB_SCRATCH22_BASE_IDX … #define regDMCUB_SCRATCH23 … #define regDMCUB_SCRATCH23_BASE_IDX … #define regHOST_INTERRUPT_CSR … #define regHOST_INTERRUPT_CSR_BASE_IDX … #define regDMCUB_REG_INBOX0_RDY … #define regDMCUB_REG_INBOX0_RDY_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG0 … #define regDMCUB_REG_INBOX0_MSG0_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG1 … #define regDMCUB_REG_INBOX0_MSG1_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG2 … #define regDMCUB_REG_INBOX0_MSG2_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG3 … #define regDMCUB_REG_INBOX0_MSG3_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG4 … #define regDMCUB_REG_INBOX0_MSG4_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG5 … #define regDMCUB_REG_INBOX0_MSG5_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG6 … #define regDMCUB_REG_INBOX0_MSG6_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG7 … #define regDMCUB_REG_INBOX0_MSG7_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG8 … #define regDMCUB_REG_INBOX0_MSG8_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG9 … #define regDMCUB_REG_INBOX0_MSG9_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG10 … #define regDMCUB_REG_INBOX0_MSG10_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG11 … #define regDMCUB_REG_INBOX0_MSG11_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG12 … #define regDMCUB_REG_INBOX0_MSG12_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG13 … #define regDMCUB_REG_INBOX0_MSG13_BASE_IDX … #define regDMCUB_REG_INBOX0_MSG14 … #define regDMCUB_REG_INBOX0_MSG14_BASE_IDX … #define regDMCUB_REG_INBOX0_RSP … #define regDMCUB_REG_INBOX0_RSP_BASE_IDX … #define regDMCUB_REG_OUTBOX0_RDY … #define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX … #define regDMCUB_REG_OUTBOX0_MSG0 … #define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX … #define regDMCUB_REG_OUTBOX0_RSP … #define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX … #define regDMCUB_REG_INBOX1_RDY … #define regDMCUB_REG_INBOX1_RDY_BASE_IDX … #define regDMCUB_REG_INBOX1_MSG0 … #define regDMCUB_REG_INBOX1_MSG0_BASE_IDX … #define regDMCUB_REG_INBOX1_MSG1 … #define regDMCUB_REG_INBOX1_MSG1_BASE_IDX … #define regDMCUB_REG_INBOX1_RSP … #define regDMCUB_REG_INBOX1_RSP_BASE_IDX … #define regDMCUB_REG_INBOX2_RDY … #define regDMCUB_REG_INBOX2_RDY_BASE_IDX … #define regDMCUB_REG_INBOX2_MSG0 … #define regDMCUB_REG_INBOX2_MSG0_BASE_IDX … #define regDMCUB_REG_INBOX2_MSG1 … #define regDMCUB_REG_INBOX2_MSG1_BASE_IDX … #define regDMCUB_REG_INBOX2_RSP … #define regDMCUB_REG_INBOX2_RSP_BASE_IDX … #define regDMCUB_REG_INBOX3_RDY … #define regDMCUB_REG_INBOX3_RDY_BASE_IDX … #define regDMCUB_REG_INBOX3_MSG0 … #define regDMCUB_REG_INBOX3_MSG0_BASE_IDX … #define regDMCUB_REG_INBOX3_MSG1 … #define regDMCUB_REG_INBOX3_MSG1_BASE_IDX … #define regDMCUB_REG_INBOX3_RSP … #define regDMCUB_REG_INBOX3_RSP_BASE_IDX … #define regDMCUB_REG_INBOX4_RDY … #define regDMCUB_REG_INBOX4_RDY_BASE_IDX … #define regDMCUB_REG_INBOX4_MSG0 … #define regDMCUB_REG_INBOX4_MSG0_BASE_IDX … #define regDMCUB_REG_INBOX4_MSG1 … #define regDMCUB_REG_INBOX4_MSG1_BASE_IDX … #define regDMCUB_REG_INBOX4_RSP … #define regDMCUB_REG_INBOX4_RSP_BASE_IDX … // addressBlock: dcn_dcec_wb0_dispdec_dwb_top_dispdec // base address: 0x0 #define regDWB_ENABLE_CLK_CTRL … #define regDWB_ENABLE_CLK_CTRL_BASE_IDX … #define regDWB_MEM_PWR_CTRL … #define regDWB_MEM_PWR_CTRL_BASE_IDX … #define regFC_MODE_CTRL … #define regFC_MODE_CTRL_BASE_IDX … #define regFC_FLOW_CTRL … #define regFC_FLOW_CTRL_BASE_IDX … #define regFC_WINDOW_START … #define regFC_WINDOW_START_BASE_IDX … #define regFC_WINDOW_SIZE … #define regFC_WINDOW_SIZE_BASE_IDX … #define regFC_SOURCE_SIZE … #define regFC_SOURCE_SIZE_BASE_IDX … #define regDWB_UPDATE_CTRL … #define regDWB_UPDATE_CTRL_BASE_IDX … #define regDWB_CRC_CTRL … #define regDWB_CRC_CTRL_BASE_IDX … #define regDWB_CRC_MASK_R_G … #define regDWB_CRC_MASK_R_G_BASE_IDX … #define regDWB_CRC_MASK_B_A … #define regDWB_CRC_MASK_B_A_BASE_IDX … #define regDWB_CRC_VAL_R_G … #define regDWB_CRC_VAL_R_G_BASE_IDX … #define regDWB_CRC_VAL_B_A … #define regDWB_CRC_VAL_B_A_BASE_IDX … #define regDWB_OUT_CTRL … #define regDWB_OUT_CTRL_BASE_IDX … #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN … #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX … #define regDWB_MMHUBBUB_BACKPRESSURE_CNT … #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX … #define regDWB_HOST_READ_CONTROL … #define regDWB_HOST_READ_CONTROL_BASE_IDX … #define regDWB_OVERFLOW_STATUS … #define regDWB_OVERFLOW_STATUS_BASE_IDX … #define regDWB_OVERFLOW_COUNTER … #define regDWB_OVERFLOW_COUNTER_BASE_IDX … #define regDWB_SOFT_RESET … #define regDWB_SOFT_RESET_BASE_IDX … #define regDWB_DEBUG_CTRL … #define regDWB_DEBUG_CTRL_BASE_IDX … #define regDWB_DEBUG … #define regDWB_DEBUG_BASE_IDX … // addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec // base address: 0x0 #define regDWB_HDR_MULT_COEF … #define regDWB_HDR_MULT_COEF_BASE_IDX … #define regDWB_GAMUT_REMAP_MODE … #define regDWB_GAMUT_REMAP_MODE_BASE_IDX … #define regDWB_GAMUT_REMAP_COEF_FORMAT … #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regDWB_GAMUT_REMAPA_C11_C12 … #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX … #define regDWB_GAMUT_REMAPA_C13_C14 … #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX … #define regDWB_GAMUT_REMAPA_C21_C22 … #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX … #define regDWB_GAMUT_REMAPA_C23_C24 … #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX … #define regDWB_GAMUT_REMAPA_C31_C32 … #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX … #define regDWB_GAMUT_REMAPA_C33_C34 … #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX … #define regDWB_GAMUT_REMAPB_C11_C12 … #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX … #define regDWB_GAMUT_REMAPB_C13_C14 … #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX … #define regDWB_GAMUT_REMAPB_C21_C22 … #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX … #define regDWB_GAMUT_REMAPB_C23_C24 … #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX … #define regDWB_GAMUT_REMAPB_C31_C32 … #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX … #define regDWB_GAMUT_REMAPB_C33_C34 … #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX … #define regDWB_OGAM_CONTROL … #define regDWB_OGAM_CONTROL_BASE_IDX … #define regDWB_OGAM_LUT_INDEX … #define regDWB_OGAM_LUT_INDEX_BASE_IDX … #define regDWB_OGAM_LUT_DATA … #define regDWB_OGAM_LUT_DATA_BASE_IDX … #define regDWB_OGAM_LUT_CONTROL … #define regDWB_OGAM_LUT_CONTROL_BASE_IDX … #define regDWB_OGAM_RAMA_START_CNTL_B … #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMA_START_CNTL_G … #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMA_START_CNTL_R … #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMA_START_BASE_CNTL_B … #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMA_START_BASE_CNTL_G … #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMA_START_BASE_CNTL_R … #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R … #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL1_B … #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL2_B … #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL1_G … #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL2_G … #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL1_R … #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define regDWB_OGAM_RAMA_END_CNTL2_R … #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define regDWB_OGAM_RAMA_OFFSET_B … #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX … #define regDWB_OGAM_RAMA_OFFSET_G … #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX … #define regDWB_OGAM_RAMA_OFFSET_R … #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_0_1 … #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_2_3 … #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_4_5 … #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_6_7 … #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_8_9 … #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_10_11 … #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_12_13 … #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_14_15 … #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_16_17 … #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_18_19 … #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_20_21 … #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_22_23 … #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_24_25 … #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_26_27 … #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_28_29 … #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_30_31 … #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX … #define regDWB_OGAM_RAMA_REGION_32_33 … #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX … #define regDWB_OGAM_RAMB_START_CNTL_B … #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMB_START_CNTL_G … #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMB_START_CNTL_R … #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMB_START_BASE_CNTL_B … #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regDWB_OGAM_RAMB_START_BASE_CNTL_G … #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regDWB_OGAM_RAMB_START_BASE_CNTL_R … #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R … #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL1_B … #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL2_B … #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL1_G … #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL2_G … #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL1_R … #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define regDWB_OGAM_RAMB_END_CNTL2_R … #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define regDWB_OGAM_RAMB_OFFSET_B … #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX … #define regDWB_OGAM_RAMB_OFFSET_G … #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX … #define regDWB_OGAM_RAMB_OFFSET_R … #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_0_1 … #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_2_3 … #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_4_5 … #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_6_7 … #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_8_9 … #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_10_11 … #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_12_13 … #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_14_15 … #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_16_17 … #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_18_19 … #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_20_21 … #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_22_23 … #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_24_25 … #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_26_27 … #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_28_29 … #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_30_31 … #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX … #define regDWB_OGAM_RAMB_REGION_32_33 … #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dcn_dcec_mmhubbub_mcif_wb0_dispdec // base address: 0x0 #define regMCIF_WB_BUFMGR_SW_CONTROL … #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define regMCIF_WB_BUFMGR_STATUS … #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX … #define regMCIF_WB_BUF_PITCH … #define regMCIF_WB_BUF_PITCH_BASE_IDX … #define regMCIF_WB_BUF_1_STATUS … #define regMCIF_WB_BUF_1_STATUS_BASE_IDX … #define regMCIF_WB_BUF_1_STATUS2 … #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX … #define regMCIF_WB_BUF_2_STATUS … #define regMCIF_WB_BUF_2_STATUS_BASE_IDX … #define regMCIF_WB_BUF_2_STATUS2 … #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX … #define regMCIF_WB_BUF_3_STATUS … #define regMCIF_WB_BUF_3_STATUS_BASE_IDX … #define regMCIF_WB_BUF_3_STATUS2 … #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX … #define regMCIF_WB_BUF_4_STATUS … #define regMCIF_WB_BUF_4_STATUS_BASE_IDX … #define regMCIF_WB_BUF_4_STATUS2 … #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX … #define regMCIF_WB_ARBITRATION_CONTROL … #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define regMCIF_WB_SCLK_CHANGE … #define regMCIF_WB_SCLK_CHANGE_BASE_IDX … #define regMCIF_WB_TEST_DEBUG_INDEX … #define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX … #define regMCIF_WB_TEST_DEBUG_DATA … #define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX … #define regMCIF_WB_BUF_1_ADDR_Y … #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define regMCIF_WB_BUF_1_ADDR_C … #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define regMCIF_WB_BUF_2_ADDR_Y … #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define regMCIF_WB_BUF_2_ADDR_C … #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define regMCIF_WB_BUF_3_ADDR_Y … #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define regMCIF_WB_BUF_3_ADDR_C … #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define regMCIF_WB_BUF_4_ADDR_Y … #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define regMCIF_WB_BUF_4_ADDR_C … #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define regMCIF_WB_BUFMGR_VCE_CONTROL … #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define regMCIF_WB_NB_PSTATE_CONTROL … #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define regMCIF_WB_CLOCK_GATER_CONTROL … #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define regMCIF_WB_SELF_REFRESH_CONTROL … #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define regMULTI_LEVEL_QOS_CTRL … #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX … #define regMCIF_WB_SECURITY_LEVEL … #define regMCIF_WB_SECURITY_LEVEL_BASE_IDX … #define regMCIF_WB_BUF_LUMA_SIZE … #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define regMCIF_WB_BUF_CHROMA_SIZE … #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … #define regMCIF_WB_BUF_1_ADDR_Y_HIGH … #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX … #define regMCIF_WB_BUF_1_ADDR_C_HIGH … #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX … #define regMCIF_WB_BUF_2_ADDR_Y_HIGH … #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX … #define regMCIF_WB_BUF_2_ADDR_C_HIGH … #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX … #define regMCIF_WB_BUF_3_ADDR_Y_HIGH … #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX … #define regMCIF_WB_BUF_3_ADDR_C_HIGH … #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX … #define regMCIF_WB_BUF_4_ADDR_Y_HIGH … #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX … #define regMCIF_WB_BUF_4_ADDR_C_HIGH … #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX … #define regMCIF_WB_BUF_1_RESOLUTION … #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX … #define regMCIF_WB_BUF_2_RESOLUTION … #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX … #define regMCIF_WB_BUF_3_RESOLUTION … #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX … #define regMCIF_WB_BUF_4_RESOLUTION … #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX … #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI … #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX … #define regMCIF_WB_VMID_CONTROL … #define regMCIF_WB_VMID_CONTROL_BASE_IDX … #define regMCIF_WB_MIN_TTO … #define regMCIF_WB_MIN_TTO_BASE_IDX … // addressBlock: dcn_dcec_mmhubbub_mmhubbub_dispdec // base address: 0x0 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define regMCIF_WB_WATERMARK … #define regMCIF_WB_WATERMARK_BASE_IDX … #define regMMHUBBUB_WARMUP_CONFIG … #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX … #define regMMHUBBUB_WARMUP_CONTROL_STATUS … #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX … #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW … #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX … #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH … #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX … #define regMMHUBBUB_WARMUP_ADDR_REGION … #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX … #define regMMHUBBUB_MIN_TTO … #define regMMHUBBUB_MIN_TTO_BASE_IDX … #define regMMHUBBUB_CTRL … #define regMMHUBBUB_CTRL_BASE_IDX … #define regWBIF_SMU_WM_CONTROL … #define regWBIF_SMU_WM_CONTROL_BASE_IDX … #define regWBIF0_MISC_CTRL … #define regWBIF0_MISC_CTRL_BASE_IDX … #define regWBIF0_PHASE0_OUTSTANDING_COUNTER … #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define regWBIF0_PHASE1_OUTSTANDING_COUNTER … #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define regMMHUBBUB_MEM_PWR_STATUS … #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX … #define regMMHUBBUB_MEM_PWR_CNTL … #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX … #define regMMHUBBUB_CLOCK_CNTL … #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX … #define regMMHUBBUB_SOFT_RESET … #define regMMHUBBUB_SOFT_RESET_BASE_IDX … #define regDMU_IF_ERR_STATUS … #define regDMU_IF_ERR_STATUS_BASE_IDX … #define regMMHUBBUB_CLIENT_UNIT_ID … #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX … #define regMMHUBBUB_WARMUP_VMID_CONTROL … #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0controller_dispdec // base address: 0x0 #define regAZALIA_CONTROLLER_CLOCK_GATING … #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX … #define regAZALIA_AUDIO_DTO … #define regAZALIA_AUDIO_DTO_BASE_IDX … #define regAZALIA_AUDIO_DTO_CONTROL … #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX … #define regAZALIA_SOCCLK_CONTROL … #define regAZALIA_SOCCLK_CONTROL_BASE_IDX … #define regAZALIA_UNDERFLOW_FILLER_SAMPLE … #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX … #define regAZALIA_DATA_DMA_CONTROL … #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX … #define regAZALIA_BDL_DMA_CONTROL … #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX … #define regAZALIA_RIRB_AND_DP_CONTROL … #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX … #define regAZALIA_CORB_DMA_CONTROL … #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX … #define regAZALIA_GLOBAL_CAPABILITIES … #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX … #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY … #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL … #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX … #define regAZALIA_INPUT_PAYLOAD_CAPABILITY … #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define regAZALIA_INPUT_CRC0_CONTROL0 … #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX … #define regAZALIA_INPUT_CRC0_CONTROL1 … #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX … #define regAZALIA_INPUT_CRC0_CONTROL2 … #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX … #define regAZALIA_INPUT_CRC0_CONTROL3 … #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX … #define regAZALIA_INPUT_CRC0_RESULT … #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX … #define regAZALIA_INPUT_CRC1_CONTROL0 … #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX … #define regAZALIA_INPUT_CRC1_CONTROL1 … #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX … #define regAZALIA_INPUT_CRC1_CONTROL2 … #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX … #define regAZALIA_INPUT_CRC1_CONTROL3 … #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX … #define regAZALIA_INPUT_CRC1_RESULT … #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX … #define regAZALIA_CRC0_CONTROL0 … #define regAZALIA_CRC0_CONTROL0_BASE_IDX … #define regAZALIA_CRC0_CONTROL1 … #define regAZALIA_CRC0_CONTROL1_BASE_IDX … #define regAZALIA_CRC0_CONTROL2 … #define regAZALIA_CRC0_CONTROL2_BASE_IDX … #define regAZALIA_CRC0_CONTROL3 … #define regAZALIA_CRC0_CONTROL3_BASE_IDX … #define regAZALIA_CRC0_RESULT … #define regAZALIA_CRC0_RESULT_BASE_IDX … #define regAZALIA_CRC1_CONTROL0 … #define regAZALIA_CRC1_CONTROL0_BASE_IDX … #define regAZALIA_CRC1_CONTROL1 … #define regAZALIA_CRC1_CONTROL1_BASE_IDX … #define regAZALIA_CRC1_CONTROL2 … #define regAZALIA_CRC1_CONTROL2_BASE_IDX … #define regAZALIA_CRC1_CONTROL3 … #define regAZALIA_CRC1_CONTROL3_BASE_IDX … #define regAZALIA_CRC1_RESULT … #define regAZALIA_CRC1_RESULT_BASE_IDX … #define regAZALIA_SOFT_RESET … #define regAZALIA_SOFT_RESET_BASE_IDX … #define regAZALIA_MEM_PWR_CTRL … #define regAZALIA_MEM_PWR_CTRL_BASE_IDX … #define regAZALIA_MEM_PWR_STATUS … #define regAZALIA_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0root_dispdec // base address: 0x0 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX … #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID … #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX … #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL … #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL … #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX … #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY … #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … #define regREG_DC_AUDIO_PORT_CONNECTIVITY … #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … // addressBlock: dcn_dcec_hda_az_misc_dispdec // base address: 0x0 #define regAZ_CLOCK_CNTL … #define regAZ_CLOCK_CNTL_BASE_IDX … #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL … #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX … #define regAZ_STRAPS … #define regAZ_STRAPS_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream0_dispdec // base address: 0x0 #define regAZF0STREAM0_AZALIA_STREAM_INDEX … #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM0_AZALIA_STREAM_DATA … #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream1_dispdec // base address: 0x8 #define regAZF0STREAM1_AZALIA_STREAM_INDEX … #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM1_AZALIA_STREAM_DATA … #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream2_dispdec // base address: 0x10 #define regAZF0STREAM2_AZALIA_STREAM_INDEX … #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM2_AZALIA_STREAM_DATA … #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream3_dispdec // base address: 0x18 #define regAZF0STREAM3_AZALIA_STREAM_INDEX … #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM3_AZALIA_STREAM_DATA … #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream4_dispdec // base address: 0x20 #define regAZF0STREAM4_AZALIA_STREAM_INDEX … #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM4_AZALIA_STREAM_DATA … #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream5_dispdec // base address: 0x28 #define regAZF0STREAM5_AZALIA_STREAM_INDEX … #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM5_AZALIA_STREAM_DATA … #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream6_dispdec // base address: 0x30 #define regAZF0STREAM6_AZALIA_STREAM_INDEX … #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM6_AZALIA_STREAM_DATA … #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream7_dispdec // base address: 0x38 #define regAZF0STREAM7_AZALIA_STREAM_INDEX … #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM7_AZALIA_STREAM_DATA … #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream8_dispdec // base address: 0x320 #define regAZF0STREAM8_AZALIA_STREAM_INDEX … #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM8_AZALIA_STREAM_DATA … #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream9_dispdec // base address: 0x328 #define regAZF0STREAM9_AZALIA_STREAM_INDEX … #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM9_AZALIA_STREAM_DATA … #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream10_dispdec // base address: 0x330 #define regAZF0STREAM10_AZALIA_STREAM_INDEX … #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM10_AZALIA_STREAM_DATA … #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream11_dispdec // base address: 0x338 #define regAZF0STREAM11_AZALIA_STREAM_INDEX … #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM11_AZALIA_STREAM_DATA … #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream12_dispdec // base address: 0x340 #define regAZF0STREAM12_AZALIA_STREAM_INDEX … #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM12_AZALIA_STREAM_DATA … #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream13_dispdec // base address: 0x348 #define regAZF0STREAM13_AZALIA_STREAM_INDEX … #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM13_AZALIA_STREAM_DATA … #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream14_dispdec // base address: 0x350 #define regAZF0STREAM14_AZALIA_STREAM_INDEX … #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM14_AZALIA_STREAM_DATA … #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0stream15_dispdec // base address: 0x358 #define regAZF0STREAM15_AZALIA_STREAM_INDEX … #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX … #define regAZF0STREAM15_AZALIA_STREAM_DATA … #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint0_dispdec // base address: 0x0 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint1_dispdec // base address: 0x18 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint2_dispdec // base address: 0x30 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint3_dispdec // base address: 0x48 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint4_dispdec // base address: 0x60 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint5_dispdec // base address: 0x78 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint6_dispdec // base address: 0x90 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0endpoint7_dispdec // base address: 0xa8 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA … #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint0_dispdec // base address: 0x0 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint1_dispdec // base address: 0x10 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint2_dispdec // base address: 0x20 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint3_dispdec // base address: 0x30 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint4_dispdec // base address: 0x40 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint5_dispdec // base address: 0x50 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint6_dispdec // base address: 0x60 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_hda_azf0inputendpoint7_dispdec // base address: 0x70 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dcn_dcec_dchubbubl_hubbub_dispdec // base address: 0x0 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND … #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX … #define regDCHUBBUB_ARB_SAT_LEVEL … #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX … #define regDCHUBBUB_ARB_QOS_FORCE … #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX … #define regDCHUBBUB_ARB_DRAM_STATE_CNTL … #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX … #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL … #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX … #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A … #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A … #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A … #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX … #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A … #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A_BASE_IDX … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A … #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A … #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A … #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A_BASE_IDX … #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B … #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B … #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B … #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX … #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B … #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B … #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B_BASE_IDX … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B … #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B_BASE_IDX … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B … #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B … #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B … #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B … #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX … #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B … #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B_BASE_IDX … #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL … #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX … #define regDCHUBBUB_ARB_MALL_CNTL … #define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX … #define regDCHUBBUB_ARB_TIMEOUT_ENABLE … #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX … #define regDCHUBBUB_GLOBAL_TIMER_CNTL … #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX … #define regSURFACE_CHECK0_ADDRESS_LSB … #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX … #define regSURFACE_CHECK0_ADDRESS_MSB … #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX … #define regSURFACE_CHECK1_ADDRESS_LSB … #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX … #define regSURFACE_CHECK1_ADDRESS_MSB … #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX … #define regSURFACE_CHECK2_ADDRESS_LSB … #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX … #define regSURFACE_CHECK2_ADDRESS_MSB … #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX … #define regSURFACE_CHECK3_ADDRESS_LSB … #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX … #define regSURFACE_CHECK3_ADDRESS_MSB … #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX … #define regVTG0_CONTROL … #define regVTG0_CONTROL_BASE_IDX … #define regVTG1_CONTROL … #define regVTG1_CONTROL_BASE_IDX … #define regVTG2_CONTROL … #define regVTG2_CONTROL_BASE_IDX … #define regVTG3_CONTROL … #define regVTG3_CONTROL_BASE_IDX … #define regDCHUBBUB_SOFT_RESET … #define regDCHUBBUB_SOFT_RESET_BASE_IDX … #define regDCHUBBUB_CLOCK_CNTL … #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX … #define regDCFCLK_CNTL … #define regDCFCLK_CNTL_BASE_IDX … #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL … #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX … #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 … #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX … #define regDCHUBBUB_VLINE_SNAPSHOT … #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX … #define regDCHUBBUB_CTRL_STATUS … #define regDCHUBBUB_CTRL_STATUS_BASE_IDX … #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 … #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX … #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 … #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX … #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS … #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX … #define regFMON_CTRL … #define regFMON_CTRL_BASE_IDX … #define regDCHUBBUB_TEST_DEBUG_INDEX … #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX … #define regDCHUBBUB_TEST_DEBUG_DATA … #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dchubbubl_hubbub_sdpif_dispdec // base address: 0x0 #define regDCHUBBUB_SDPIF_CFG0 … #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX … #define regDCHUBBUB_SDPIF_CFG1 … #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX … #define regDCHUBBUB_SDPIF_CFG2 … #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX … #define regVM_REQUEST_PHYSICAL … #define regVM_REQUEST_PHYSICAL_BASE_IDX … #define regDCHUBBUB_FORCE_IO_STATUS_0 … #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX … #define regDCHUBBUB_FORCE_IO_STATUS_1 … #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX … #define regDCN_VM_FB_LOCATION_BASE … #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX … #define regDCN_VM_FB_LOCATION_TOP … #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX … #define regDCN_VM_FB_OFFSET … #define regDCN_VM_FB_OFFSET_BASE_IDX … #define regDCN_VM_AGP_BOT … #define regDCN_VM_AGP_BOT_BASE_IDX … #define regDCN_VM_AGP_TOP … #define regDCN_VM_AGP_TOP_BASE_IDX … #define regDCN_VM_AGP_BASE … #define regDCN_VM_AGP_BASE_BASE_IDX … #define regDCN_VM_LOCAL_HBM_ADDRESS_START … #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define regDCN_VM_LOCAL_HBM_ADDRESS_END … #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL … #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_NOALLOC … #define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL … #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL … #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL … #define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL … #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX … #define regDCHUBBUB_SDPIF_PIPE_DATAFETCH … #define regDCHUBBUB_SDPIF_PIPE_DATAFETCH_BASE_IDX … #define regSDPIF_REQUEST_RATE_LIMIT … #define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX … #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL … #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX … #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS … #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX … #define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL … #define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL_BASE_IDX … // addressBlock: dcn_dcec_dchubbubl_hubbub_ret_path_dispdec // base address: 0x0 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL … #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX … #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS … #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX … #define regDCHUBBUB_CRC_CTRL … #define regDCHUBBUB_CRC_CTRL_BASE_IDX … #define regDCHUBBUB_CRC0_VAL_R_G … #define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX … #define regDCHUBBUB_CRC0_VAL_B_A … #define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX … #define regDCHUBBUB_CRC1_VAL_R_G … #define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX … #define regDCHUBBUB_CRC1_VAL_B_A … #define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX … #define regDCHUBBUB_DCC_STAT_CNTL … #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX … #define regDCHUBBUB_DCC_STAT0 … #define regDCHUBBUB_DCC_STAT0_BASE_IDX … #define regDCHUBBUB_DCC_STAT1 … #define regDCHUBBUB_DCC_STAT1_BASE_IDX … #define regDCHUBBUB_DCC_STAT2 … #define regDCHUBBUB_DCC_STAT2_BASE_IDX … #define regDCHUBBUB_COMPBUF_CTRL … #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX … #define regDCHUBBUB_DET0_CTRL … #define regDCHUBBUB_DET0_CTRL_BASE_IDX … #define regDCHUBBUB_DET1_CTRL … #define regDCHUBBUB_DET1_CTRL_BASE_IDX … #define regDCHUBBUB_DET2_CTRL … #define regDCHUBBUB_DET2_CTRL_BASE_IDX … #define regDCHUBBUB_DET3_CTRL … #define regDCHUBBUB_DET3_CTRL_BASE_IDX … #define regDCHUBBUB_STAT … #define regDCHUBBUB_STAT_BASE_IDX … #define regDCHUBBUB_MEM_PWR_MODE_CTRL … #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX … #define regCOMPBUF_MEM_PWR_CTRL_1 … #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX … #define regCOMPBUF_MEM_PWR_CTRL_2 … #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX … #define regDCHUBBUB_MEM_PWR_STATUS … #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX … #define regCOMPBUF_RESERVED_SPACE … #define regCOMPBUF_RESERVED_SPACE_BASE_IDX … #define regDCN_DECOMP_STATUS … #define regDCN_DECOMP_STATUS_BASE_IDX … #define regDCHUBBUB_DEBUG_CTRL_0 … #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX … #define regDCHUBBUB_DEBUG_CTRL_1 … #define regDCHUBBUB_DEBUG_CTRL_1_BASE_IDX … #define regDCHUBBUB_DEBUG_CTRL_2 … #define regDCHUBBUB_DEBUG_CTRL_2_BASE_IDX … #define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX … #define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX … #define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA … #define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dchubbubl_hubbub_vmrq_if_dispdec // base address: 0x0 #define regDCN_VM_CONTEXT0_CNTL … #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT1_CNTL … #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT2_CNTL … #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT3_CNTL … #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT4_CNTL … #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT5_CNTL … #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT6_CNTL … #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT7_CNTL … #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT8_CNTL … #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT9_CNTL … #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT10_CNTL … #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT11_CNTL … #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT12_CNTL … #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT13_CNTL … #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT14_CNTL … #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT15_CNTL … #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regDCN_VM_DEFAULT_ADDR_MSB … #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX … #define regDCN_VM_DEFAULT_ADDR_LSB … #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX … #define regDCN_VM_FAULT_CNTL … #define regDCN_VM_FAULT_CNTL_BASE_IDX … #define regDCN_VM_FAULT_STATUS … #define regDCN_VM_FAULT_STATUS_BASE_IDX … #define regDCN_VM_FAULT_ADDR_MSB … #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX … #define regDCN_VM_FAULT_ADDR_LSB … #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX … // addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dispdec // base address: 0x0 #define regHUBP0_DCSURF_SURFACE_CONFIG … #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX … #define regHUBP0_DCSURF_ADDR_CONFIG … #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX … #define regHUBP0_DCSURF_TILING_CONFIG … #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX … #define regHUBP0_DCSURF_PRI_VIEWPORT_START … #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE … #define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX … #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION … #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C … #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP0_DCSURF_SEC_VIEWPORT_START … #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION … #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C … #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG … #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C … #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define regHUBP0_DCHUBP_CNTL … #define regHUBP0_DCHUBP_CNTL_BASE_IDX … #define regHUBP0_HUBP_CLK_CNTL … #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX … #define regHUBP0_DCHUBP_VMPG_CONFIG … #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX … #define regHUBP0_DCHUBP_MALL_CONFIG … #define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX … #define regHUBP0_DCHUBP_MALL_SUB_VP0 … #define regHUBP0_DCHUBP_MALL_SUB_VP0_BASE_IDX … #define regHUBP0_DCHUBP_MALL_SUB_VP1 … #define regHUBP0_DCHUBP_MALL_SUB_VP1_BASE_IDX … #define regHUBP0_DCHUBP_MALL_SUB_VP2 … #define regHUBP0_DCHUBP_MALL_SUB_VP2_BASE_IDX … #define regHUBP0_DCHUBP_MCACHEID_CONFIG … #define regHUBP0_DCHUBP_MCACHEID_CONFIG_BASE_IDX … #define regHUBP0_HUBPREQ_DEBUG_DB … #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX … #define regHUBP0_HUBPREQ_DEBUG … #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX … #define regHUBP0_HUBP_DEBUG_CTRL … #define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX … #define regHUBP0_HUBP_DEBUG_MUX_DCFCLK … #define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX … #define regHUBP0_HUBP_DEBUG_MUX_DPPCLK … #define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX … #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … #define regHUBP0_HUBP_MALL_STATUS … #define regHUBP0_HUBP_MALL_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp0_dispdec_hubpreq_dispdec // base address: 0x0 #define regHUBPREQ0_DCSURF_SURFACE_PITCH … #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C … #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define regHUBPREQ0_VMID_SETTINGS_0 … #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_CONTROL … #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX … #define regHUBPREQ0_DCSURF_FLIP_CONTROL … #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX … #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 … #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT … #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_INUSE … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C … #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ0_DCN_EXPANSION_MODE … #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX … #define regHUBPREQ0_DCN_TTU_QOS_WM … #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX … #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL … #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 … #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 … #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 … #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 … #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 … #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 … #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 … #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 … #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ0_DCN_DMDATA_VM_CNTL … #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX … #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR … #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL … #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define regHUBPREQ0_BLANK_OFFSET_0 … #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX … #define regHUBPREQ0_BLANK_OFFSET_1 … #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX … #define regHUBPREQ0_DST_DIMENSIONS … #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX … #define regHUBPREQ0_DST_AFTER_SCALER … #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX … #define regHUBPREQ0_PREFETCH_SETTINGS … #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX … #define regHUBPREQ0_PREFETCH_SETTINGS_C … #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_0 … #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_1 … #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_2 … #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_3 … #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_4 … #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_0 … #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_1 … #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_2 … #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_0 … #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_1 … #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_2 … #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_3 … #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_4 … #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_5 … #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_6 … #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX … #define regHUBPREQ0_NOM_PARAMETERS_7 … #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX … #define regHUBPREQ0_PER_LINE_DELIVERY_PRE … #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX … #define regHUBPREQ0_PER_LINE_DELIVERY … #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX … #define regHUBPREQ0_CURSOR_SETTINGS … #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX … #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ … #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT … #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL … #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS … #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_5 … #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX … #define regHUBPREQ0_VBLANK_PARAMETERS_6 … #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_3 … #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_4 … #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_5 … #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX … #define regHUBPREQ0_FLIP_PARAMETERS_6 … #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX … #define regHUBPREQ0_UCLK_PSTATE_FORCE … #define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX … #define regHUBPREQ0_HUBPREQ_STATUS_REG0 … #define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX … #define regHUBPREQ0_HUBPREQ_STATUS_REG1 … #define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX … #define regHUBPREQ0_HUBPREQ_STATUS_REG2 … #define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX … #define regHUBPREQ0_HUBPREQ_STATUS_REG3 … #define regHUBPREQ0_HUBPREQ_STATUS_REG3_BASE_IDX … // addressBlock: dcn_dcec_dcbubp0_dispdec_hubpret_dispdec // base address: 0x0 #define regHUBPRET0_HUBPRET_CONTROL … #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX … #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL … #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS … #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 … #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 … #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE0 … #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE1 … #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX … #define regHUBPRET0_HUBPRET_INTERRUPT … #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE_VALUE … #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define regHUBPRET0_HUBPRET_READ_LINE_STATUS … #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp0_dispdec_cursor0_dispdec // base address: 0x0 #define regCURSOR0_0_CURSOR_CONTROL … #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX … #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS … #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH … #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_0_CURSOR_SIZE … #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX … #define regCURSOR0_0_CURSOR_POSITION … #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX … #define regCURSOR0_0_CURSOR_HOT_SPOT … #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX … #define regCURSOR0_0_CURSOR_STEREO_CONTROL … #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX … #define regCURSOR0_0_CURSOR_DST_OFFSET … #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX … #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL … #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS … #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define regCURSOR0_0_DMDATA_ADDRESS_HIGH … #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_0_DMDATA_ADDRESS_LOW … #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_0_DMDATA_CNTL … #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX … #define regCURSOR0_0_DMDATA_QOS_CNTL … #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX … #define regCURSOR0_0_DMDATA_STATUS … #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX … #define regCURSOR0_0_DMDATA_SW_CNTL … #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX … #define regCURSOR0_0_DMDATA_SW_DATA … #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX … #define regCURSOR0_0_HUBP_3DLUT_CONTROL … #define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX … #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW … #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH … #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM … #define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX … // addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dispdec // base address: 0x370 #define regHUBP1_DCSURF_SURFACE_CONFIG … #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX … #define regHUBP1_DCSURF_ADDR_CONFIG … #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX … #define regHUBP1_DCSURF_TILING_CONFIG … #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX … #define regHUBP1_DCSURF_PRI_VIEWPORT_START … #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE … #define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX … #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION … #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C … #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP1_DCSURF_SEC_VIEWPORT_START … #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION … #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C … #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG … #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C … #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define regHUBP1_DCHUBP_CNTL … #define regHUBP1_DCHUBP_CNTL_BASE_IDX … #define regHUBP1_HUBP_CLK_CNTL … #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX … #define regHUBP1_DCHUBP_VMPG_CONFIG … #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX … #define regHUBP1_DCHUBP_MALL_CONFIG … #define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX … #define regHUBP1_DCHUBP_MALL_SUB_VP0 … #define regHUBP1_DCHUBP_MALL_SUB_VP0_BASE_IDX … #define regHUBP1_DCHUBP_MALL_SUB_VP1 … #define regHUBP1_DCHUBP_MALL_SUB_VP1_BASE_IDX … #define regHUBP1_DCHUBP_MALL_SUB_VP2 … #define regHUBP1_DCHUBP_MALL_SUB_VP2_BASE_IDX … #define regHUBP1_DCHUBP_MCACHEID_CONFIG … #define regHUBP1_DCHUBP_MCACHEID_CONFIG_BASE_IDX … #define regHUBP1_HUBPREQ_DEBUG_DB … #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX … #define regHUBP1_HUBPREQ_DEBUG … #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX … #define regHUBP1_HUBP_DEBUG_CTRL … #define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX … #define regHUBP1_HUBP_DEBUG_MUX_DCFCLK … #define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX … #define regHUBP1_HUBP_DEBUG_MUX_DPPCLK … #define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX … #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … #define regHUBP1_HUBP_MALL_STATUS … #define regHUBP1_HUBP_MALL_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp1_dispdec_hubpreq_dispdec // base address: 0x370 #define regHUBPREQ1_DCSURF_SURFACE_PITCH … #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C … #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define regHUBPREQ1_VMID_SETTINGS_0 … #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_CONTROL … #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX … #define regHUBPREQ1_DCSURF_FLIP_CONTROL … #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX … #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 … #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT … #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_INUSE … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C … #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ1_DCN_EXPANSION_MODE … #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX … #define regHUBPREQ1_DCN_TTU_QOS_WM … #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX … #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL … #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 … #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 … #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 … #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 … #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 … #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 … #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 … #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 … #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ1_DCN_DMDATA_VM_CNTL … #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX … #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR … #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL … #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define regHUBPREQ1_BLANK_OFFSET_0 … #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX … #define regHUBPREQ1_BLANK_OFFSET_1 … #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX … #define regHUBPREQ1_DST_DIMENSIONS … #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX … #define regHUBPREQ1_DST_AFTER_SCALER … #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX … #define regHUBPREQ1_PREFETCH_SETTINGS … #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX … #define regHUBPREQ1_PREFETCH_SETTINGS_C … #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_0 … #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_1 … #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_2 … #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_3 … #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_4 … #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_0 … #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_1 … #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_2 … #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_0 … #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_1 … #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_2 … #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_3 … #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_4 … #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_5 … #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_6 … #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX … #define regHUBPREQ1_NOM_PARAMETERS_7 … #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX … #define regHUBPREQ1_PER_LINE_DELIVERY_PRE … #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX … #define regHUBPREQ1_PER_LINE_DELIVERY … #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX … #define regHUBPREQ1_CURSOR_SETTINGS … #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX … #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ … #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT … #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL … #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS … #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_5 … #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX … #define regHUBPREQ1_VBLANK_PARAMETERS_6 … #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_3 … #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_4 … #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_5 … #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX … #define regHUBPREQ1_FLIP_PARAMETERS_6 … #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX … #define regHUBPREQ1_UCLK_PSTATE_FORCE … #define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX … #define regHUBPREQ1_HUBPREQ_STATUS_REG0 … #define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX … #define regHUBPREQ1_HUBPREQ_STATUS_REG1 … #define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX … #define regHUBPREQ1_HUBPREQ_STATUS_REG2 … #define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX … #define regHUBPREQ1_HUBPREQ_STATUS_REG3 … #define regHUBPREQ1_HUBPREQ_STATUS_REG3_BASE_IDX … // addressBlock: dcn_dcec_dcbubp1_dispdec_hubpret_dispdec // base address: 0x370 #define regHUBPRET1_HUBPRET_CONTROL … #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX … #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL … #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS … #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 … #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 … #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE0 … #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE1 … #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX … #define regHUBPRET1_HUBPRET_INTERRUPT … #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE_VALUE … #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define regHUBPRET1_HUBPRET_READ_LINE_STATUS … #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp1_dispdec_cursor0_dispdec // base address: 0x370 #define regCURSOR0_1_CURSOR_CONTROL … #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX … #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS … #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH … #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_1_CURSOR_SIZE … #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX … #define regCURSOR0_1_CURSOR_POSITION … #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX … #define regCURSOR0_1_CURSOR_HOT_SPOT … #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX … #define regCURSOR0_1_CURSOR_STEREO_CONTROL … #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX … #define regCURSOR0_1_CURSOR_DST_OFFSET … #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX … #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL … #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS … #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define regCURSOR0_1_DMDATA_ADDRESS_HIGH … #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_1_DMDATA_ADDRESS_LOW … #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_1_DMDATA_CNTL … #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX … #define regCURSOR0_1_DMDATA_QOS_CNTL … #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX … #define regCURSOR0_1_DMDATA_STATUS … #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX … #define regCURSOR0_1_DMDATA_SW_CNTL … #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX … #define regCURSOR0_1_DMDATA_SW_DATA … #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX … #define regCURSOR0_1_HUBP_3DLUT_CONTROL … #define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX … #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW … #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH … #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM … #define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX … // addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dispdec // base address: 0x6e0 #define regHUBP2_DCSURF_SURFACE_CONFIG … #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX … #define regHUBP2_DCSURF_ADDR_CONFIG … #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX … #define regHUBP2_DCSURF_TILING_CONFIG … #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX … #define regHUBP2_DCSURF_PRI_VIEWPORT_START … #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE … #define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX … #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION … #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C … #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP2_DCSURF_SEC_VIEWPORT_START … #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION … #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C … #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG … #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C … #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define regHUBP2_DCHUBP_CNTL … #define regHUBP2_DCHUBP_CNTL_BASE_IDX … #define regHUBP2_HUBP_CLK_CNTL … #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX … #define regHUBP2_DCHUBP_VMPG_CONFIG … #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX … #define regHUBP2_DCHUBP_MALL_CONFIG … #define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX … #define regHUBP2_DCHUBP_MALL_SUB_VP0 … #define regHUBP2_DCHUBP_MALL_SUB_VP0_BASE_IDX … #define regHUBP2_DCHUBP_MALL_SUB_VP1 … #define regHUBP2_DCHUBP_MALL_SUB_VP1_BASE_IDX … #define regHUBP2_DCHUBP_MALL_SUB_VP2 … #define regHUBP2_DCHUBP_MALL_SUB_VP2_BASE_IDX … #define regHUBP2_DCHUBP_MCACHEID_CONFIG … #define regHUBP2_DCHUBP_MCACHEID_CONFIG_BASE_IDX … #define regHUBP2_HUBPREQ_DEBUG_DB … #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX … #define regHUBP2_HUBPREQ_DEBUG … #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX … #define regHUBP2_HUBP_DEBUG_CTRL … #define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX … #define regHUBP2_HUBP_DEBUG_MUX_DCFCLK … #define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX … #define regHUBP2_HUBP_DEBUG_MUX_DPPCLK … #define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX … #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … #define regHUBP2_HUBP_MALL_STATUS … #define regHUBP2_HUBP_MALL_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp2_dispdec_hubpreq_dispdec // base address: 0x6e0 #define regHUBPREQ2_DCSURF_SURFACE_PITCH … #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C … #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define regHUBPREQ2_VMID_SETTINGS_0 … #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_CONTROL … #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX … #define regHUBPREQ2_DCSURF_FLIP_CONTROL … #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX … #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 … #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT … #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_INUSE … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C … #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ2_DCN_EXPANSION_MODE … #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX … #define regHUBPREQ2_DCN_TTU_QOS_WM … #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX … #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL … #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 … #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 … #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 … #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 … #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 … #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 … #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 … #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 … #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ2_DCN_DMDATA_VM_CNTL … #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX … #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR … #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL … #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define regHUBPREQ2_BLANK_OFFSET_0 … #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX … #define regHUBPREQ2_BLANK_OFFSET_1 … #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX … #define regHUBPREQ2_DST_DIMENSIONS … #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX … #define regHUBPREQ2_DST_AFTER_SCALER … #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX … #define regHUBPREQ2_PREFETCH_SETTINGS … #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX … #define regHUBPREQ2_PREFETCH_SETTINGS_C … #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_0 … #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_1 … #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_2 … #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_3 … #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_4 … #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_0 … #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_1 … #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_2 … #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_0 … #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_1 … #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_2 … #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_3 … #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_4 … #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_5 … #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_6 … #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX … #define regHUBPREQ2_NOM_PARAMETERS_7 … #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX … #define regHUBPREQ2_PER_LINE_DELIVERY_PRE … #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX … #define regHUBPREQ2_PER_LINE_DELIVERY … #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX … #define regHUBPREQ2_CURSOR_SETTINGS … #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX … #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ … #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT … #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL … #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS … #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_5 … #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX … #define regHUBPREQ2_VBLANK_PARAMETERS_6 … #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_3 … #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_4 … #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_5 … #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX … #define regHUBPREQ2_FLIP_PARAMETERS_6 … #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX … #define regHUBPREQ2_UCLK_PSTATE_FORCE … #define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX … #define regHUBPREQ2_HUBPREQ_STATUS_REG0 … #define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX … #define regHUBPREQ2_HUBPREQ_STATUS_REG1 … #define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX … #define regHUBPREQ2_HUBPREQ_STATUS_REG2 … #define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX … #define regHUBPREQ2_HUBPREQ_STATUS_REG3 … #define regHUBPREQ2_HUBPREQ_STATUS_REG3_BASE_IDX … // addressBlock: dcn_dcec_dcbubp2_dispdec_hubpret_dispdec // base address: 0x6e0 #define regHUBPRET2_HUBPRET_CONTROL … #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX … #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL … #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS … #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 … #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 … #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE0 … #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE1 … #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX … #define regHUBPRET2_HUBPRET_INTERRUPT … #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE_VALUE … #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define regHUBPRET2_HUBPRET_READ_LINE_STATUS … #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp2_dispdec_cursor0_dispdec // base address: 0x6e0 #define regCURSOR0_2_CURSOR_CONTROL … #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX … #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS … #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH … #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_2_CURSOR_SIZE … #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX … #define regCURSOR0_2_CURSOR_POSITION … #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX … #define regCURSOR0_2_CURSOR_HOT_SPOT … #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX … #define regCURSOR0_2_CURSOR_STEREO_CONTROL … #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX … #define regCURSOR0_2_CURSOR_DST_OFFSET … #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX … #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL … #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS … #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define regCURSOR0_2_DMDATA_ADDRESS_HIGH … #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_2_DMDATA_ADDRESS_LOW … #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_2_DMDATA_CNTL … #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX … #define regCURSOR0_2_DMDATA_QOS_CNTL … #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX … #define regCURSOR0_2_DMDATA_STATUS … #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX … #define regCURSOR0_2_DMDATA_SW_CNTL … #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX … #define regCURSOR0_2_DMDATA_SW_DATA … #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX … #define regCURSOR0_2_HUBP_3DLUT_CONTROL … #define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX … #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW … #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH … #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM … #define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX … // addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dispdec // base address: 0xa50 #define regHUBP3_DCSURF_SURFACE_CONFIG … #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX … #define regHUBP3_DCSURF_ADDR_CONFIG … #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX … #define regHUBP3_DCSURF_TILING_CONFIG … #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX … #define regHUBP3_DCSURF_PRI_VIEWPORT_START … #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE … #define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX … #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION … #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C … #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP3_DCSURF_SEC_VIEWPORT_START … #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION … #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C … #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG … #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C … #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define regHUBP3_DCHUBP_CNTL … #define regHUBP3_DCHUBP_CNTL_BASE_IDX … #define regHUBP3_HUBP_CLK_CNTL … #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX … #define regHUBP3_DCHUBP_VMPG_CONFIG … #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX … #define regHUBP3_DCHUBP_MALL_CONFIG … #define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX … #define regHUBP3_DCHUBP_MALL_SUB_VP0 … #define regHUBP3_DCHUBP_MALL_SUB_VP0_BASE_IDX … #define regHUBP3_DCHUBP_MALL_SUB_VP1 … #define regHUBP3_DCHUBP_MALL_SUB_VP1_BASE_IDX … #define regHUBP3_DCHUBP_MALL_SUB_VP2 … #define regHUBP3_DCHUBP_MALL_SUB_VP2_BASE_IDX … #define regHUBP3_DCHUBP_MCACHEID_CONFIG … #define regHUBP3_DCHUBP_MCACHEID_CONFIG_BASE_IDX … #define regHUBP3_HUBPREQ_DEBUG_DB … #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX … #define regHUBP3_HUBPREQ_DEBUG … #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX … #define regHUBP3_HUBP_DEBUG_CTRL … #define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX … #define regHUBP3_HUBP_DEBUG_MUX_DCFCLK … #define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX … #define regHUBP3_HUBP_DEBUG_MUX_DPPCLK … #define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX … #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … #define regHUBP3_HUBP_MALL_STATUS … #define regHUBP3_HUBP_MALL_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp3_dispdec_hubpreq_dispdec // base address: 0xa50 #define regHUBPREQ3_DCSURF_SURFACE_PITCH … #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C … #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define regHUBPREQ3_VMID_SETTINGS_0 … #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_CONTROL … #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX … #define regHUBPREQ3_DCSURF_FLIP_CONTROL … #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX … #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 … #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT … #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_INUSE … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C … #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define regHUBPREQ3_DCN_EXPANSION_MODE … #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX … #define regHUBPREQ3_DCN_TTU_QOS_WM … #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX … #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL … #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 … #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 … #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 … #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 … #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 … #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 … #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 … #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 … #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define regHUBPREQ3_DCN_DMDATA_VM_CNTL … #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX … #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR … #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL … #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define regHUBPREQ3_BLANK_OFFSET_0 … #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX … #define regHUBPREQ3_BLANK_OFFSET_1 … #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX … #define regHUBPREQ3_DST_DIMENSIONS … #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX … #define regHUBPREQ3_DST_AFTER_SCALER … #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX … #define regHUBPREQ3_PREFETCH_SETTINGS … #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX … #define regHUBPREQ3_PREFETCH_SETTINGS_C … #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_0 … #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_1 … #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_2 … #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_3 … #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_4 … #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_0 … #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_1 … #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_2 … #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_0 … #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_1 … #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_2 … #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_3 … #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_4 … #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_5 … #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_6 … #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX … #define regHUBPREQ3_NOM_PARAMETERS_7 … #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX … #define regHUBPREQ3_PER_LINE_DELIVERY_PRE … #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX … #define regHUBPREQ3_PER_LINE_DELIVERY … #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX … #define regHUBPREQ3_CURSOR_SETTINGS … #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX … #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ … #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT … #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL … #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS … #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_5 … #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX … #define regHUBPREQ3_VBLANK_PARAMETERS_6 … #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_3 … #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_4 … #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_5 … #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX … #define regHUBPREQ3_FLIP_PARAMETERS_6 … #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX … #define regHUBPREQ3_UCLK_PSTATE_FORCE … #define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX … #define regHUBPREQ3_HUBPREQ_STATUS_REG0 … #define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX … #define regHUBPREQ3_HUBPREQ_STATUS_REG1 … #define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX … #define regHUBPREQ3_HUBPREQ_STATUS_REG2 … #define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX … #define regHUBPREQ3_HUBPREQ_STATUS_REG3 … #define regHUBPREQ3_HUBPREQ_STATUS_REG3_BASE_IDX … // addressBlock: dcn_dcec_dcbubp3_dispdec_hubpret_dispdec // base address: 0xa50 #define regHUBPRET3_HUBPRET_CONTROL … #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX … #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL … #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS … #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 … #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 … #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE0 … #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE1 … #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX … #define regHUBPRET3_HUBPRET_INTERRUPT … #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE_VALUE … #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define regHUBPRET3_HUBPRET_READ_LINE_STATUS … #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcbubp3_dispdec_cursor0_dispdec // base address: 0xa50 #define regCURSOR0_3_CURSOR_CONTROL … #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX … #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS … #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH … #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_3_CURSOR_SIZE … #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX … #define regCURSOR0_3_CURSOR_POSITION … #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX … #define regCURSOR0_3_CURSOR_HOT_SPOT … #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX … #define regCURSOR0_3_CURSOR_STEREO_CONTROL … #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX … #define regCURSOR0_3_CURSOR_DST_OFFSET … #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX … #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL … #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS … #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define regCURSOR0_3_DMDATA_ADDRESS_HIGH … #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_3_DMDATA_ADDRESS_LOW … #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_3_DMDATA_CNTL … #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX … #define regCURSOR0_3_DMDATA_QOS_CNTL … #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX … #define regCURSOR0_3_DMDATA_STATUS … #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX … #define regCURSOR0_3_DMDATA_SW_CNTL … #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX … #define regCURSOR0_3_DMDATA_SW_DATA … #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX … #define regCURSOR0_3_HUBP_3DLUT_CONTROL … #define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX … #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW … #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX … #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH … #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX … #define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM … #define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX … // addressBlock: dcn_dcec_dpp0_dispdec_cnvc_cfg_dispdec // base address: 0x0 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT … #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define regCNVC_CFG0_FORMAT_CONTROL … #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_BIAS_R … #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_BIAS_G … #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_BIAS_B … #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_SCALE_R … #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_SCALE_G … #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX … #define regCNVC_CFG0_FCNV_FP_SCALE_B … #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX … #define regCNVC_CFG0_COLOR_KEYER_CONTROL … #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX … #define regCNVC_CFG0_COLOR_KEYER_ALPHA … #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX … #define regCNVC_CFG0_COLOR_KEYER_RED … #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX … #define regCNVC_CFG0_COLOR_KEYER_GREEN … #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX … #define regCNVC_CFG0_COLOR_KEYER_BLUE … #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX … #define regCNVC_CFG0_ALPHA_2BIT_LUT … #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX … #define regCNVC_CFG0_PRE_DEALPHA … #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_MODE … #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C11_C12 … #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C13_C14 … #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C21_C22 … #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C23_C24 … #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C31_C32 … #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_C33_C34 … #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C11_C12 … #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C13_C14 … #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C21_C22 … #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C23_C24 … #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX … #define regCNVC_CFG0_PRE_CSC_B_C33_C34 … #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX … #define regCNVC_CFG0_CNVC_COEF_FORMAT … #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX … #define regCNVC_CFG0_PRE_DEGAM … #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX … #define regCNVC_CFG0_PRE_REALPHA … #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX … // addressBlock: dcn_dcec_dpp0_dispdec_cm_cur_dispdec // base address: 0x0 #define regCM_CUR0_CURSOR0_CONTROL … #define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX … #define regCM_CUR0_CURSOR0_COLOR0 … #define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX … #define regCM_CUR0_CURSOR0_COLOR1 … #define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX … #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y … #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX … #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB … #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_MODE … #define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C11_C12_A … #define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C13_C14_A … #define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C21_C22_A … #define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C23_C24_A … #define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C31_C32_A … #define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C33_C34_A … #define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C11_C12_B … #define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C13_C14_B … #define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C21_C22_B … #define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C23_C24_B … #define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C31_C32_B … #define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX … #define regCM_CUR0_CUR0_MATRIX_C33_C34_B … #define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_dpp0_dispdec_dscl_dispdec // base address: 0x0 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT … #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define regDSCL0_SCL_COEF_RAM_TAP_DATA … #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define regDSCL0_SCL_MODE … #define regDSCL0_SCL_MODE_BASE_IDX … #define regDSCL0_SCL_TAP_CONTROL … #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX … #define regDSCL0_DSCL_CONTROL … #define regDSCL0_DSCL_CONTROL_BASE_IDX … #define regDSCL0_DSCL_2TAP_CONTROL … #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX … #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL … #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO … #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL0_SCL_HORZ_FILTER_INIT … #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX … #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C … #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL0_SCL_HORZ_FILTER_INIT_C … #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO … #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_INIT … #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_INIT_BOT … #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C … #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_INIT_C … #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C … #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define regDSCL0_SCL_BLACK_COLOR … #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX … #define regDSCL0_DSCL_UPDATE … #define regDSCL0_DSCL_UPDATE_BASE_IDX … #define regDSCL0_DSCL_AUTOCAL … #define regDSCL0_DSCL_AUTOCAL_BASE_IDX … #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define regDSCL0_OTG_H_BLANK … #define regDSCL0_OTG_H_BLANK_BASE_IDX … #define regDSCL0_OTG_V_BLANK … #define regDSCL0_OTG_V_BLANK_BASE_IDX … #define regDSCL0_RECOUT_START … #define regDSCL0_RECOUT_START_BASE_IDX … #define regDSCL0_RECOUT_SIZE … #define regDSCL0_RECOUT_SIZE_BASE_IDX … #define regDSCL0_MPC_SIZE … #define regDSCL0_MPC_SIZE_BASE_IDX … #define regDSCL0_LB_DATA_FORMAT … #define regDSCL0_LB_DATA_FORMAT_BASE_IDX … #define regDSCL0_LB_MEMORY_CTRL … #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX … #define regDSCL0_LB_V_COUNTER … #define regDSCL0_LB_V_COUNTER_BASE_IDX … #define regDSCL0_DSCL_MEM_PWR_CTRL … #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … #define regDSCL0_DSCL_MEM_PWR_STATUS … #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … #define regDSCL0_OBUF_CONTROL … #define regDSCL0_OBUF_CONTROL_BASE_IDX … #define regDSCL0_OBUF_MEM_PWR_CTRL … #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX … #define regDSCL0_DSCL_EASF_H_MODE … #define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX … #define regDSCL0_DSCL_EASF_V_MODE … #define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX … #define regDSCL0_DSCL_SC_MODE … #define regDSCL0_DSCL_SC_MODE_BASE_IDX … #define regDSCL0_DSCL_SC_MATRIX_C0C1 … #define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX … #define regDSCL0_DSCL_SC_MATRIX_C2C3 … #define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX … #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN … #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE … #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN … #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE … #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 … #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX … #define regDSCL0_DSCL_EASF_RINGEST_FORCE … #define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF_CNTL … #define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN … #define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF_CNTL … #define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN … #define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7 … #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7 … #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5 … #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5 … #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX … #define regDSCL0_ISHARP_MODE … #define regDSCL0_ISHARP_MODE_BASE_IDX … #define regDSCL0_ISHARP_DELTA_CTRL … #define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX … #define regDSCL0_ISHARP_DELTA_INDEX … #define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX … #define regDSCL0_ISHARP_DELTA_DATA … #define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX … #define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP … #define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX … #define regDSCL0_ISHARP_NOISEDET_THRESHOLD … #define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX … #define regDSCL0_ISHARP_NOISE_GAIN_PWL … #define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG0 … #define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG1 … #define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG2 … #define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG3 … #define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG4 … #define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX … #define regDSCL0_ISHARP_LBA_PWL_SEG5 … #define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX … #define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL … #define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dcn_dcec_dpp0_dispdec_cm_dispdec // base address: 0x0 #define regCM0_CM_CONTROL … #define regCM0_CM_CONTROL_BASE_IDX … #define regCM0_CM_POST_CSC_CONTROL … #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX … #define regCM0_CM_POST_CSC_C11_C12 … #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX … #define regCM0_CM_POST_CSC_C13_C14 … #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX … #define regCM0_CM_POST_CSC_C21_C22 … #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX … #define regCM0_CM_POST_CSC_C23_C24 … #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX … #define regCM0_CM_POST_CSC_C31_C32 … #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX … #define regCM0_CM_POST_CSC_C33_C34 … #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX … #define regCM0_CM_POST_CSC_B_C11_C12 … #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … #define regCM0_CM_POST_CSC_B_C13_C14 … #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX … #define regCM0_CM_POST_CSC_B_C21_C22 … #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX … #define regCM0_CM_POST_CSC_B_C23_C24 … #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX … #define regCM0_CM_POST_CSC_B_C31_C32 … #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX … #define regCM0_CM_POST_CSC_B_C33_C34 … #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX … #define regCM0_CM_BIAS_CR_R … #define regCM0_CM_BIAS_CR_R_BASE_IDX … #define regCM0_CM_BIAS_Y_G_CB_B … #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX … #define regCM0_CM_GAMCOR_CONTROL … #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX … #define regCM0_CM_GAMCOR_LUT_INDEX … #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX … #define regCM0_CM_GAMCOR_LUT_DATA … #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX … #define regCM0_CM_GAMCOR_LUT_CONTROL … #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R … #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R … #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R … #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R … #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R … #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_OFFSET_B … #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_OFFSET_G … #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_OFFSET_R … #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 … #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 … #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 … #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 … #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 … #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 … #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 … #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 … #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 … #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 … #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 … #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 … #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 … #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 … #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 … #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 … #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX … #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 … #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R … #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R … #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R … #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R … #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R … #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_OFFSET_B … #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_OFFSET_G … #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_OFFSET_R … #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 … #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 … #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 … #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 … #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 … #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 … #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 … #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 … #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 … #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 … #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 … #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 … #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 … #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 … #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 … #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 … #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX … #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 … #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX … #define regCM0_CM_HDR_MULT_COEF … #define regCM0_CM_HDR_MULT_COEF_BASE_IDX … #define regCM0_CM_MEM_PWR_CTRL … #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX … #define regCM0_CM_MEM_PWR_STATUS … #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … #define regCM0_CM_DEALPHA … #define regCM0_CM_DEALPHA_BASE_IDX … #define regCM0_CM_COEF_FORMAT … #define regCM0_CM_COEF_FORMAT_BASE_IDX … #define regCM0_CM_TEST_DEBUG_INDEX … #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX … #define regCM0_CM_TEST_DEBUG_DATA … #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dpp0_dispdec_dpp_top_dispdec // base address: 0x0 #define regDPP_TOP0_DPP_CONTROL … #define regDPP_TOP0_DPP_CONTROL_BASE_IDX … #define regDPP_TOP0_DPP_SOFT_RESET … #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX … #define regDPP_TOP0_DPP_CRC_VAL_R_G … #define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX … #define regDPP_TOP0_DPP_CRC_VAL_B_A … #define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX … #define regDPP_TOP0_DPP_CRC_CTRL … #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX … #define regDPP_TOP0_HOST_READ_CONTROL … #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dpp1_dispdec_cnvc_cfg_dispdec // base address: 0x5ac #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT … #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define regCNVC_CFG1_FORMAT_CONTROL … #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_BIAS_R … #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_BIAS_G … #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_BIAS_B … #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_SCALE_R … #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_SCALE_G … #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX … #define regCNVC_CFG1_FCNV_FP_SCALE_B … #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX … #define regCNVC_CFG1_COLOR_KEYER_CONTROL … #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX … #define regCNVC_CFG1_COLOR_KEYER_ALPHA … #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX … #define regCNVC_CFG1_COLOR_KEYER_RED … #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX … #define regCNVC_CFG1_COLOR_KEYER_GREEN … #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX … #define regCNVC_CFG1_COLOR_KEYER_BLUE … #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX … #define regCNVC_CFG1_ALPHA_2BIT_LUT … #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX … #define regCNVC_CFG1_PRE_DEALPHA … #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_MODE … #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C11_C12 … #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C13_C14 … #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C21_C22 … #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C23_C24 … #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C31_C32 … #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_C33_C34 … #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C11_C12 … #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C13_C14 … #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C21_C22 … #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C23_C24 … #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C31_C32 … #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX … #define regCNVC_CFG1_PRE_CSC_B_C33_C34 … #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX … #define regCNVC_CFG1_CNVC_COEF_FORMAT … #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX … #define regCNVC_CFG1_PRE_DEGAM … #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX … #define regCNVC_CFG1_PRE_REALPHA … #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX … // addressBlock: dcn_dcec_dpp1_dispdec_cm_cur_dispdec // base address: 0x5ac #define regCM_CUR1_CURSOR0_CONTROL … #define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX … #define regCM_CUR1_CURSOR0_COLOR0 … #define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX … #define regCM_CUR1_CURSOR0_COLOR1 … #define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX … #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y … #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX … #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB … #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_MODE … #define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C11_C12_A … #define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C13_C14_A … #define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C21_C22_A … #define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C23_C24_A … #define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C31_C32_A … #define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C33_C34_A … #define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C11_C12_B … #define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C13_C14_B … #define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C21_C22_B … #define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C23_C24_B … #define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C31_C32_B … #define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX … #define regCM_CUR1_CUR0_MATRIX_C33_C34_B … #define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_dpp1_dispdec_dscl_dispdec // base address: 0x5ac #define regDSCL1_SCL_COEF_RAM_TAP_SELECT … #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define regDSCL1_SCL_COEF_RAM_TAP_DATA … #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define regDSCL1_SCL_MODE … #define regDSCL1_SCL_MODE_BASE_IDX … #define regDSCL1_SCL_TAP_CONTROL … #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX … #define regDSCL1_DSCL_CONTROL … #define regDSCL1_DSCL_CONTROL_BASE_IDX … #define regDSCL1_DSCL_2TAP_CONTROL … #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX … #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL … #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO … #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL1_SCL_HORZ_FILTER_INIT … #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX … #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C … #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL1_SCL_HORZ_FILTER_INIT_C … #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO … #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_INIT … #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_INIT_BOT … #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C … #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_INIT_C … #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C … #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define regDSCL1_SCL_BLACK_COLOR … #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX … #define regDSCL1_DSCL_UPDATE … #define regDSCL1_DSCL_UPDATE_BASE_IDX … #define regDSCL1_DSCL_AUTOCAL … #define regDSCL1_DSCL_AUTOCAL_BASE_IDX … #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define regDSCL1_OTG_H_BLANK … #define regDSCL1_OTG_H_BLANK_BASE_IDX … #define regDSCL1_OTG_V_BLANK … #define regDSCL1_OTG_V_BLANK_BASE_IDX … #define regDSCL1_RECOUT_START … #define regDSCL1_RECOUT_START_BASE_IDX … #define regDSCL1_RECOUT_SIZE … #define regDSCL1_RECOUT_SIZE_BASE_IDX … #define regDSCL1_MPC_SIZE … #define regDSCL1_MPC_SIZE_BASE_IDX … #define regDSCL1_LB_DATA_FORMAT … #define regDSCL1_LB_DATA_FORMAT_BASE_IDX … #define regDSCL1_LB_MEMORY_CTRL … #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX … #define regDSCL1_LB_V_COUNTER … #define regDSCL1_LB_V_COUNTER_BASE_IDX … #define regDSCL1_DSCL_MEM_PWR_CTRL … #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX … #define regDSCL1_DSCL_MEM_PWR_STATUS … #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … #define regDSCL1_OBUF_CONTROL … #define regDSCL1_OBUF_CONTROL_BASE_IDX … #define regDSCL1_OBUF_MEM_PWR_CTRL … #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … #define regDSCL1_DSCL_EASF_H_MODE … #define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX … #define regDSCL1_DSCL_EASF_V_MODE … #define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX … #define regDSCL1_DSCL_SC_MODE … #define regDSCL1_DSCL_SC_MODE_BASE_IDX … #define regDSCL1_DSCL_SC_MATRIX_C0C1 … #define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX … #define regDSCL1_DSCL_SC_MATRIX_C2C3 … #define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX … #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN … #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE … #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN … #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE … #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 … #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX … #define regDSCL1_DSCL_EASF_RINGEST_FORCE … #define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF_CNTL … #define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN … #define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF_CNTL … #define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN … #define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7 … #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7 … #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5 … #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5 … #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX … #define regDSCL1_ISHARP_MODE … #define regDSCL1_ISHARP_MODE_BASE_IDX … #define regDSCL1_ISHARP_DELTA_CTRL … #define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX … #define regDSCL1_ISHARP_DELTA_INDEX … #define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX … #define regDSCL1_ISHARP_DELTA_DATA … #define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX … #define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP … #define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX … #define regDSCL1_ISHARP_NOISEDET_THRESHOLD … #define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX … #define regDSCL1_ISHARP_NOISE_GAIN_PWL … #define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG0 … #define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG1 … #define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG2 … #define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG3 … #define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG4 … #define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX … #define regDSCL1_ISHARP_LBA_PWL_SEG5 … #define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX … #define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL … #define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dcn_dcec_dpp1_dispdec_cm_dispdec // base address: 0x5ac #define regCM1_CM_CONTROL … #define regCM1_CM_CONTROL_BASE_IDX … #define regCM1_CM_POST_CSC_CONTROL … #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX … #define regCM1_CM_POST_CSC_C11_C12 … #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX … #define regCM1_CM_POST_CSC_C13_C14 … #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX … #define regCM1_CM_POST_CSC_C21_C22 … #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX … #define regCM1_CM_POST_CSC_C23_C24 … #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX … #define regCM1_CM_POST_CSC_C31_C32 … #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX … #define regCM1_CM_POST_CSC_C33_C34 … #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX … #define regCM1_CM_POST_CSC_B_C11_C12 … #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX … #define regCM1_CM_POST_CSC_B_C13_C14 … #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX … #define regCM1_CM_POST_CSC_B_C21_C22 … #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX … #define regCM1_CM_POST_CSC_B_C23_C24 … #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX … #define regCM1_CM_POST_CSC_B_C31_C32 … #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … #define regCM1_CM_POST_CSC_B_C33_C34 … #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … #define regCM1_CM_BIAS_CR_R … #define regCM1_CM_BIAS_CR_R_BASE_IDX … #define regCM1_CM_BIAS_Y_G_CB_B … #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX … #define regCM1_CM_GAMCOR_CONTROL … #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX … #define regCM1_CM_GAMCOR_LUT_INDEX … #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX … #define regCM1_CM_GAMCOR_LUT_DATA … #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX … #define regCM1_CM_GAMCOR_LUT_CONTROL … #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R … #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R … #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R … #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R … #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R … #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_OFFSET_B … #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_OFFSET_G … #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_OFFSET_R … #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 … #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 … #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 … #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 … #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 … #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 … #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 … #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 … #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 … #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 … #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 … #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 … #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 … #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 … #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 … #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 … #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX … #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 … #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R … #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R … #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R … #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R … #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R … #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_OFFSET_B … #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_OFFSET_G … #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_OFFSET_R … #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 … #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 … #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 … #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 … #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 … #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 … #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 … #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 … #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 … #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 … #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 … #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 … #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 … #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 … #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 … #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 … #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX … #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 … #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX … #define regCM1_CM_HDR_MULT_COEF … #define regCM1_CM_HDR_MULT_COEF_BASE_IDX … #define regCM1_CM_MEM_PWR_CTRL … #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … #define regCM1_CM_MEM_PWR_STATUS … #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … #define regCM1_CM_DEALPHA … #define regCM1_CM_DEALPHA_BASE_IDX … #define regCM1_CM_COEF_FORMAT … #define regCM1_CM_COEF_FORMAT_BASE_IDX … #define regCM1_CM_TEST_DEBUG_INDEX … #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX … #define regCM1_CM_TEST_DEBUG_DATA … #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dpp1_dispdec_dpp_top_dispdec // base address: 0x5ac #define regDPP_TOP1_DPP_CONTROL … #define regDPP_TOP1_DPP_CONTROL_BASE_IDX … #define regDPP_TOP1_DPP_SOFT_RESET … #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX … #define regDPP_TOP1_DPP_CRC_VAL_R_G … #define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX … #define regDPP_TOP1_DPP_CRC_VAL_B_A … #define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX … #define regDPP_TOP1_DPP_CRC_CTRL … #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX … #define regDPP_TOP1_HOST_READ_CONTROL … #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dpp2_dispdec_cnvc_cfg_dispdec // base address: 0xb58 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT … #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define regCNVC_CFG2_FORMAT_CONTROL … #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_BIAS_R … #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_BIAS_G … #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_BIAS_B … #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_SCALE_R … #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_SCALE_G … #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX … #define regCNVC_CFG2_FCNV_FP_SCALE_B … #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX … #define regCNVC_CFG2_COLOR_KEYER_CONTROL … #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX … #define regCNVC_CFG2_COLOR_KEYER_ALPHA … #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX … #define regCNVC_CFG2_COLOR_KEYER_RED … #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX … #define regCNVC_CFG2_COLOR_KEYER_GREEN … #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX … #define regCNVC_CFG2_COLOR_KEYER_BLUE … #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX … #define regCNVC_CFG2_ALPHA_2BIT_LUT … #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX … #define regCNVC_CFG2_PRE_DEALPHA … #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_MODE … #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C11_C12 … #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C13_C14 … #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C21_C22 … #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C23_C24 … #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C31_C32 … #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_C33_C34 … #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C11_C12 … #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C13_C14 … #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C21_C22 … #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C23_C24 … #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C31_C32 … #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX … #define regCNVC_CFG2_PRE_CSC_B_C33_C34 … #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX … #define regCNVC_CFG2_CNVC_COEF_FORMAT … #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX … #define regCNVC_CFG2_PRE_DEGAM … #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX … #define regCNVC_CFG2_PRE_REALPHA … #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX … // addressBlock: dcn_dcec_dpp2_dispdec_cm_cur_dispdec // base address: 0xb58 #define regCM_CUR2_CURSOR0_CONTROL … #define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX … #define regCM_CUR2_CURSOR0_COLOR0 … #define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX … #define regCM_CUR2_CURSOR0_COLOR1 … #define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX … #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y … #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX … #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB … #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_MODE … #define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C11_C12_A … #define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C13_C14_A … #define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C21_C22_A … #define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C23_C24_A … #define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C31_C32_A … #define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C33_C34_A … #define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C11_C12_B … #define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C13_C14_B … #define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C21_C22_B … #define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C23_C24_B … #define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C31_C32_B … #define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX … #define regCM_CUR2_CUR0_MATRIX_C33_C34_B … #define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_dpp2_dispdec_dscl_dispdec // base address: 0xb58 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT … #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define regDSCL2_SCL_COEF_RAM_TAP_DATA … #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define regDSCL2_SCL_MODE … #define regDSCL2_SCL_MODE_BASE_IDX … #define regDSCL2_SCL_TAP_CONTROL … #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX … #define regDSCL2_DSCL_CONTROL … #define regDSCL2_DSCL_CONTROL_BASE_IDX … #define regDSCL2_DSCL_2TAP_CONTROL … #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX … #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL … #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO … #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL2_SCL_HORZ_FILTER_INIT … #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX … #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C … #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL2_SCL_HORZ_FILTER_INIT_C … #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO … #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_INIT … #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_INIT_BOT … #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C … #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_INIT_C … #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C … #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define regDSCL2_SCL_BLACK_COLOR … #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX … #define regDSCL2_DSCL_UPDATE … #define regDSCL2_DSCL_UPDATE_BASE_IDX … #define regDSCL2_DSCL_AUTOCAL … #define regDSCL2_DSCL_AUTOCAL_BASE_IDX … #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define regDSCL2_OTG_H_BLANK … #define regDSCL2_OTG_H_BLANK_BASE_IDX … #define regDSCL2_OTG_V_BLANK … #define regDSCL2_OTG_V_BLANK_BASE_IDX … #define regDSCL2_RECOUT_START … #define regDSCL2_RECOUT_START_BASE_IDX … #define regDSCL2_RECOUT_SIZE … #define regDSCL2_RECOUT_SIZE_BASE_IDX … #define regDSCL2_MPC_SIZE … #define regDSCL2_MPC_SIZE_BASE_IDX … #define regDSCL2_LB_DATA_FORMAT … #define regDSCL2_LB_DATA_FORMAT_BASE_IDX … #define regDSCL2_LB_MEMORY_CTRL … #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX … #define regDSCL2_LB_V_COUNTER … #define regDSCL2_LB_V_COUNTER_BASE_IDX … #define regDSCL2_DSCL_MEM_PWR_CTRL … #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … #define regDSCL2_DSCL_MEM_PWR_STATUS … #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … #define regDSCL2_OBUF_CONTROL … #define regDSCL2_OBUF_CONTROL_BASE_IDX … #define regDSCL2_OBUF_MEM_PWR_CTRL … #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX … #define regDSCL2_DSCL_EASF_H_MODE … #define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX … #define regDSCL2_DSCL_EASF_V_MODE … #define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX … #define regDSCL2_DSCL_SC_MODE … #define regDSCL2_DSCL_SC_MODE_BASE_IDX … #define regDSCL2_DSCL_SC_MATRIX_C0C1 … #define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX … #define regDSCL2_DSCL_SC_MATRIX_C2C3 … #define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX … #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN … #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE … #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN … #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE … #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 … #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX … #define regDSCL2_DSCL_EASF_RINGEST_FORCE … #define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF_CNTL … #define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN … #define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF_CNTL … #define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN … #define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7 … #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7 … #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5 … #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5 … #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX … #define regDSCL2_ISHARP_MODE … #define regDSCL2_ISHARP_MODE_BASE_IDX … #define regDSCL2_ISHARP_DELTA_CTRL … #define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX … #define regDSCL2_ISHARP_DELTA_INDEX … #define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX … #define regDSCL2_ISHARP_DELTA_DATA … #define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX … #define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP … #define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX … #define regDSCL2_ISHARP_NOISEDET_THRESHOLD … #define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX … #define regDSCL2_ISHARP_NOISE_GAIN_PWL … #define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG0 … #define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG1 … #define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG2 … #define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG3 … #define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG4 … #define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX … #define regDSCL2_ISHARP_LBA_PWL_SEG5 … #define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX … #define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL … #define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dcn_dcec_dpp2_dispdec_cm_dispdec // base address: 0xb58 #define regCM2_CM_CONTROL … #define regCM2_CM_CONTROL_BASE_IDX … #define regCM2_CM_POST_CSC_CONTROL … #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX … #define regCM2_CM_POST_CSC_C11_C12 … #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX … #define regCM2_CM_POST_CSC_C13_C14 … #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX … #define regCM2_CM_POST_CSC_C21_C22 … #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX … #define regCM2_CM_POST_CSC_C23_C24 … #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX … #define regCM2_CM_POST_CSC_C31_C32 … #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX … #define regCM2_CM_POST_CSC_C33_C34 … #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX … #define regCM2_CM_POST_CSC_B_C11_C12 … #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX … #define regCM2_CM_POST_CSC_B_C13_C14 … #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX … #define regCM2_CM_POST_CSC_B_C21_C22 … #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX … #define regCM2_CM_POST_CSC_B_C23_C24 … #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX … #define regCM2_CM_POST_CSC_B_C31_C32 … #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX … #define regCM2_CM_POST_CSC_B_C33_C34 … #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX … #define regCM2_CM_BIAS_CR_R … #define regCM2_CM_BIAS_CR_R_BASE_IDX … #define regCM2_CM_BIAS_Y_G_CB_B … #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX … #define regCM2_CM_GAMCOR_CONTROL … #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX … #define regCM2_CM_GAMCOR_LUT_INDEX … #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX … #define regCM2_CM_GAMCOR_LUT_DATA … #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX … #define regCM2_CM_GAMCOR_LUT_CONTROL … #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R … #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R … #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R … #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R … #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R … #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_OFFSET_B … #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_OFFSET_G … #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_OFFSET_R … #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 … #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 … #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 … #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 … #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 … #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 … #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 … #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 … #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 … #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 … #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 … #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 … #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 … #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 … #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 … #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 … #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX … #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 … #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R … #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R … #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R … #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R … #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R … #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_OFFSET_B … #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_OFFSET_G … #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_OFFSET_R … #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 … #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 … #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 … #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 … #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 … #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 … #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 … #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 … #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 … #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 … #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 … #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 … #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 … #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 … #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 … #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 … #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX … #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 … #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX … #define regCM2_CM_HDR_MULT_COEF … #define regCM2_CM_HDR_MULT_COEF_BASE_IDX … #define regCM2_CM_MEM_PWR_CTRL … #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX … #define regCM2_CM_MEM_PWR_STATUS … #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX … #define regCM2_CM_DEALPHA … #define regCM2_CM_DEALPHA_BASE_IDX … #define regCM2_CM_COEF_FORMAT … #define regCM2_CM_COEF_FORMAT_BASE_IDX … #define regCM2_CM_TEST_DEBUG_INDEX … #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX … #define regCM2_CM_TEST_DEBUG_DATA … #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dpp2_dispdec_dpp_top_dispdec // base address: 0xb58 #define regDPP_TOP2_DPP_CONTROL … #define regDPP_TOP2_DPP_CONTROL_BASE_IDX … #define regDPP_TOP2_DPP_SOFT_RESET … #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX … #define regDPP_TOP2_DPP_CRC_VAL_R_G … #define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX … #define regDPP_TOP2_DPP_CRC_VAL_B_A … #define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX … #define regDPP_TOP2_DPP_CRC_CTRL … #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX … #define regDPP_TOP2_HOST_READ_CONTROL … #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dpp3_dispdec_cnvc_cfg_dispdec // base address: 0x1104 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT … #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define regCNVC_CFG3_FORMAT_CONTROL … #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_BIAS_R … #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_BIAS_G … #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_BIAS_B … #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_SCALE_R … #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_SCALE_G … #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX … #define regCNVC_CFG3_FCNV_FP_SCALE_B … #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX … #define regCNVC_CFG3_COLOR_KEYER_CONTROL … #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX … #define regCNVC_CFG3_COLOR_KEYER_ALPHA … #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX … #define regCNVC_CFG3_COLOR_KEYER_RED … #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX … #define regCNVC_CFG3_COLOR_KEYER_GREEN … #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX … #define regCNVC_CFG3_COLOR_KEYER_BLUE … #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX … #define regCNVC_CFG3_ALPHA_2BIT_LUT … #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX … #define regCNVC_CFG3_PRE_DEALPHA … #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_MODE … #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C11_C12 … #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C13_C14 … #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C21_C22 … #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C23_C24 … #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C31_C32 … #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_C33_C34 … #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C13_C14 … #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C21_C22 … #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C23_C24 … #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C31_C32 … #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX … #define regCNVC_CFG3_PRE_CSC_B_C33_C34 … #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX … #define regCNVC_CFG3_CNVC_COEF_FORMAT … #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX … #define regCNVC_CFG3_PRE_DEGAM … #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX … #define regCNVC_CFG3_PRE_REALPHA … #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX … // addressBlock: dcn_dcec_dpp3_dispdec_cm_cur_dispdec // base address: 0x1104 #define regCM_CUR3_CURSOR0_CONTROL … #define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX … #define regCM_CUR3_CURSOR0_COLOR0 … #define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX … #define regCM_CUR3_CURSOR0_COLOR1 … #define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX … #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y … #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX … #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB … #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_MODE … #define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C11_C12_A … #define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C13_C14_A … #define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C21_C22_A … #define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C23_C24_A … #define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C31_C32_A … #define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C33_C34_A … #define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C11_C12_B … #define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C13_C14_B … #define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C21_C22_B … #define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C23_C24_B … #define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C31_C32_B … #define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX … #define regCM_CUR3_CUR0_MATRIX_C33_C34_B … #define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_dpp3_dispdec_dscl_dispdec // base address: 0x1104 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT … #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define regDSCL3_SCL_COEF_RAM_TAP_DATA … #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define regDSCL3_SCL_MODE … #define regDSCL3_SCL_MODE_BASE_IDX … #define regDSCL3_SCL_TAP_CONTROL … #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … #define regDSCL3_DSCL_CONTROL … #define regDSCL3_DSCL_CONTROL_BASE_IDX … #define regDSCL3_DSCL_2TAP_CONTROL … #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX … #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL … #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO … #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL3_SCL_HORZ_FILTER_INIT … #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX … #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C … #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL3_SCL_HORZ_FILTER_INIT_C … #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO … #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_INIT … #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_INIT_BOT … #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C … #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_INIT_C … #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C … #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define regDSCL3_SCL_BLACK_COLOR … #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX … #define regDSCL3_DSCL_UPDATE … #define regDSCL3_DSCL_UPDATE_BASE_IDX … #define regDSCL3_DSCL_AUTOCAL … #define regDSCL3_DSCL_AUTOCAL_BASE_IDX … #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define regDSCL3_OTG_H_BLANK … #define regDSCL3_OTG_H_BLANK_BASE_IDX … #define regDSCL3_OTG_V_BLANK … #define regDSCL3_OTG_V_BLANK_BASE_IDX … #define regDSCL3_RECOUT_START … #define regDSCL3_RECOUT_START_BASE_IDX … #define regDSCL3_RECOUT_SIZE … #define regDSCL3_RECOUT_SIZE_BASE_IDX … #define regDSCL3_MPC_SIZE … #define regDSCL3_MPC_SIZE_BASE_IDX … #define regDSCL3_LB_DATA_FORMAT … #define regDSCL3_LB_DATA_FORMAT_BASE_IDX … #define regDSCL3_LB_MEMORY_CTRL … #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX … #define regDSCL3_LB_V_COUNTER … #define regDSCL3_LB_V_COUNTER_BASE_IDX … #define regDSCL3_DSCL_MEM_PWR_CTRL … #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX … #define regDSCL3_DSCL_MEM_PWR_STATUS … #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … #define regDSCL3_OBUF_CONTROL … #define regDSCL3_OBUF_CONTROL_BASE_IDX … #define regDSCL3_OBUF_MEM_PWR_CTRL … #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX … #define regDSCL3_DSCL_EASF_H_MODE … #define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX … #define regDSCL3_DSCL_EASF_V_MODE … #define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX … #define regDSCL3_DSCL_SC_MODE … #define regDSCL3_DSCL_SC_MODE_BASE_IDX … #define regDSCL3_DSCL_SC_MATRIX_C0C1 … #define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX … #define regDSCL3_DSCL_SC_MATRIX_C2C3 … #define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX … #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN … #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE … #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN … #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX … #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE … #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 … #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX … #define regDSCL3_DSCL_EASF_RINGEST_FORCE … #define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF_CNTL … #define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN … #define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF_CNTL … #define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN … #define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7 … #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7 … #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5 … #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5 … #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX … #define regDSCL3_ISHARP_MODE … #define regDSCL3_ISHARP_MODE_BASE_IDX … #define regDSCL3_ISHARP_DELTA_CTRL … #define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX … #define regDSCL3_ISHARP_DELTA_INDEX … #define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX … #define regDSCL3_ISHARP_DELTA_DATA … #define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX … #define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP … #define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX … #define regDSCL3_ISHARP_NOISEDET_THRESHOLD … #define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX … #define regDSCL3_ISHARP_NOISE_GAIN_PWL … #define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG0 … #define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG1 … #define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG2 … #define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG3 … #define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG4 … #define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX … #define regDSCL3_ISHARP_LBA_PWL_SEG5 … #define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX … #define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL … #define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dcn_dcec_dpp3_dispdec_cm_dispdec // base address: 0x1104 #define regCM3_CM_CONTROL … #define regCM3_CM_CONTROL_BASE_IDX … #define regCM3_CM_POST_CSC_CONTROL … #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX … #define regCM3_CM_POST_CSC_C11_C12 … #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX … #define regCM3_CM_POST_CSC_C13_C14 … #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX … #define regCM3_CM_POST_CSC_C21_C22 … #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX … #define regCM3_CM_POST_CSC_C23_C24 … #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX … #define regCM3_CM_POST_CSC_C31_C32 … #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX … #define regCM3_CM_POST_CSC_C33_C34 … #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX … #define regCM3_CM_POST_CSC_B_C11_C12 … #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … #define regCM3_CM_POST_CSC_B_C13_C14 … #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX … #define regCM3_CM_POST_CSC_B_C21_C22 … #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX … #define regCM3_CM_POST_CSC_B_C23_C24 … #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX … #define regCM3_CM_POST_CSC_B_C31_C32 … #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX … #define regCM3_CM_POST_CSC_B_C33_C34 … #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX … #define regCM3_CM_BIAS_CR_R … #define regCM3_CM_BIAS_CR_R_BASE_IDX … #define regCM3_CM_BIAS_Y_G_CB_B … #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX … #define regCM3_CM_GAMCOR_CONTROL … #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX … #define regCM3_CM_GAMCOR_LUT_INDEX … #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX … #define regCM3_CM_GAMCOR_LUT_DATA … #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX … #define regCM3_CM_GAMCOR_LUT_CONTROL … #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R … #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R … #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R … #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R … #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R … #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_OFFSET_B … #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_OFFSET_G … #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_OFFSET_R … #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 … #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 … #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 … #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 … #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 … #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 … #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 … #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 … #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 … #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 … #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 … #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 … #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 … #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 … #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 … #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 … #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX … #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 … #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R … #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R … #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R … #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R … #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R … #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_OFFSET_B … #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_OFFSET_G … #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_OFFSET_R … #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 … #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 … #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 … #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 … #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 … #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 … #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 … #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 … #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 … #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 … #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 … #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 … #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 … #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 … #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 … #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 … #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX … #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 … #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX … #define regCM3_CM_HDR_MULT_COEF … #define regCM3_CM_HDR_MULT_COEF_BASE_IDX … #define regCM3_CM_MEM_PWR_CTRL … #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX … #define regCM3_CM_MEM_PWR_STATUS … #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX … #define regCM3_CM_DEALPHA … #define regCM3_CM_DEALPHA_BASE_IDX … #define regCM3_CM_COEF_FORMAT … #define regCM3_CM_COEF_FORMAT_BASE_IDX … #define regCM3_CM_TEST_DEBUG_INDEX … #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX … #define regCM3_CM_TEST_DEBUG_DATA … #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dpp3_dispdec_dpp_top_dispdec // base address: 0x1104 #define regDPP_TOP3_DPP_CONTROL … #define regDPP_TOP3_DPP_CONTROL_BASE_IDX … #define regDPP_TOP3_DPP_SOFT_RESET … #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX … #define regDPP_TOP3_DPP_CRC_VAL_R_G … #define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX … #define regDPP_TOP3_DPP_CRC_VAL_B_A … #define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX … #define regDPP_TOP3_DPP_CRC_CTRL … #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX … #define regDPP_TOP3_HOST_READ_CONTROL … #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc0_dispdec // base address: 0x0 #define regMPCC0_MPCC_TOP_SEL … #define regMPCC0_MPCC_TOP_SEL_BASE_IDX … #define regMPCC0_MPCC_BOT_SEL … #define regMPCC0_MPCC_BOT_SEL_BASE_IDX … #define regMPCC0_MPCC_OPP_ID … #define regMPCC0_MPCC_OPP_ID_BASE_IDX … #define regMPCC0_MPCC_CONTROL … #define regMPCC0_MPCC_CONTROL_BASE_IDX … #define regMPCC0_MPCC_SM_CONTROL … #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX … #define regMPCC0_MPCC_UPDATE_LOCK_SEL … #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define regMPCC0_MPCC_TOP_GAIN … #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX … #define regMPCC0_MPCC_BOT_GAIN_INSIDE … #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE … #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL … #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX … #define regMPCC0_MPCC_BG_R_CR … #define regMPCC0_MPCC_BG_R_CR_BASE_IDX … #define regMPCC0_MPCC_BG_G_Y … #define regMPCC0_MPCC_BG_G_Y_BASE_IDX … #define regMPCC0_MPCC_BG_B_CB … #define regMPCC0_MPCC_BG_B_CB_BASE_IDX … #define regMPCC0_MPCC_MEM_PWR_CTRL … #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … #define regMPCC0_MPCC_STATUS … #define regMPCC0_MPCC_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc1_dispdec // base address: 0x54 #define regMPCC1_MPCC_TOP_SEL … #define regMPCC1_MPCC_TOP_SEL_BASE_IDX … #define regMPCC1_MPCC_BOT_SEL … #define regMPCC1_MPCC_BOT_SEL_BASE_IDX … #define regMPCC1_MPCC_OPP_ID … #define regMPCC1_MPCC_OPP_ID_BASE_IDX … #define regMPCC1_MPCC_CONTROL … #define regMPCC1_MPCC_CONTROL_BASE_IDX … #define regMPCC1_MPCC_SM_CONTROL … #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … #define regMPCC1_MPCC_UPDATE_LOCK_SEL … #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define regMPCC1_MPCC_TOP_GAIN … #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX … #define regMPCC1_MPCC_BOT_GAIN_INSIDE … #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE … #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL … #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX … #define regMPCC1_MPCC_BG_R_CR … #define regMPCC1_MPCC_BG_R_CR_BASE_IDX … #define regMPCC1_MPCC_BG_G_Y … #define regMPCC1_MPCC_BG_G_Y_BASE_IDX … #define regMPCC1_MPCC_BG_B_CB … #define regMPCC1_MPCC_BG_B_CB_BASE_IDX … #define regMPCC1_MPCC_MEM_PWR_CTRL … #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX … #define regMPCC1_MPCC_STATUS … #define regMPCC1_MPCC_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc2_dispdec // base address: 0xa8 #define regMPCC2_MPCC_TOP_SEL … #define regMPCC2_MPCC_TOP_SEL_BASE_IDX … #define regMPCC2_MPCC_BOT_SEL … #define regMPCC2_MPCC_BOT_SEL_BASE_IDX … #define regMPCC2_MPCC_OPP_ID … #define regMPCC2_MPCC_OPP_ID_BASE_IDX … #define regMPCC2_MPCC_CONTROL … #define regMPCC2_MPCC_CONTROL_BASE_IDX … #define regMPCC2_MPCC_SM_CONTROL … #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX … #define regMPCC2_MPCC_UPDATE_LOCK_SEL … #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define regMPCC2_MPCC_TOP_GAIN … #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX … #define regMPCC2_MPCC_BOT_GAIN_INSIDE … #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE … #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL … #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX … #define regMPCC2_MPCC_BG_R_CR … #define regMPCC2_MPCC_BG_R_CR_BASE_IDX … #define regMPCC2_MPCC_BG_G_Y … #define regMPCC2_MPCC_BG_G_Y_BASE_IDX … #define regMPCC2_MPCC_BG_B_CB … #define regMPCC2_MPCC_BG_B_CB_BASE_IDX … #define regMPCC2_MPCC_MEM_PWR_CTRL … #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX … #define regMPCC2_MPCC_STATUS … #define regMPCC2_MPCC_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc3_dispdec // base address: 0xfc #define regMPCC3_MPCC_TOP_SEL … #define regMPCC3_MPCC_TOP_SEL_BASE_IDX … #define regMPCC3_MPCC_BOT_SEL … #define regMPCC3_MPCC_BOT_SEL_BASE_IDX … #define regMPCC3_MPCC_OPP_ID … #define regMPCC3_MPCC_OPP_ID_BASE_IDX … #define regMPCC3_MPCC_CONTROL … #define regMPCC3_MPCC_CONTROL_BASE_IDX … #define regMPCC3_MPCC_SM_CONTROL … #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX … #define regMPCC3_MPCC_UPDATE_LOCK_SEL … #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define regMPCC3_MPCC_TOP_GAIN … #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX … #define regMPCC3_MPCC_BOT_GAIN_INSIDE … #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE … #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL … #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX … #define regMPCC3_MPCC_BG_R_CR … #define regMPCC3_MPCC_BG_R_CR_BASE_IDX … #define regMPCC3_MPCC_BG_G_Y … #define regMPCC3_MPCC_BG_G_Y_BASE_IDX … #define regMPCC3_MPCC_BG_B_CB … #define regMPCC3_MPCC_BG_B_CB_BASE_IDX … #define regMPCC3_MPCC_MEM_PWR_CTRL … #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … #define regMPCC3_MPCC_STATUS … #define regMPCC3_MPCC_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpc_cfg_dispdec // base address: 0x0 #define regMPC_CLOCK_CONTROL … #define regMPC_CLOCK_CONTROL_BASE_IDX … #define regMPC_SOFT_RESET … #define regMPC_SOFT_RESET_BASE_IDX … #define regMPC_CRC_CTRL … #define regMPC_CRC_CTRL_BASE_IDX … #define regMPC_CRC_SEL_CONTROL … #define regMPC_CRC_SEL_CONTROL_BASE_IDX … #define regMPC_CRC_RESULT_AR … #define regMPC_CRC_RESULT_AR_BASE_IDX … #define regMPC_CRC_RESULT_GB … #define regMPC_CRC_RESULT_GB_BASE_IDX … #define regMPC_CRC_RESULT_C … #define regMPC_CRC_RESULT_C_BASE_IDX … #define regMPC_BYPASS_BG_AR … #define regMPC_BYPASS_BG_AR_BASE_IDX … #define regMPC_BYPASS_BG_GB … #define regMPC_BYPASS_BG_GB_BASE_IDX … #define regMPC_HOST_READ_CONTROL … #define regMPC_HOST_READ_CONTROL_BASE_IDX … #define regMPC_DPP_PENDING_STATUS … #define regMPC_DPP_PENDING_STATUS_BASE_IDX … #define regMPC_PENDING_STATUS_MISC … #define regMPC_PENDING_STATUS_MISC_BASE_IDX … #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 … #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX … #define regADR_CFG_VUPDATE_LOCK_SET0 … #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX … #define regADR_VUPDATE_LOCK_SET0 … #define regADR_VUPDATE_LOCK_SET0_BASE_IDX … #define regCFG_VUPDATE_LOCK_SET0 … #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX … #define regCUR_VUPDATE_LOCK_SET0 … #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX … #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 … #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX … #define regADR_CFG_VUPDATE_LOCK_SET1 … #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX … #define regADR_VUPDATE_LOCK_SET1 … #define regADR_VUPDATE_LOCK_SET1_BASE_IDX … #define regCFG_VUPDATE_LOCK_SET1 … #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX … #define regCUR_VUPDATE_LOCK_SET1 … #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX … #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 … #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX … #define regADR_CFG_VUPDATE_LOCK_SET2 … #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX … #define regADR_VUPDATE_LOCK_SET2 … #define regADR_VUPDATE_LOCK_SET2_BASE_IDX … #define regCFG_VUPDATE_LOCK_SET2 … #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX … #define regCUR_VUPDATE_LOCK_SET2 … #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX … #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 … #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX … #define regADR_CFG_VUPDATE_LOCK_SET3 … #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX … #define regADR_VUPDATE_LOCK_SET3 … #define regADR_VUPDATE_LOCK_SET3_BASE_IDX … #define regCFG_VUPDATE_LOCK_SET3 … #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX … #define regCUR_VUPDATE_LOCK_SET3 … #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX … #define regHUBP0_3DLUT_FL_CONFIG … #define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX … #define regHUBP0_3DLUT_FL_BIAS_SCALE … #define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX … #define regHUBP1_3DLUT_FL_CONFIG … #define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX … #define regHUBP1_3DLUT_FL_BIAS_SCALE … #define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX … #define regHUBP2_3DLUT_FL_CONFIG … #define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX … #define regHUBP2_3DLUT_FL_BIAS_SCALE … #define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX … #define regHUBP3_3DLUT_FL_CONFIG … #define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX … #define regHUBP3_3DLUT_FL_BIAS_SCALE … #define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX … #define regMPC_DWB0_MUX … #define regMPC_DWB0_MUX_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_ogam0_dispdec // base address: 0x0 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL … #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX … #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA … #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL … #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 … #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 … #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE … #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B … #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_ogam1_dispdec // base address: 0x178 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL … #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX … #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA … #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL … #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 … #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 … #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE … #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B … #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_ogam2_dispdec // base address: 0x2f0 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL … #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX … #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA … #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL … #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 … #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 … #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE … #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B … #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_ogam3_dispdec // base address: 0x468 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL … #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX … #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA … #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL … #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 … #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 … #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE … #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B … #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_mcm0_dispdec // base address: 0x0 #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL … #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK … #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 … #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE … #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA … #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT … #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL … #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B … #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL … #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL … #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 … #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE … #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE … #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL … #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT … #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX … #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS … #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_mcm1_dispdec // base address: 0x2c0 #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL … #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK … #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 … #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE … #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA … #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT … #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL … #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B … #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL … #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL … #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 … #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE … #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE … #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL … #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT … #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX … #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS … #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_mcm2_dispdec // base address: 0x580 #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL … #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK … #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 … #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE … #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA … #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT … #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL … #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B … #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL … #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL … #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 … #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE … #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE … #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL … #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT … #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX … #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS … #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpcc_mcm3_dispdec // base address: 0x840 #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL … #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK … #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 … #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE … #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA … #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT … #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL … #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B … #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL … #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL … #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 … #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE … #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT … #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE … #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B … #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL … #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT … #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX … #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS … #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX … // addressBlock: dcn_dcec_mpc_mpc_ocsc_dispdec // base address: 0x0 #define regMPC_OUT0_MUX … #define regMPC_OUT0_MUX_BASE_IDX … #define regMPC_OUT0_DENORM_CONTROL … #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX … #define regMPC_OUT0_DENORM_CLAMP_G_Y … #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX … #define regMPC_OUT0_DENORM_CLAMP_B_CB … #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX … #define regMPC_OUT1_MUX … #define regMPC_OUT1_MUX_BASE_IDX … #define regMPC_OUT1_DENORM_CONTROL … #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX … #define regMPC_OUT1_DENORM_CLAMP_G_Y … #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX … #define regMPC_OUT1_DENORM_CLAMP_B_CB … #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX … #define regMPC_OUT2_MUX … #define regMPC_OUT2_MUX_BASE_IDX … #define regMPC_OUT2_DENORM_CONTROL … #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX … #define regMPC_OUT2_DENORM_CLAMP_G_Y … #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX … #define regMPC_OUT2_DENORM_CLAMP_B_CB … #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX … #define regMPC_OUT3_MUX … #define regMPC_OUT3_MUX_BASE_IDX … #define regMPC_OUT3_DENORM_CONTROL … #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX … #define regMPC_OUT3_DENORM_CLAMP_G_Y … #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX … #define regMPC_OUT3_DENORM_CLAMP_B_CB … #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX … #define regMPC_OUT_CSC_COEF_FORMAT … #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX … #define regMPC_OUT0_CSC_MODE … #define regMPC_OUT0_CSC_MODE_BASE_IDX … #define regMPC_OUT0_CSC_C11_C12_A … #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX … #define regMPC_OUT0_CSC_C13_C14_A … #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX … #define regMPC_OUT0_CSC_C21_C22_A … #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX … #define regMPC_OUT0_CSC_C23_C24_A … #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX … #define regMPC_OUT0_CSC_C31_C32_A … #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX … #define regMPC_OUT0_CSC_C33_C34_A … #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX … #define regMPC_OUT0_CSC_C11_C12_B … #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX … #define regMPC_OUT0_CSC_C13_C14_B … #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX … #define regMPC_OUT0_CSC_C21_C22_B … #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX … #define regMPC_OUT0_CSC_C23_C24_B … #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX … #define regMPC_OUT0_CSC_C31_C32_B … #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX … #define regMPC_OUT0_CSC_C33_C34_B … #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX … #define regMPC_OUT1_CSC_MODE … #define regMPC_OUT1_CSC_MODE_BASE_IDX … #define regMPC_OUT1_CSC_C11_C12_A … #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX … #define regMPC_OUT1_CSC_C13_C14_A … #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX … #define regMPC_OUT1_CSC_C21_C22_A … #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX … #define regMPC_OUT1_CSC_C23_C24_A … #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX … #define regMPC_OUT1_CSC_C31_C32_A … #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX … #define regMPC_OUT1_CSC_C33_C34_A … #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX … #define regMPC_OUT1_CSC_C11_C12_B … #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX … #define regMPC_OUT1_CSC_C13_C14_B … #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX … #define regMPC_OUT1_CSC_C21_C22_B … #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX … #define regMPC_OUT1_CSC_C23_C24_B … #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX … #define regMPC_OUT1_CSC_C31_C32_B … #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX … #define regMPC_OUT1_CSC_C33_C34_B … #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX … #define regMPC_OUT2_CSC_MODE … #define regMPC_OUT2_CSC_MODE_BASE_IDX … #define regMPC_OUT2_CSC_C11_C12_A … #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX … #define regMPC_OUT2_CSC_C13_C14_A … #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX … #define regMPC_OUT2_CSC_C21_C22_A … #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX … #define regMPC_OUT2_CSC_C23_C24_A … #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX … #define regMPC_OUT2_CSC_C31_C32_A … #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX … #define regMPC_OUT2_CSC_C33_C34_A … #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX … #define regMPC_OUT2_CSC_C11_C12_B … #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX … #define regMPC_OUT2_CSC_C13_C14_B … #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX … #define regMPC_OUT2_CSC_C21_C22_B … #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX … #define regMPC_OUT2_CSC_C23_C24_B … #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX … #define regMPC_OUT2_CSC_C31_C32_B … #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX … #define regMPC_OUT2_CSC_C33_C34_B … #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX … #define regMPC_OUT3_CSC_MODE … #define regMPC_OUT3_CSC_MODE_BASE_IDX … #define regMPC_OUT3_CSC_C11_C12_A … #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX … #define regMPC_OUT3_CSC_C13_C14_A … #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX … #define regMPC_OUT3_CSC_C21_C22_A … #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX … #define regMPC_OUT3_CSC_C23_C24_A … #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX … #define regMPC_OUT3_CSC_C31_C32_A … #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX … #define regMPC_OUT3_CSC_C33_C34_A … #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX … #define regMPC_OUT3_CSC_C11_C12_B … #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX … #define regMPC_OUT3_CSC_C13_C14_B … #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX … #define regMPC_OUT3_CSC_C21_C22_B … #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX … #define regMPC_OUT3_CSC_C23_C24_B … #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX … #define regMPC_OUT3_CSC_C31_C32_B … #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX … #define regMPC_OUT3_CSC_C33_C34_B … #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX … #define regMPC_OCSC_TEST_DEBUG_INDEX … #define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX … #define regMPC_OCSC_TEST_DEBUG_DATA … #define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_opp_abm0_dispdec // base address: 0x0 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define regABM0_BL1_PWM_USER_LEVEL … #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX … #define regABM0_BL1_PWM_TARGET_ABM_LEVEL … #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL … #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE … #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE … #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define regABM0_BL1_PWM_ABM_CNTL … #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX … #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define regABM0_BL1_PWM_GRP2_REG_LOCK … #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define regABM0_DC_ABM1_CNTL … #define regABM0_DC_ABM1_CNTL_BASE_IDX … #define regABM0_DC_ABM1_IPCSC_COEFF_SEL … #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define regABM0_DC_ABM1_ACE_PWL_CNTL … #define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX … #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA … #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX … #define regABM0_DC_ABM1_ACE_THRES_DATA … #define regABM0_DC_ABM1_ACE_THRES_DATA_BASE_IDX … #define regABM0_DC_ABM1_ACE_CNTL_MISC … #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS … #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define regABM0_DC_ABM1_HG_MISC_CTRL … #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define regABM0_DC_ABM1_LS_SUM_OF_LUMA … #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA … #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define regABM0_DC_ABM1_LS_PIXEL_COUNT … #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM0_DC_ABM1_HG_SAMPLE_RATE … #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define regABM0_DC_ABM1_LS_SAMPLE_RATE … #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG … #define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX … #define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_RESULT_INDEX … #define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX … #define regABM0_DC_ABM1_HG_RESULT_DATA … #define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX … #define regABM0_DC_ABM1_BL_MASTER_LOCK … #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dcn_dcec_opp_abm1_dispdec // base address: 0x104 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define regABM1_BL1_PWM_USER_LEVEL … #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX … #define regABM1_BL1_PWM_TARGET_ABM_LEVEL … #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL … #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE … #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE … #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define regABM1_BL1_PWM_ABM_CNTL … #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX … #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define regABM1_BL1_PWM_GRP2_REG_LOCK … #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define regABM1_DC_ABM1_CNTL … #define regABM1_DC_ABM1_CNTL_BASE_IDX … #define regABM1_DC_ABM1_IPCSC_COEFF_SEL … #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define regABM1_DC_ABM1_ACE_PWL_CNTL … #define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX … #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA … #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX … #define regABM1_DC_ABM1_ACE_THRES_DATA … #define regABM1_DC_ABM1_ACE_THRES_DATA_BASE_IDX … #define regABM1_DC_ABM1_ACE_CNTL_MISC … #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS … #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define regABM1_DC_ABM1_HG_MISC_CTRL … #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define regABM1_DC_ABM1_LS_SUM_OF_LUMA … #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA … #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define regABM1_DC_ABM1_LS_PIXEL_COUNT … #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM1_DC_ABM1_HG_SAMPLE_RATE … #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define regABM1_DC_ABM1_LS_SAMPLE_RATE … #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG … #define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX … #define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_RESULT_INDEX … #define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX … #define regABM1_DC_ABM1_HG_RESULT_DATA … #define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX … #define regABM1_DC_ABM1_BL_MASTER_LOCK … #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dcn_dcec_opp_abm2_dispdec // base address: 0x208 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define regABM2_BL1_PWM_USER_LEVEL … #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX … #define regABM2_BL1_PWM_TARGET_ABM_LEVEL … #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL … #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE … #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE … #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define regABM2_BL1_PWM_ABM_CNTL … #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX … #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define regABM2_BL1_PWM_GRP2_REG_LOCK … #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define regABM2_DC_ABM1_CNTL … #define regABM2_DC_ABM1_CNTL_BASE_IDX … #define regABM2_DC_ABM1_IPCSC_COEFF_SEL … #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define regABM2_DC_ABM1_ACE_PWL_CNTL … #define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX … #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA … #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX … #define regABM2_DC_ABM1_ACE_THRES_DATA … #define regABM2_DC_ABM1_ACE_THRES_DATA_BASE_IDX … #define regABM2_DC_ABM1_ACE_CNTL_MISC … #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS … #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define regABM2_DC_ABM1_HG_MISC_CTRL … #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define regABM2_DC_ABM1_LS_SUM_OF_LUMA … #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA … #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define regABM2_DC_ABM1_LS_PIXEL_COUNT … #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM2_DC_ABM1_HG_SAMPLE_RATE … #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define regABM2_DC_ABM1_LS_SAMPLE_RATE … #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG … #define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX … #define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_RESULT_INDEX … #define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX … #define regABM2_DC_ABM1_HG_RESULT_DATA … #define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX … #define regABM2_DC_ABM1_BL_MASTER_LOCK … #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dcn_dcec_opp_abm3_dispdec // base address: 0x30c #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define regABM3_BL1_PWM_USER_LEVEL … #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX … #define regABM3_BL1_PWM_TARGET_ABM_LEVEL … #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL … #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE … #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE … #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define regABM3_BL1_PWM_ABM_CNTL … #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX … #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define regABM3_BL1_PWM_GRP2_REG_LOCK … #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define regABM3_DC_ABM1_CNTL … #define regABM3_DC_ABM1_CNTL_BASE_IDX … #define regABM3_DC_ABM1_IPCSC_COEFF_SEL … #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define regABM3_DC_ABM1_ACE_PWL_CNTL … #define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX … #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA … #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX … #define regABM3_DC_ABM1_ACE_THRES_DATA … #define regABM3_DC_ABM1_ACE_THRES_DATA_BASE_IDX … #define regABM3_DC_ABM1_ACE_CNTL_MISC … #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS … #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define regABM3_DC_ABM1_HG_MISC_CTRL … #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define regABM3_DC_ABM1_LS_SUM_OF_LUMA … #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA … #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define regABM3_DC_ABM1_LS_PIXEL_COUNT … #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define regABM3_DC_ABM1_HG_SAMPLE_RATE … #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define regABM3_DC_ABM1_LS_SAMPLE_RATE … #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG … #define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX … #define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_RESULT_INDEX … #define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX … #define regABM3_DC_ABM1_HG_RESULT_DATA … #define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX … #define regABM3_DC_ABM1_BL_MASTER_LOCK … #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dcn_dcec_opp_dpg0_dispdec // base address: 0x0 #define regDPG0_DPG_CONTROL … #define regDPG0_DPG_CONTROL_BASE_IDX … #define regDPG0_DPG_RAMP_CONTROL … #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX … #define regDPG0_DPG_DIMENSIONS … #define regDPG0_DPG_DIMENSIONS_BASE_IDX … #define regDPG0_DPG_COLOUR_R_CR … #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX … #define regDPG0_DPG_COLOUR_G_Y … #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX … #define regDPG0_DPG_COLOUR_B_CB … #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX … #define regDPG0_DPG_OFFSET_SEGMENT … #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX … #define regDPG0_DPG_STATUS … #define regDPG0_DPG_STATUS_BASE_IDX … // addressBlock: dcn_dcec_opp_fmt0_dispdec // base address: 0x0 #define regFMT0_FMT_CLAMP_COMPONENT_R … #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define regFMT0_FMT_CLAMP_COMPONENT_G … #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define regFMT0_FMT_CLAMP_COMPONENT_B … #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define regFMT0_FMT_DYNAMIC_EXP_CNTL … #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define regFMT0_FMT_CONTROL … #define regFMT0_FMT_CONTROL_BASE_IDX … #define regFMT0_FMT_BIT_DEPTH_CONTROL … #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define regFMT0_FMT_DITHER_RAND_R_SEED … #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define regFMT0_FMT_DITHER_RAND_G_SEED … #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define regFMT0_FMT_DITHER_RAND_B_SEED … #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define regFMT0_FMT_CLAMP_CNTL … #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX … #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define regFMT0_FMT_MAP420_MEMORY_CONTROL … #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define regFMT0_FMT_422_CONTROL … #define regFMT0_FMT_422_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_oppbuf0_dispdec // base address: 0x0 #define regOPPBUF0_OPPBUF_CONTROL … #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX … #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 … #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 … #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX … #define regOPPBUF0_OPPBUF_CONTROL1 … #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe0_dispdec // base address: 0x0 #define regOPP_PIPE0_OPP_PIPE_CONTROL … #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe_crc0_dispdec // base address: 0x0 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 … #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dcn_dcec_opp_dpg1_dispdec // base address: 0x168 #define regDPG1_DPG_CONTROL … #define regDPG1_DPG_CONTROL_BASE_IDX … #define regDPG1_DPG_RAMP_CONTROL … #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX … #define regDPG1_DPG_DIMENSIONS … #define regDPG1_DPG_DIMENSIONS_BASE_IDX … #define regDPG1_DPG_COLOUR_R_CR … #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX … #define regDPG1_DPG_COLOUR_G_Y … #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX … #define regDPG1_DPG_COLOUR_B_CB … #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX … #define regDPG1_DPG_OFFSET_SEGMENT … #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX … #define regDPG1_DPG_STATUS … #define regDPG1_DPG_STATUS_BASE_IDX … // addressBlock: dcn_dcec_opp_fmt1_dispdec // base address: 0x168 #define regFMT1_FMT_CLAMP_COMPONENT_R … #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define regFMT1_FMT_CLAMP_COMPONENT_G … #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define regFMT1_FMT_CLAMP_COMPONENT_B … #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define regFMT1_FMT_DYNAMIC_EXP_CNTL … #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define regFMT1_FMT_CONTROL … #define regFMT1_FMT_CONTROL_BASE_IDX … #define regFMT1_FMT_BIT_DEPTH_CONTROL … #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define regFMT1_FMT_DITHER_RAND_R_SEED … #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define regFMT1_FMT_DITHER_RAND_G_SEED … #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define regFMT1_FMT_DITHER_RAND_B_SEED … #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define regFMT1_FMT_CLAMP_CNTL … #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX … #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define regFMT1_FMT_MAP420_MEMORY_CONTROL … #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define regFMT1_FMT_422_CONTROL … #define regFMT1_FMT_422_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_oppbuf1_dispdec // base address: 0x168 #define regOPPBUF1_OPPBUF_CONTROL … #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX … #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 … #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 … #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX … #define regOPPBUF1_OPPBUF_CONTROL1 … #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe1_dispdec // base address: 0x168 #define regOPP_PIPE1_OPP_PIPE_CONTROL … #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe_crc1_dispdec // base address: 0x168 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 … #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dcn_dcec_opp_dpg2_dispdec // base address: 0x2d0 #define regDPG2_DPG_CONTROL … #define regDPG2_DPG_CONTROL_BASE_IDX … #define regDPG2_DPG_RAMP_CONTROL … #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX … #define regDPG2_DPG_DIMENSIONS … #define regDPG2_DPG_DIMENSIONS_BASE_IDX … #define regDPG2_DPG_COLOUR_R_CR … #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX … #define regDPG2_DPG_COLOUR_G_Y … #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX … #define regDPG2_DPG_COLOUR_B_CB … #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX … #define regDPG2_DPG_OFFSET_SEGMENT … #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX … #define regDPG2_DPG_STATUS … #define regDPG2_DPG_STATUS_BASE_IDX … // addressBlock: dcn_dcec_opp_fmt2_dispdec // base address: 0x2d0 #define regFMT2_FMT_CLAMP_COMPONENT_R … #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define regFMT2_FMT_CLAMP_COMPONENT_G … #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define regFMT2_FMT_CLAMP_COMPONENT_B … #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define regFMT2_FMT_DYNAMIC_EXP_CNTL … #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define regFMT2_FMT_CONTROL … #define regFMT2_FMT_CONTROL_BASE_IDX … #define regFMT2_FMT_BIT_DEPTH_CONTROL … #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define regFMT2_FMT_DITHER_RAND_R_SEED … #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define regFMT2_FMT_DITHER_RAND_G_SEED … #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define regFMT2_FMT_DITHER_RAND_B_SEED … #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define regFMT2_FMT_CLAMP_CNTL … #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX … #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define regFMT2_FMT_MAP420_MEMORY_CONTROL … #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define regFMT2_FMT_422_CONTROL … #define regFMT2_FMT_422_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_oppbuf2_dispdec // base address: 0x2d0 #define regOPPBUF2_OPPBUF_CONTROL … #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX … #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 … #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 … #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX … #define regOPPBUF2_OPPBUF_CONTROL1 … #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe2_dispdec // base address: 0x2d0 #define regOPP_PIPE2_OPP_PIPE_CONTROL … #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe_crc2_dispdec // base address: 0x2d0 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 … #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dcn_dcec_opp_dpg3_dispdec // base address: 0x438 #define regDPG3_DPG_CONTROL … #define regDPG3_DPG_CONTROL_BASE_IDX … #define regDPG3_DPG_RAMP_CONTROL … #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX … #define regDPG3_DPG_DIMENSIONS … #define regDPG3_DPG_DIMENSIONS_BASE_IDX … #define regDPG3_DPG_COLOUR_R_CR … #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX … #define regDPG3_DPG_COLOUR_G_Y … #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX … #define regDPG3_DPG_COLOUR_B_CB … #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX … #define regDPG3_DPG_OFFSET_SEGMENT … #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX … #define regDPG3_DPG_STATUS … #define regDPG3_DPG_STATUS_BASE_IDX … // addressBlock: dcn_dcec_opp_fmt3_dispdec // base address: 0x438 #define regFMT3_FMT_CLAMP_COMPONENT_R … #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define regFMT3_FMT_CLAMP_COMPONENT_G … #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define regFMT3_FMT_CLAMP_COMPONENT_B … #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define regFMT3_FMT_DYNAMIC_EXP_CNTL … #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define regFMT3_FMT_CONTROL … #define regFMT3_FMT_CONTROL_BASE_IDX … #define regFMT3_FMT_BIT_DEPTH_CONTROL … #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define regFMT3_FMT_DITHER_RAND_R_SEED … #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define regFMT3_FMT_DITHER_RAND_G_SEED … #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define regFMT3_FMT_DITHER_RAND_B_SEED … #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define regFMT3_FMT_CLAMP_CNTL … #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX … #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define regFMT3_FMT_MAP420_MEMORY_CONTROL … #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define regFMT3_FMT_422_CONTROL … #define regFMT3_FMT_422_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_oppbuf3_dispdec // base address: 0x438 #define regOPPBUF3_OPPBUF_CONTROL … #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX … #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 … #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 … #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX … #define regOPPBUF3_OPPBUF_CONTROL1 … #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe3_dispdec // base address: 0x438 #define regOPP_PIPE3_OPP_PIPE_CONTROL … #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_pipe_crc3_dispdec // base address: 0x438 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 … #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dcn_dcec_opp_dscrm0_dispdec // base address: 0x0 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG … #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX … // addressBlock: dcn_dcec_opp_dscrm1_dispdec // base address: 0x4 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG … #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX … // addressBlock: dcn_dcec_opp_dscrm2_dispdec // base address: 0x8 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG … #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX … // addressBlock: dcn_dcec_opp_dscrm3_dispdec // base address: 0xc #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG … #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX … // addressBlock: dcn_dcec_opp_opp_top_dispdec // base address: 0x0 #define regOPP_TOP_CLK_CONTROL … #define regOPP_TOP_CLK_CONTROL_BASE_IDX … #define regOPP_ABM_CONTROL … #define regOPP_ABM_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_optc_odm0_dispdec // base address: 0x0 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL … #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define regODM0_OPTC_DATA_SOURCE_SELECT … #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define regODM0_OPTC_DATA_FORMAT_CONTROL … #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define regODM0_OPTC_BYTES_PER_PIXEL … #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define regODM0_OPTC_WIDTH_CONTROL … #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX … #define regODM0_OPTC_WIDTH_CONTROL2 … #define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX … #define regODM0_OPTC_INPUT_CLOCK_CONTROL … #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define regODM0_OPTC_MEMORY_CONFIG … #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX … #define regODM0_OPTC_INPUT_SPARE_REGISTER … #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_odm1_dispdec // base address: 0x40 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL … #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define regODM1_OPTC_DATA_SOURCE_SELECT … #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define regODM1_OPTC_DATA_FORMAT_CONTROL … #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define regODM1_OPTC_BYTES_PER_PIXEL … #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define regODM1_OPTC_WIDTH_CONTROL … #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX … #define regODM1_OPTC_WIDTH_CONTROL2 … #define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX … #define regODM1_OPTC_INPUT_CLOCK_CONTROL … #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define regODM1_OPTC_MEMORY_CONFIG … #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX … #define regODM1_OPTC_INPUT_SPARE_REGISTER … #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_odm2_dispdec // base address: 0x80 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL … #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define regODM2_OPTC_DATA_SOURCE_SELECT … #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define regODM2_OPTC_DATA_FORMAT_CONTROL … #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define regODM2_OPTC_BYTES_PER_PIXEL … #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define regODM2_OPTC_WIDTH_CONTROL … #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX … #define regODM2_OPTC_WIDTH_CONTROL2 … #define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX … #define regODM2_OPTC_INPUT_CLOCK_CONTROL … #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define regODM2_OPTC_MEMORY_CONFIG … #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX … #define regODM2_OPTC_INPUT_SPARE_REGISTER … #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_odm3_dispdec // base address: 0xc0 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL … #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define regODM3_OPTC_DATA_SOURCE_SELECT … #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define regODM3_OPTC_DATA_FORMAT_CONTROL … #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define regODM3_OPTC_BYTES_PER_PIXEL … #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define regODM3_OPTC_WIDTH_CONTROL … #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX … #define regODM3_OPTC_WIDTH_CONTROL2 … #define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX … #define regODM3_OPTC_INPUT_CLOCK_CONTROL … #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define regODM3_OPTC_MEMORY_CONFIG … #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX … #define regODM3_OPTC_INPUT_SPARE_REGISTER … #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_otg0_dispdec // base address: 0x0 #define regOTG0_OTG_H_TOTAL … #define regOTG0_OTG_H_TOTAL_BASE_IDX … #define regOTG0_OTG_H_BLANK_START_END … #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX … #define regOTG0_OTG_H_SYNC_A … #define regOTG0_OTG_H_SYNC_A_BASE_IDX … #define regOTG0_OTG_H_SYNC_A_CNTL … #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX … #define regOTG0_OTG_H_TIMING_CNTL … #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX … #define regOTG0_OTG_V_TOTAL … #define regOTG0_OTG_V_TOTAL_BASE_IDX … #define regOTG0_OTG_V_TOTAL_MIN … #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX … #define regOTG0_OTG_V_TOTAL_MAX … #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX … #define regOTG0_OTG_V_TOTAL_MID … #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … #define regOTG0_OTG_V_TOTAL_CONTROL … #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX … #define regOTG0_OTG_V_COUNT_STOP_CONTROL … #define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX … #define regOTG0_OTG_V_COUNT_STOP_CONTROL2 … #define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX … #define regOTG0_OTG_V_TOTAL_INT_STATUS … #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define regOTG0_OTG_VSYNC_NOM_INT_STATUS … #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define regOTG0_OTG_V_BLANK_START_END … #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX … #define regOTG0_OTG_V_SYNC_A … #define regOTG0_OTG_V_SYNC_A_BASE_IDX … #define regOTG0_OTG_V_SYNC_A_CNTL … #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX … #define regOTG0_OTG_TRIGA_CNTL … #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX … #define regOTG0_OTG_TRIGA_MANUAL_TRIG … #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define regOTG0_OTG_TRIGB_CNTL … #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX … #define regOTG0_OTG_TRIGB_MANUAL_TRIG … #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL … #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define regOTG0_OTG_FLOW_CONTROL … #define regOTG0_OTG_FLOW_CONTROL_BASE_IDX … #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE … #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define regOTG0_OTG_CONTROL … #define regOTG0_OTG_CONTROL_BASE_IDX … #define regOTG0_OTG_DLPC_CONTROL … #define regOTG0_OTG_DLPC_CONTROL_BASE_IDX … #define regOTG0_OTG_INTERLACE_CONTROL … #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX … #define regOTG0_OTG_INTERLACE_STATUS … #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX … #define regOTG0_OTG_PIXEL_DATA_READBACK0 … #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define regOTG0_OTG_PIXEL_DATA_READBACK1 … #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define regOTG0_OTG_STATUS … #define regOTG0_OTG_STATUS_BASE_IDX … #define regOTG0_OTG_STATUS_POSITION … #define regOTG0_OTG_STATUS_POSITION_BASE_IDX … #define regOTG0_OTG_LONG_VBLANK_STATUS … #define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX … #define regOTG0_OTG_NOM_VERT_POSITION … #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX … #define regOTG0_OTG_STATUS_FRAME_COUNT … #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define regOTG0_OTG_STATUS_VF_COUNT … #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX … #define regOTG0_OTG_STATUS_HV_COUNT … #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … #define regOTG0_OTG_COUNT_CONTROL … #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX … #define regOTG0_OTG_COUNT_RESET … #define regOTG0_OTG_COUNT_RESET_BASE_IDX … #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define regOTG0_OTG_VERT_SYNC_CONTROL … #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define regOTG0_OTG_STEREO_STATUS … #define regOTG0_OTG_STEREO_STATUS_BASE_IDX … #define regOTG0_OTG_STEREO_CONTROL … #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX … #define regOTG0_OTG_SNAPSHOT_STATUS … #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX … #define regOTG0_OTG_SNAPSHOT_CONTROL … #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define regOTG0_OTG_SNAPSHOT_POSITION … #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX … #define regOTG0_OTG_SNAPSHOT_FRAME … #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX … #define regOTG0_OTG_INTERRUPT_CONTROL … #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … #define regOTG0_OTG_UPDATE_LOCK … #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX … #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL … #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regOTG0_OTG_MASTER_EN … #define regOTG0_OTG_MASTER_EN_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION … #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL … #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION … #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL … #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION … #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL … #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC_CNTL … #define regOTG0_OTG_CRC_CNTL_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL … #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL … #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL … #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL … #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC0_DATA_RG … #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX … #define regOTG0_OTG_CRC0_DATA_B … #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL … #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL … #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL … #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL … #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG0_OTG_CRC1_DATA_RG … #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX … #define regOTG0_OTG_CRC1_DATA_B … #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX … #define regOTG0_OTG_CRC2_DATA_RG … #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX … #define regOTG0_OTG_CRC2_DATA_B … #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX … #define regOTG0_OTG_CRC3_DATA_RG … #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX … #define regOTG0_OTG_CRC3_DATA_B … #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX … #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK … #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK … #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK … #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK … #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK … #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK … #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK … #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK … #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK … #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG0_OTG_STATIC_SCREEN_CONTROL … #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define regOTG0_OTG_3D_STRUCTURE_CONTROL … #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define regOTG0_OTG_GSL_VSYNC_GAP … #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX … #define regOTG0_OTG_MASTER_UPDATE_MODE … #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define regOTG0_OTG_CLOCK_CONTROL … #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX … #define regOTG0_OTG_VSTARTUP_PARAM … #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX … #define regOTG0_OTG_VUPDATE_PARAM … #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX … #define regOTG0_OTG_VREADY_PARAM … #define regOTG0_OTG_VREADY_PARAM_BASE_IDX … #define regOTG0_OTG_GLOBAL_SYNC_STATUS … #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define regOTG0_OTG_MASTER_UPDATE_LOCK … #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define regOTG0_OTG_GSL_CONTROL … #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … #define regOTG0_OTG_GSL_WINDOW_X … #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX … #define regOTG0_OTG_GSL_WINDOW_Y … #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX … #define regOTG0_OTG_VUPDATE_KEEPOUT … #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define regOTG0_OTG_GLOBAL_CONTROL0 … #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX … #define regOTG0_OTG_GLOBAL_CONTROL1 … #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX … #define regOTG0_OTG_GLOBAL_CONTROL2 … #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX … #define regOTG0_OTG_GLOBAL_CONTROL3 … #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX … #define regOTG0_OTG_GLOBAL_CONTROL4 … #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX … #define regOTG0_OTG_TRIG_MANUAL_CONTROL … #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define regOTG0_OTG_MANUAL_FLOW_CONTROL … #define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define regOTG0_OTG_DRR_TIMING_INT_STATUS … #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX … #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE … #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX … #define regOTG0_OTG_DRR_V_TOTAL_CHANGE … #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX … #define regOTG0_OTG_DRR_TRIGGER_WINDOW … #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX … #define regOTG0_OTG_DRR_CONTROL … #define regOTG0_OTG_DRR_CONTROL_BASE_IDX … #define regOTG0_OTG_DRR_CONTOL2 … #define regOTG0_OTG_DRR_CONTOL2_BASE_IDX … #define regOTG0_OTG_M_CONST_DTO0 … #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX … #define regOTG0_OTG_M_CONST_DTO1 … #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX … #define regOTG0_OTG_REQUEST_CONTROL … #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX … #define regOTG0_OTG_PIPE_UPDATE_STATUS … #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX … #define regOTG0_OTG_PSTATE_REGISTER … #define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX … #define regOTG0_OTG_SPARE_REGISTER … #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_otg1_dispdec // base address: 0x200 #define regOTG1_OTG_H_TOTAL … #define regOTG1_OTG_H_TOTAL_BASE_IDX … #define regOTG1_OTG_H_BLANK_START_END … #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX … #define regOTG1_OTG_H_SYNC_A … #define regOTG1_OTG_H_SYNC_A_BASE_IDX … #define regOTG1_OTG_H_SYNC_A_CNTL … #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX … #define regOTG1_OTG_H_TIMING_CNTL … #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX … #define regOTG1_OTG_V_TOTAL … #define regOTG1_OTG_V_TOTAL_BASE_IDX … #define regOTG1_OTG_V_TOTAL_MIN … #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX … #define regOTG1_OTG_V_TOTAL_MAX … #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX … #define regOTG1_OTG_V_TOTAL_MID … #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … #define regOTG1_OTG_V_TOTAL_CONTROL … #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX … #define regOTG1_OTG_V_COUNT_STOP_CONTROL … #define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX … #define regOTG1_OTG_V_COUNT_STOP_CONTROL2 … #define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX … #define regOTG1_OTG_V_TOTAL_INT_STATUS … #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define regOTG1_OTG_VSYNC_NOM_INT_STATUS … #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define regOTG1_OTG_V_BLANK_START_END … #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX … #define regOTG1_OTG_V_SYNC_A … #define regOTG1_OTG_V_SYNC_A_BASE_IDX … #define regOTG1_OTG_V_SYNC_A_CNTL … #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX … #define regOTG1_OTG_TRIGA_CNTL … #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX … #define regOTG1_OTG_TRIGA_MANUAL_TRIG … #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define regOTG1_OTG_TRIGB_CNTL … #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX … #define regOTG1_OTG_TRIGB_MANUAL_TRIG … #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL … #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define regOTG1_OTG_FLOW_CONTROL … #define regOTG1_OTG_FLOW_CONTROL_BASE_IDX … #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE … #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define regOTG1_OTG_CONTROL … #define regOTG1_OTG_CONTROL_BASE_IDX … #define regOTG1_OTG_DLPC_CONTROL … #define regOTG1_OTG_DLPC_CONTROL_BASE_IDX … #define regOTG1_OTG_INTERLACE_CONTROL … #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX … #define regOTG1_OTG_INTERLACE_STATUS … #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX … #define regOTG1_OTG_PIXEL_DATA_READBACK0 … #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define regOTG1_OTG_PIXEL_DATA_READBACK1 … #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define regOTG1_OTG_STATUS … #define regOTG1_OTG_STATUS_BASE_IDX … #define regOTG1_OTG_STATUS_POSITION … #define regOTG1_OTG_STATUS_POSITION_BASE_IDX … #define regOTG1_OTG_LONG_VBLANK_STATUS … #define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX … #define regOTG1_OTG_NOM_VERT_POSITION … #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX … #define regOTG1_OTG_STATUS_FRAME_COUNT … #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define regOTG1_OTG_STATUS_VF_COUNT … #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX … #define regOTG1_OTG_STATUS_HV_COUNT … #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX … #define regOTG1_OTG_COUNT_CONTROL … #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX … #define regOTG1_OTG_COUNT_RESET … #define regOTG1_OTG_COUNT_RESET_BASE_IDX … #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define regOTG1_OTG_VERT_SYNC_CONTROL … #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define regOTG1_OTG_STEREO_STATUS … #define regOTG1_OTG_STEREO_STATUS_BASE_IDX … #define regOTG1_OTG_STEREO_CONTROL … #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX … #define regOTG1_OTG_SNAPSHOT_STATUS … #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX … #define regOTG1_OTG_SNAPSHOT_CONTROL … #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define regOTG1_OTG_SNAPSHOT_POSITION … #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX … #define regOTG1_OTG_SNAPSHOT_FRAME … #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX … #define regOTG1_OTG_INTERRUPT_CONTROL … #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX … #define regOTG1_OTG_UPDATE_LOCK … #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX … #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL … #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regOTG1_OTG_MASTER_EN … #define regOTG1_OTG_MASTER_EN_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION … #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL … #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION … #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL … #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION … #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL … #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC_CNTL … #define regOTG1_OTG_CRC_CNTL_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL … #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL … #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL … #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL … #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC0_DATA_RG … #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX … #define regOTG1_OTG_CRC0_DATA_B … #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL … #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL … #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL … #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL … #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG1_OTG_CRC1_DATA_RG … #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX … #define regOTG1_OTG_CRC1_DATA_B … #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX … #define regOTG1_OTG_CRC2_DATA_RG … #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX … #define regOTG1_OTG_CRC2_DATA_B … #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX … #define regOTG1_OTG_CRC3_DATA_RG … #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX … #define regOTG1_OTG_CRC3_DATA_B … #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX … #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK … #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK … #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK … #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK … #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK … #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK … #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK … #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK … #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK … #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG1_OTG_STATIC_SCREEN_CONTROL … #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define regOTG1_OTG_3D_STRUCTURE_CONTROL … #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define regOTG1_OTG_GSL_VSYNC_GAP … #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX … #define regOTG1_OTG_MASTER_UPDATE_MODE … #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define regOTG1_OTG_CLOCK_CONTROL … #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX … #define regOTG1_OTG_VSTARTUP_PARAM … #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX … #define regOTG1_OTG_VUPDATE_PARAM … #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX … #define regOTG1_OTG_VREADY_PARAM … #define regOTG1_OTG_VREADY_PARAM_BASE_IDX … #define regOTG1_OTG_GLOBAL_SYNC_STATUS … #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define regOTG1_OTG_MASTER_UPDATE_LOCK … #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define regOTG1_OTG_GSL_CONTROL … #define regOTG1_OTG_GSL_CONTROL_BASE_IDX … #define regOTG1_OTG_GSL_WINDOW_X … #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX … #define regOTG1_OTG_GSL_WINDOW_Y … #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX … #define regOTG1_OTG_VUPDATE_KEEPOUT … #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define regOTG1_OTG_GLOBAL_CONTROL0 … #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX … #define regOTG1_OTG_GLOBAL_CONTROL1 … #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX … #define regOTG1_OTG_GLOBAL_CONTROL2 … #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX … #define regOTG1_OTG_GLOBAL_CONTROL3 … #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX … #define regOTG1_OTG_GLOBAL_CONTROL4 … #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX … #define regOTG1_OTG_TRIG_MANUAL_CONTROL … #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define regOTG1_OTG_MANUAL_FLOW_CONTROL … #define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define regOTG1_OTG_DRR_TIMING_INT_STATUS … #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX … #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE … #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX … #define regOTG1_OTG_DRR_V_TOTAL_CHANGE … #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX … #define regOTG1_OTG_DRR_TRIGGER_WINDOW … #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX … #define regOTG1_OTG_DRR_CONTROL … #define regOTG1_OTG_DRR_CONTROL_BASE_IDX … #define regOTG1_OTG_DRR_CONTOL2 … #define regOTG1_OTG_DRR_CONTOL2_BASE_IDX … #define regOTG1_OTG_M_CONST_DTO0 … #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX … #define regOTG1_OTG_M_CONST_DTO1 … #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX … #define regOTG1_OTG_REQUEST_CONTROL … #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX … #define regOTG1_OTG_PIPE_UPDATE_STATUS … #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX … #define regOTG1_OTG_PSTATE_REGISTER … #define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX … #define regOTG1_OTG_SPARE_REGISTER … #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_otg2_dispdec // base address: 0x400 #define regOTG2_OTG_H_TOTAL … #define regOTG2_OTG_H_TOTAL_BASE_IDX … #define regOTG2_OTG_H_BLANK_START_END … #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX … #define regOTG2_OTG_H_SYNC_A … #define regOTG2_OTG_H_SYNC_A_BASE_IDX … #define regOTG2_OTG_H_SYNC_A_CNTL … #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX … #define regOTG2_OTG_H_TIMING_CNTL … #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX … #define regOTG2_OTG_V_TOTAL … #define regOTG2_OTG_V_TOTAL_BASE_IDX … #define regOTG2_OTG_V_TOTAL_MIN … #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX … #define regOTG2_OTG_V_TOTAL_MAX … #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX … #define regOTG2_OTG_V_TOTAL_MID … #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX … #define regOTG2_OTG_V_TOTAL_CONTROL … #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX … #define regOTG2_OTG_V_COUNT_STOP_CONTROL … #define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX … #define regOTG2_OTG_V_COUNT_STOP_CONTROL2 … #define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX … #define regOTG2_OTG_V_TOTAL_INT_STATUS … #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define regOTG2_OTG_VSYNC_NOM_INT_STATUS … #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define regOTG2_OTG_V_BLANK_START_END … #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX … #define regOTG2_OTG_V_SYNC_A … #define regOTG2_OTG_V_SYNC_A_BASE_IDX … #define regOTG2_OTG_V_SYNC_A_CNTL … #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX … #define regOTG2_OTG_TRIGA_CNTL … #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX … #define regOTG2_OTG_TRIGA_MANUAL_TRIG … #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define regOTG2_OTG_TRIGB_CNTL … #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX … #define regOTG2_OTG_TRIGB_MANUAL_TRIG … #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL … #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define regOTG2_OTG_FLOW_CONTROL … #define regOTG2_OTG_FLOW_CONTROL_BASE_IDX … #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE … #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define regOTG2_OTG_CONTROL … #define regOTG2_OTG_CONTROL_BASE_IDX … #define regOTG2_OTG_DLPC_CONTROL … #define regOTG2_OTG_DLPC_CONTROL_BASE_IDX … #define regOTG2_OTG_INTERLACE_CONTROL … #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX … #define regOTG2_OTG_INTERLACE_STATUS … #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX … #define regOTG2_OTG_PIXEL_DATA_READBACK0 … #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define regOTG2_OTG_PIXEL_DATA_READBACK1 … #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define regOTG2_OTG_STATUS … #define regOTG2_OTG_STATUS_BASE_IDX … #define regOTG2_OTG_STATUS_POSITION … #define regOTG2_OTG_STATUS_POSITION_BASE_IDX … #define regOTG2_OTG_LONG_VBLANK_STATUS … #define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX … #define regOTG2_OTG_NOM_VERT_POSITION … #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX … #define regOTG2_OTG_STATUS_FRAME_COUNT … #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define regOTG2_OTG_STATUS_VF_COUNT … #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX … #define regOTG2_OTG_STATUS_HV_COUNT … #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX … #define regOTG2_OTG_COUNT_CONTROL … #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX … #define regOTG2_OTG_COUNT_RESET … #define regOTG2_OTG_COUNT_RESET_BASE_IDX … #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define regOTG2_OTG_VERT_SYNC_CONTROL … #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define regOTG2_OTG_STEREO_STATUS … #define regOTG2_OTG_STEREO_STATUS_BASE_IDX … #define regOTG2_OTG_STEREO_CONTROL … #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX … #define regOTG2_OTG_SNAPSHOT_STATUS … #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX … #define regOTG2_OTG_SNAPSHOT_CONTROL … #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define regOTG2_OTG_SNAPSHOT_POSITION … #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX … #define regOTG2_OTG_SNAPSHOT_FRAME … #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX … #define regOTG2_OTG_INTERRUPT_CONTROL … #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX … #define regOTG2_OTG_UPDATE_LOCK … #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX … #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL … #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regOTG2_OTG_MASTER_EN … #define regOTG2_OTG_MASTER_EN_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION … #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL … #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION … #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL … #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION … #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL … #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC_CNTL … #define regOTG2_OTG_CRC_CNTL_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL … #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL … #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL … #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL … #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC0_DATA_RG … #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX … #define regOTG2_OTG_CRC0_DATA_B … #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL … #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL … #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL … #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL … #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG2_OTG_CRC1_DATA_RG … #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX … #define regOTG2_OTG_CRC1_DATA_B … #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX … #define regOTG2_OTG_CRC2_DATA_RG … #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX … #define regOTG2_OTG_CRC2_DATA_B … #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX … #define regOTG2_OTG_CRC3_DATA_RG … #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX … #define regOTG2_OTG_CRC3_DATA_B … #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX … #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK … #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK … #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK … #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK … #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK … #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK … #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK … #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK … #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK … #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG2_OTG_STATIC_SCREEN_CONTROL … #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define regOTG2_OTG_3D_STRUCTURE_CONTROL … #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define regOTG2_OTG_GSL_VSYNC_GAP … #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX … #define regOTG2_OTG_MASTER_UPDATE_MODE … #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define regOTG2_OTG_CLOCK_CONTROL … #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX … #define regOTG2_OTG_VSTARTUP_PARAM … #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX … #define regOTG2_OTG_VUPDATE_PARAM … #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX … #define regOTG2_OTG_VREADY_PARAM … #define regOTG2_OTG_VREADY_PARAM_BASE_IDX … #define regOTG2_OTG_GLOBAL_SYNC_STATUS … #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define regOTG2_OTG_MASTER_UPDATE_LOCK … #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define regOTG2_OTG_GSL_CONTROL … #define regOTG2_OTG_GSL_CONTROL_BASE_IDX … #define regOTG2_OTG_GSL_WINDOW_X … #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX … #define regOTG2_OTG_GSL_WINDOW_Y … #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX … #define regOTG2_OTG_VUPDATE_KEEPOUT … #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define regOTG2_OTG_GLOBAL_CONTROL0 … #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX … #define regOTG2_OTG_GLOBAL_CONTROL1 … #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX … #define regOTG2_OTG_GLOBAL_CONTROL2 … #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX … #define regOTG2_OTG_GLOBAL_CONTROL3 … #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX … #define regOTG2_OTG_GLOBAL_CONTROL4 … #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX … #define regOTG2_OTG_TRIG_MANUAL_CONTROL … #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define regOTG2_OTG_MANUAL_FLOW_CONTROL … #define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define regOTG2_OTG_DRR_TIMING_INT_STATUS … #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX … #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE … #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX … #define regOTG2_OTG_DRR_V_TOTAL_CHANGE … #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX … #define regOTG2_OTG_DRR_TRIGGER_WINDOW … #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX … #define regOTG2_OTG_DRR_CONTROL … #define regOTG2_OTG_DRR_CONTROL_BASE_IDX … #define regOTG2_OTG_DRR_CONTOL2 … #define regOTG2_OTG_DRR_CONTOL2_BASE_IDX … #define regOTG2_OTG_M_CONST_DTO0 … #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX … #define regOTG2_OTG_M_CONST_DTO1 … #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX … #define regOTG2_OTG_REQUEST_CONTROL … #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX … #define regOTG2_OTG_PIPE_UPDATE_STATUS … #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX … #define regOTG2_OTG_PSTATE_REGISTER … #define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX … #define regOTG2_OTG_SPARE_REGISTER … #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_otg3_dispdec // base address: 0x600 #define regOTG3_OTG_H_TOTAL … #define regOTG3_OTG_H_TOTAL_BASE_IDX … #define regOTG3_OTG_H_BLANK_START_END … #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX … #define regOTG3_OTG_H_SYNC_A … #define regOTG3_OTG_H_SYNC_A_BASE_IDX … #define regOTG3_OTG_H_SYNC_A_CNTL … #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX … #define regOTG3_OTG_H_TIMING_CNTL … #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX … #define regOTG3_OTG_V_TOTAL … #define regOTG3_OTG_V_TOTAL_BASE_IDX … #define regOTG3_OTG_V_TOTAL_MIN … #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX … #define regOTG3_OTG_V_TOTAL_MAX … #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX … #define regOTG3_OTG_V_TOTAL_MID … #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX … #define regOTG3_OTG_V_TOTAL_CONTROL … #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX … #define regOTG3_OTG_V_COUNT_STOP_CONTROL … #define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX … #define regOTG3_OTG_V_COUNT_STOP_CONTROL2 … #define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX … #define regOTG3_OTG_V_TOTAL_INT_STATUS … #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define regOTG3_OTG_VSYNC_NOM_INT_STATUS … #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define regOTG3_OTG_V_BLANK_START_END … #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX … #define regOTG3_OTG_V_SYNC_A … #define regOTG3_OTG_V_SYNC_A_BASE_IDX … #define regOTG3_OTG_V_SYNC_A_CNTL … #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX … #define regOTG3_OTG_TRIGA_CNTL … #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX … #define regOTG3_OTG_TRIGA_MANUAL_TRIG … #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define regOTG3_OTG_TRIGB_CNTL … #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX … #define regOTG3_OTG_TRIGB_MANUAL_TRIG … #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL … #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define regOTG3_OTG_FLOW_CONTROL … #define regOTG3_OTG_FLOW_CONTROL_BASE_IDX … #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE … #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define regOTG3_OTG_CONTROL … #define regOTG3_OTG_CONTROL_BASE_IDX … #define regOTG3_OTG_DLPC_CONTROL … #define regOTG3_OTG_DLPC_CONTROL_BASE_IDX … #define regOTG3_OTG_INTERLACE_CONTROL … #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX … #define regOTG3_OTG_INTERLACE_STATUS … #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX … #define regOTG3_OTG_PIXEL_DATA_READBACK0 … #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define regOTG3_OTG_PIXEL_DATA_READBACK1 … #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define regOTG3_OTG_STATUS … #define regOTG3_OTG_STATUS_BASE_IDX … #define regOTG3_OTG_STATUS_POSITION … #define regOTG3_OTG_STATUS_POSITION_BASE_IDX … #define regOTG3_OTG_LONG_VBLANK_STATUS … #define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX … #define regOTG3_OTG_NOM_VERT_POSITION … #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX … #define regOTG3_OTG_STATUS_FRAME_COUNT … #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define regOTG3_OTG_STATUS_VF_COUNT … #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX … #define regOTG3_OTG_STATUS_HV_COUNT … #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX … #define regOTG3_OTG_COUNT_CONTROL … #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX … #define regOTG3_OTG_COUNT_RESET … #define regOTG3_OTG_COUNT_RESET_BASE_IDX … #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define regOTG3_OTG_VERT_SYNC_CONTROL … #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define regOTG3_OTG_STEREO_STATUS … #define regOTG3_OTG_STEREO_STATUS_BASE_IDX … #define regOTG3_OTG_STEREO_CONTROL … #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX … #define regOTG3_OTG_SNAPSHOT_STATUS … #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX … #define regOTG3_OTG_SNAPSHOT_CONTROL … #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define regOTG3_OTG_SNAPSHOT_POSITION … #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX … #define regOTG3_OTG_SNAPSHOT_FRAME … #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX … #define regOTG3_OTG_INTERRUPT_CONTROL … #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX … #define regOTG3_OTG_UPDATE_LOCK … #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX … #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL … #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regOTG3_OTG_MASTER_EN … #define regOTG3_OTG_MASTER_EN_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION … #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL … #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION … #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL … #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION … #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL … #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC_CNTL … #define regOTG3_OTG_CRC_CNTL_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL … #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL … #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL … #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL … #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC0_DATA_RG … #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX … #define regOTG3_OTG_CRC0_DATA_B … #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL … #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL … #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL … #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL … #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define regOTG3_OTG_CRC1_DATA_RG … #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX … #define regOTG3_OTG_CRC1_DATA_B … #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX … #define regOTG3_OTG_CRC2_DATA_RG … #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX … #define regOTG3_OTG_CRC2_DATA_B … #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX … #define regOTG3_OTG_CRC3_DATA_RG … #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX … #define regOTG3_OTG_CRC3_DATA_B … #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX … #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK … #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK … #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK … #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK … #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK … #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK … #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK … #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK … #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK … #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX … #define regOTG3_OTG_STATIC_SCREEN_CONTROL … #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define regOTG3_OTG_3D_STRUCTURE_CONTROL … #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define regOTG3_OTG_GSL_VSYNC_GAP … #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX … #define regOTG3_OTG_MASTER_UPDATE_MODE … #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define regOTG3_OTG_CLOCK_CONTROL … #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX … #define regOTG3_OTG_VSTARTUP_PARAM … #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX … #define regOTG3_OTG_VUPDATE_PARAM … #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX … #define regOTG3_OTG_VREADY_PARAM … #define regOTG3_OTG_VREADY_PARAM_BASE_IDX … #define regOTG3_OTG_GLOBAL_SYNC_STATUS … #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define regOTG3_OTG_MASTER_UPDATE_LOCK … #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define regOTG3_OTG_GSL_CONTROL … #define regOTG3_OTG_GSL_CONTROL_BASE_IDX … #define regOTG3_OTG_GSL_WINDOW_X … #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX … #define regOTG3_OTG_GSL_WINDOW_Y … #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX … #define regOTG3_OTG_VUPDATE_KEEPOUT … #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define regOTG3_OTG_GLOBAL_CONTROL0 … #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX … #define regOTG3_OTG_GLOBAL_CONTROL1 … #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX … #define regOTG3_OTG_GLOBAL_CONTROL2 … #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX … #define regOTG3_OTG_GLOBAL_CONTROL3 … #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX … #define regOTG3_OTG_GLOBAL_CONTROL4 … #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX … #define regOTG3_OTG_TRIG_MANUAL_CONTROL … #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define regOTG3_OTG_MANUAL_FLOW_CONTROL … #define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define regOTG3_OTG_DRR_TIMING_INT_STATUS … #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX … #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE … #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX … #define regOTG3_OTG_DRR_V_TOTAL_CHANGE … #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX … #define regOTG3_OTG_DRR_TRIGGER_WINDOW … #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX … #define regOTG3_OTG_DRR_CONTROL … #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … #define regOTG3_OTG_DRR_CONTOL2 … #define regOTG3_OTG_DRR_CONTOL2_BASE_IDX … #define regOTG3_OTG_M_CONST_DTO0 … #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX … #define regOTG3_OTG_M_CONST_DTO1 … #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX … #define regOTG3_OTG_REQUEST_CONTROL … #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX … #define regOTG3_OTG_PIPE_UPDATE_STATUS … #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX … #define regOTG3_OTG_PSTATE_REGISTER … #define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX … #define regOTG3_OTG_SPARE_REGISTER … #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_optc_optc_misc_dispdec // base address: 0x0 #define regGSL_SOURCE_SELECT … #define regGSL_SOURCE_SELECT_BASE_IDX … #define regOPTC_DLPC_CONTROL … #define regOPTC_DLPC_CONTROL_BASE_IDX … #define regOPTC_CLOCK_CONTROL … #define regOPTC_CLOCK_CONTROL_BASE_IDX … #define regODM_MEM_PWR_CTRL … #define regODM_MEM_PWR_CTRL_BASE_IDX … #define regODM_MEM_PWR_CTRL2 … #define regODM_MEM_PWR_CTRL2_BASE_IDX … #define regODM_MEM_PWR_CTRL3 … #define regODM_MEM_PWR_CTRL3_BASE_IDX … #define regODM_MEM_PWR_STATUS … #define regODM_MEM_PWR_STATUS_BASE_IDX … #define regOPTC_MISC_SPARE_REGISTER … #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX … // addressBlock: dcn_dcec_dio_dp0_dispdec // base address: 0x0 #define regDP0_DP_LINK_CNTL … #define regDP0_DP_LINK_CNTL_BASE_IDX … #define regDP0_DP_PIXEL_FORMAT … #define regDP0_DP_PIXEL_FORMAT_BASE_IDX … #define regDP0_DP_MSA_COLORIMETRY … #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX … #define regDP0_DP_CONFIG … #define regDP0_DP_CONFIG_BASE_IDX … #define regDP0_DP_VID_STREAM_CNTL … #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX … #define regDP0_DP_STEER_FIFO … #define regDP0_DP_STEER_FIFO_BASE_IDX … #define regDP0_DP_MSA_MISC … #define regDP0_DP_MSA_MISC_BASE_IDX … #define regDP0_DP_DPHY_INTERNAL_CTRL … #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define regDP0_DP_VID_TIMING … #define regDP0_DP_VID_TIMING_BASE_IDX … #define regDP0_DP_VID_N … #define regDP0_DP_VID_N_BASE_IDX … #define regDP0_DP_VID_M … #define regDP0_DP_VID_M_BASE_IDX … #define regDP0_DP_LINK_FRAMING_CNTL … #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX … #define regDP0_DP_HBR2_EYE_PATTERN … #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX … #define regDP0_DP_VID_MSA_VBID … #define regDP0_DP_VID_MSA_VBID_BASE_IDX … #define regDP0_DP_VID_INTERRUPT_CNTL … #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define regDP0_DP_DPHY_CNTL … #define regDP0_DP_DPHY_CNTL_BASE_IDX … #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL … #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define regDP0_DP_DPHY_SYM0 … #define regDP0_DP_DPHY_SYM0_BASE_IDX … #define regDP0_DP_DPHY_SYM1 … #define regDP0_DP_DPHY_SYM1_BASE_IDX … #define regDP0_DP_DPHY_SYM2 … #define regDP0_DP_DPHY_SYM2_BASE_IDX … #define regDP0_DP_DPHY_8B10B_CNTL … #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX … #define regDP0_DP_DPHY_PRBS_CNTL … #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX … #define regDP0_DP_DPHY_SCRAM_CNTL … #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define regDP0_DP_DPHY_CRC_EN … #define regDP0_DP_DPHY_CRC_EN_BASE_IDX … #define regDP0_DP_DPHY_CRC_CNTL … #define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX … #define regDP0_DP_DPHY_CRC_RESULT … #define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX … #define regDP0_DP_DPHY_CRC_MST_CNTL … #define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define regDP0_DP_DPHY_CRC_MST_STATUS … #define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define regDP0_DP_DPHY_FAST_TRAINING … #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX … #define regDP0_DP_DPHY_FAST_TRAINING_STATUS … #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define regDP0_DP_TU_CNTL … #define regDP0_DP_TU_CNTL_BASE_IDX … #define regDP0_DP_PIXEL_FORMAT_DB_CNTL … #define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX … #define regDP0_DP_CP_LINK_VERIFICATION_PATTERN … #define regDP0_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX … #define regDP0_DP_SEC_CNTL … #define regDP0_DP_SEC_CNTL_BASE_IDX … #define regDP0_DP_SEC_CNTL1 … #define regDP0_DP_SEC_CNTL1_BASE_IDX … #define regDP0_DP_SEC_FRAMING1 … #define regDP0_DP_SEC_FRAMING1_BASE_IDX … #define regDP0_DP_SEC_FRAMING2 … #define regDP0_DP_SEC_FRAMING2_BASE_IDX … #define regDP0_DP_SEC_FRAMING3 … #define regDP0_DP_SEC_FRAMING3_BASE_IDX … #define regDP0_DP_SEC_FRAMING4 … #define regDP0_DP_SEC_FRAMING4_BASE_IDX … #define regDP0_DP_SEC_AUD_N … #define regDP0_DP_SEC_AUD_N_BASE_IDX … #define regDP0_DP_SEC_AUD_N_READBACK … #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX … #define regDP0_DP_SEC_AUD_M … #define regDP0_DP_SEC_AUD_M_BASE_IDX … #define regDP0_DP_SEC_AUD_M_READBACK … #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX … #define regDP0_DP_SEC_TIMESTAMP … #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX … #define regDP0_DP_SEC_PACKET_CNTL … #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX … #define regDP0_DP_MSE_RATE_CNTL … #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX … #define regDP0_DP_CP_MSE_STATUS … #define regDP0_DP_CP_MSE_STATUS_BASE_IDX … #define regDP0_DP_MSE_RATE_UPDATE … #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX … #define regDP0_DP_MSE_SAT0 … #define regDP0_DP_MSE_SAT0_BASE_IDX … #define regDP0_DP_MSE_SAT1 … #define regDP0_DP_MSE_SAT1_BASE_IDX … #define regDP0_DP_MSE_SAT2 … #define regDP0_DP_MSE_SAT2_BASE_IDX … #define regDP0_DP_MSE_SAT_UPDATE … #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX … #define regDP0_DP_MSE_LINK_TIMING … #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX … #define regDP0_DP_MSE_MISC_CNTL … #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX … #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL … #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL … #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define regDP0_DP_MSE_SAT0_STATUS … #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX … #define regDP0_DP_MSE_SAT1_STATUS … #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX … #define regDP0_DP_MSE_SAT2_STATUS … #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX … #define regDP0_DP_DPIA_SPARE … #define regDP0_DP_DPIA_SPARE_BASE_IDX … #define regDP0_DP_HBLANK_CONTROL … #define regDP0_DP_HBLANK_CONTROL_BASE_IDX … #define regDP0_DP_MSA_TIMING_PARAM1 … #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX … #define regDP0_DP_MSA_TIMING_PARAM2 … #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX … #define regDP0_DP_MSA_TIMING_PARAM3 … #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX … #define regDP0_DP_MSA_TIMING_PARAM4 … #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … #define regDP0_DP_MSO_CNTL … #define regDP0_DP_MSO_CNTL_BASE_IDX … #define regDP0_DP_MSO_CNTL1 … #define regDP0_DP_MSO_CNTL1_BASE_IDX … #define regDP0_DP_STEER_FIFO_CNTL … #define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX … #define regDP0_DP_SEC_CNTL2 … #define regDP0_DP_SEC_CNTL2_BASE_IDX … #define regDP0_DP_SEC_CNTL3 … #define regDP0_DP_SEC_CNTL3_BASE_IDX … #define regDP0_DP_SEC_CNTL4 … #define regDP0_DP_SEC_CNTL4_BASE_IDX … #define regDP0_DP_SEC_CNTL5 … #define regDP0_DP_SEC_CNTL5_BASE_IDX … #define regDP0_DP_SEC_CNTL6 … #define regDP0_DP_SEC_CNTL6_BASE_IDX … #define regDP0_DP_SEC_CNTL7 … #define regDP0_DP_SEC_CNTL7_BASE_IDX … #define regDP0_DP_DB_CNTL … #define regDP0_DP_DB_CNTL_BASE_IDX … #define regDP0_DP_MSA_VBID_MISC … #define regDP0_DP_MSA_VBID_MISC_BASE_IDX … #define regDP0_DP_SEC_METADATA_TRANSMISSION … #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define regDP0_DP_ALPM_CNTL … #define regDP0_DP_ALPM_CNTL_BASE_IDX … #define regDP0_DP_GSP8_CNTL … #define regDP0_DP_GSP8_CNTL_BASE_IDX … #define regDP0_DP_GSP9_CNTL … #define regDP0_DP_GSP9_CNTL_BASE_IDX … #define regDP0_DP_GSP10_CNTL … #define regDP0_DP_GSP10_CNTL_BASE_IDX … #define regDP0_DP_GSP11_CNTL … #define regDP0_DP_GSP11_CNTL_BASE_IDX … #define regDP0_DP_GSP_EN_DB_STATUS … #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX … #define regDP0_DP_AUXLESS_ALPM_CNTL1 … #define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX … #define regDP0_DP_AUXLESS_ALPM_CNTL2 … #define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX … #define regDP0_DP_AUXLESS_ALPM_CNTL3 … #define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX … #define regDP0_DP_AUXLESS_ALPM_CNTL4 … #define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX … #define regDP0_DP_AUXLESS_ALPM_CNTL5 … #define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX … #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS … #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL … #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 … #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 … #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL … #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig0_dispdec // base address: 0x0 #define regDIG0_DIG_FE_CNTL … #define regDIG0_DIG_FE_CNTL_BASE_IDX … #define regDIG0_DIG_FE_CLK_CNTL … #define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX … #define regDIG0_DIG_FE_EN_CNTL … #define regDIG0_DIG_FE_EN_CNTL_BASE_IDX … #define regDIG0_DIG_OUTPUT_CRC_CNTL … #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define regDIG0_DIG_OUTPUT_CRC_RESULT … #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define regDIG0_DIG_CLOCK_PATTERN … #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX … #define regDIG0_DIG_TEST_PATTERN … #define regDIG0_DIG_TEST_PATTERN_BASE_IDX … #define regDIG0_DIG_RANDOM_PATTERN_SEED … #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define regDIG0_DIG_FIFO_CTRL0 … #define regDIG0_DIG_FIFO_CTRL0_BASE_IDX … #define regDIG0_DIG_FIFO_CTRL1 … #define regDIG0_DIG_FIFO_CTRL1_BASE_IDX … #define regDIG0_HDMI_METADATA_PACKET_CONTROL … #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define regDIG0_HDMI_CONTROL … #define regDIG0_HDMI_CONTROL_BASE_IDX … #define regDIG0_HDMI_STATUS … #define regDIG0_HDMI_STATUS_BASE_IDX … #define regDIG0_HDMI_AUDIO_PACKET_CONTROL … #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define regDIG0_HDMI_ACR_PACKET_CONTROL … #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define regDIG0_HDMI_VBI_PACKET_CONTROL … #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define regDIG0_HDMI_INFOFRAME_CONTROL0 … #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define regDIG0_HDMI_INFOFRAME_CONTROL1 … #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … #define regDIG0_HDMI_GC … #define regDIG0_HDMI_GC_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 … #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX … #define regDIG0_HDMI_DB_CONTROL … #define regDIG0_HDMI_DB_CONTROL_BASE_IDX … #define regDIG0_HDMI_ACR_32_0 … #define regDIG0_HDMI_ACR_32_0_BASE_IDX … #define regDIG0_HDMI_ACR_32_1 … #define regDIG0_HDMI_ACR_32_1_BASE_IDX … #define regDIG0_HDMI_ACR_44_0 … #define regDIG0_HDMI_ACR_44_0_BASE_IDX … #define regDIG0_HDMI_ACR_44_1 … #define regDIG0_HDMI_ACR_44_1_BASE_IDX … #define regDIG0_HDMI_ACR_48_0 … #define regDIG0_HDMI_ACR_48_0_BASE_IDX … #define regDIG0_HDMI_ACR_48_1 … #define regDIG0_HDMI_ACR_48_1_BASE_IDX … #define regDIG0_HDMI_ACR_STATUS_0 … #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX … #define regDIG0_HDMI_ACR_STATUS_1 … #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX … #define regDIG0_AFMT_CNTL … #define regDIG0_AFMT_CNTL_BASE_IDX … #define regDIG0_DIG_BE_CLK_CNTL … #define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX … #define regDIG0_DIG_BE_CNTL … #define regDIG0_DIG_BE_CNTL_BASE_IDX … #define regDIG0_DIG_BE_EN_CNTL … #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX … #define regDIG0_TMDS_CNTL … #define regDIG0_TMDS_CNTL_BASE_IDX … #define regDIG0_TMDS_CONTROL_CHAR … #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX … #define regDIG0_TMDS_CONTROL0_FEEDBACK … #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define regDIG0_TMDS_STEREOSYNC_CTL_SEL … #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 … #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 … #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define regDIG0_TMDS_CTL_BITS … #define regDIG0_TMDS_CTL_BITS_BASE_IDX … #define regDIG0_TMDS_DCBALANCER_CONTROL … #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR … #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define regDIG0_TMDS_CTL0_1_GEN_CNTL … #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define regDIG0_TMDS_CTL2_3_GEN_CNTL … #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define regDIG0_DIG_VERSION … #define regDIG0_DIG_VERSION_BASE_IDX … // addressBlock: dcn_dcec_dio_dp1_dispdec // base address: 0x490 #define regDP1_DP_LINK_CNTL … #define regDP1_DP_LINK_CNTL_BASE_IDX … #define regDP1_DP_PIXEL_FORMAT … #define regDP1_DP_PIXEL_FORMAT_BASE_IDX … #define regDP1_DP_MSA_COLORIMETRY … #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX … #define regDP1_DP_CONFIG … #define regDP1_DP_CONFIG_BASE_IDX … #define regDP1_DP_VID_STREAM_CNTL … #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX … #define regDP1_DP_STEER_FIFO … #define regDP1_DP_STEER_FIFO_BASE_IDX … #define regDP1_DP_MSA_MISC … #define regDP1_DP_MSA_MISC_BASE_IDX … #define regDP1_DP_DPHY_INTERNAL_CTRL … #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define regDP1_DP_VID_TIMING … #define regDP1_DP_VID_TIMING_BASE_IDX … #define regDP1_DP_VID_N … #define regDP1_DP_VID_N_BASE_IDX … #define regDP1_DP_VID_M … #define regDP1_DP_VID_M_BASE_IDX … #define regDP1_DP_LINK_FRAMING_CNTL … #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX … #define regDP1_DP_HBR2_EYE_PATTERN … #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX … #define regDP1_DP_VID_MSA_VBID … #define regDP1_DP_VID_MSA_VBID_BASE_IDX … #define regDP1_DP_VID_INTERRUPT_CNTL … #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define regDP1_DP_DPHY_CNTL … #define regDP1_DP_DPHY_CNTL_BASE_IDX … #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL … #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define regDP1_DP_DPHY_SYM0 … #define regDP1_DP_DPHY_SYM0_BASE_IDX … #define regDP1_DP_DPHY_SYM1 … #define regDP1_DP_DPHY_SYM1_BASE_IDX … #define regDP1_DP_DPHY_SYM2 … #define regDP1_DP_DPHY_SYM2_BASE_IDX … #define regDP1_DP_DPHY_8B10B_CNTL … #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX … #define regDP1_DP_DPHY_PRBS_CNTL … #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX … #define regDP1_DP_DPHY_SCRAM_CNTL … #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define regDP1_DP_DPHY_CRC_EN … #define regDP1_DP_DPHY_CRC_EN_BASE_IDX … #define regDP1_DP_DPHY_CRC_CNTL … #define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX … #define regDP1_DP_DPHY_CRC_RESULT … #define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX … #define regDP1_DP_DPHY_CRC_MST_CNTL … #define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define regDP1_DP_DPHY_CRC_MST_STATUS … #define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define regDP1_DP_DPHY_FAST_TRAINING … #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX … #define regDP1_DP_DPHY_FAST_TRAINING_STATUS … #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define regDP1_DP_TU_CNTL … #define regDP1_DP_TU_CNTL_BASE_IDX … #define regDP1_DP_PIXEL_FORMAT_DB_CNTL … #define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX … #define regDP1_DP_CP_LINK_VERIFICATION_PATTERN … #define regDP1_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX … #define regDP1_DP_SEC_CNTL … #define regDP1_DP_SEC_CNTL_BASE_IDX … #define regDP1_DP_SEC_CNTL1 … #define regDP1_DP_SEC_CNTL1_BASE_IDX … #define regDP1_DP_SEC_FRAMING1 … #define regDP1_DP_SEC_FRAMING1_BASE_IDX … #define regDP1_DP_SEC_FRAMING2 … #define regDP1_DP_SEC_FRAMING2_BASE_IDX … #define regDP1_DP_SEC_FRAMING3 … #define regDP1_DP_SEC_FRAMING3_BASE_IDX … #define regDP1_DP_SEC_FRAMING4 … #define regDP1_DP_SEC_FRAMING4_BASE_IDX … #define regDP1_DP_SEC_AUD_N … #define regDP1_DP_SEC_AUD_N_BASE_IDX … #define regDP1_DP_SEC_AUD_N_READBACK … #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX … #define regDP1_DP_SEC_AUD_M … #define regDP1_DP_SEC_AUD_M_BASE_IDX … #define regDP1_DP_SEC_AUD_M_READBACK … #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX … #define regDP1_DP_SEC_TIMESTAMP … #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX … #define regDP1_DP_SEC_PACKET_CNTL … #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX … #define regDP1_DP_MSE_RATE_CNTL … #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX … #define regDP1_DP_CP_MSE_STATUS … #define regDP1_DP_CP_MSE_STATUS_BASE_IDX … #define regDP1_DP_MSE_RATE_UPDATE … #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX … #define regDP1_DP_MSE_SAT0 … #define regDP1_DP_MSE_SAT0_BASE_IDX … #define regDP1_DP_MSE_SAT1 … #define regDP1_DP_MSE_SAT1_BASE_IDX … #define regDP1_DP_MSE_SAT2 … #define regDP1_DP_MSE_SAT2_BASE_IDX … #define regDP1_DP_MSE_SAT_UPDATE … #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX … #define regDP1_DP_MSE_LINK_TIMING … #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX … #define regDP1_DP_MSE_MISC_CNTL … #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX … #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL … #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL … #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define regDP1_DP_MSE_SAT0_STATUS … #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX … #define regDP1_DP_MSE_SAT1_STATUS … #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX … #define regDP1_DP_MSE_SAT2_STATUS … #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX … #define regDP1_DP_DPIA_SPARE … #define regDP1_DP_DPIA_SPARE_BASE_IDX … #define regDP1_DP_HBLANK_CONTROL … #define regDP1_DP_HBLANK_CONTROL_BASE_IDX … #define regDP1_DP_MSA_TIMING_PARAM1 … #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX … #define regDP1_DP_MSA_TIMING_PARAM2 … #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX … #define regDP1_DP_MSA_TIMING_PARAM3 … #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX … #define regDP1_DP_MSA_TIMING_PARAM4 … #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX … #define regDP1_DP_MSO_CNTL … #define regDP1_DP_MSO_CNTL_BASE_IDX … #define regDP1_DP_MSO_CNTL1 … #define regDP1_DP_MSO_CNTL1_BASE_IDX … #define regDP1_DP_STEER_FIFO_CNTL … #define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX … #define regDP1_DP_SEC_CNTL2 … #define regDP1_DP_SEC_CNTL2_BASE_IDX … #define regDP1_DP_SEC_CNTL3 … #define regDP1_DP_SEC_CNTL3_BASE_IDX … #define regDP1_DP_SEC_CNTL4 … #define regDP1_DP_SEC_CNTL4_BASE_IDX … #define regDP1_DP_SEC_CNTL5 … #define regDP1_DP_SEC_CNTL5_BASE_IDX … #define regDP1_DP_SEC_CNTL6 … #define regDP1_DP_SEC_CNTL6_BASE_IDX … #define regDP1_DP_SEC_CNTL7 … #define regDP1_DP_SEC_CNTL7_BASE_IDX … #define regDP1_DP_DB_CNTL … #define regDP1_DP_DB_CNTL_BASE_IDX … #define regDP1_DP_MSA_VBID_MISC … #define regDP1_DP_MSA_VBID_MISC_BASE_IDX … #define regDP1_DP_SEC_METADATA_TRANSMISSION … #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define regDP1_DP_ALPM_CNTL … #define regDP1_DP_ALPM_CNTL_BASE_IDX … #define regDP1_DP_GSP8_CNTL … #define regDP1_DP_GSP8_CNTL_BASE_IDX … #define regDP1_DP_GSP9_CNTL … #define regDP1_DP_GSP9_CNTL_BASE_IDX … #define regDP1_DP_GSP10_CNTL … #define regDP1_DP_GSP10_CNTL_BASE_IDX … #define regDP1_DP_GSP11_CNTL … #define regDP1_DP_GSP11_CNTL_BASE_IDX … #define regDP1_DP_GSP_EN_DB_STATUS … #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX … #define regDP1_DP_AUXLESS_ALPM_CNTL1 … #define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX … #define regDP1_DP_AUXLESS_ALPM_CNTL2 … #define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX … #define regDP1_DP_AUXLESS_ALPM_CNTL3 … #define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX … #define regDP1_DP_AUXLESS_ALPM_CNTL4 … #define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX … #define regDP1_DP_AUXLESS_ALPM_CNTL5 … #define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX … #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS … #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL … #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 … #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 … #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL … #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig1_dispdec // base address: 0x490 #define regDIG1_DIG_FE_CNTL … #define regDIG1_DIG_FE_CNTL_BASE_IDX … #define regDIG1_DIG_FE_CLK_CNTL … #define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX … #define regDIG1_DIG_FE_EN_CNTL … #define regDIG1_DIG_FE_EN_CNTL_BASE_IDX … #define regDIG1_DIG_OUTPUT_CRC_CNTL … #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define regDIG1_DIG_OUTPUT_CRC_RESULT … #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define regDIG1_DIG_CLOCK_PATTERN … #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX … #define regDIG1_DIG_TEST_PATTERN … #define regDIG1_DIG_TEST_PATTERN_BASE_IDX … #define regDIG1_DIG_RANDOM_PATTERN_SEED … #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define regDIG1_DIG_FIFO_CTRL0 … #define regDIG1_DIG_FIFO_CTRL0_BASE_IDX … #define regDIG1_DIG_FIFO_CTRL1 … #define regDIG1_DIG_FIFO_CTRL1_BASE_IDX … #define regDIG1_HDMI_METADATA_PACKET_CONTROL … #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define regDIG1_HDMI_CONTROL … #define regDIG1_HDMI_CONTROL_BASE_IDX … #define regDIG1_HDMI_STATUS … #define regDIG1_HDMI_STATUS_BASE_IDX … #define regDIG1_HDMI_AUDIO_PACKET_CONTROL … #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define regDIG1_HDMI_ACR_PACKET_CONTROL … #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define regDIG1_HDMI_VBI_PACKET_CONTROL … #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define regDIG1_HDMI_INFOFRAME_CONTROL0 … #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define regDIG1_HDMI_INFOFRAME_CONTROL1 … #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … #define regDIG1_HDMI_GC … #define regDIG1_HDMI_GC_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 … #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX … #define regDIG1_HDMI_DB_CONTROL … #define regDIG1_HDMI_DB_CONTROL_BASE_IDX … #define regDIG1_HDMI_ACR_32_0 … #define regDIG1_HDMI_ACR_32_0_BASE_IDX … #define regDIG1_HDMI_ACR_32_1 … #define regDIG1_HDMI_ACR_32_1_BASE_IDX … #define regDIG1_HDMI_ACR_44_0 … #define regDIG1_HDMI_ACR_44_0_BASE_IDX … #define regDIG1_HDMI_ACR_44_1 … #define regDIG1_HDMI_ACR_44_1_BASE_IDX … #define regDIG1_HDMI_ACR_48_0 … #define regDIG1_HDMI_ACR_48_0_BASE_IDX … #define regDIG1_HDMI_ACR_48_1 … #define regDIG1_HDMI_ACR_48_1_BASE_IDX … #define regDIG1_HDMI_ACR_STATUS_0 … #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX … #define regDIG1_HDMI_ACR_STATUS_1 … #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX … #define regDIG1_AFMT_CNTL … #define regDIG1_AFMT_CNTL_BASE_IDX … #define regDIG1_DIG_BE_CLK_CNTL … #define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX … #define regDIG1_DIG_BE_CNTL … #define regDIG1_DIG_BE_CNTL_BASE_IDX … #define regDIG1_DIG_BE_EN_CNTL … #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX … #define regDIG1_TMDS_CNTL … #define regDIG1_TMDS_CNTL_BASE_IDX … #define regDIG1_TMDS_CONTROL_CHAR … #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX … #define regDIG1_TMDS_CONTROL0_FEEDBACK … #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define regDIG1_TMDS_STEREOSYNC_CTL_SEL … #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 … #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 … #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define regDIG1_TMDS_CTL_BITS … #define regDIG1_TMDS_CTL_BITS_BASE_IDX … #define regDIG1_TMDS_DCBALANCER_CONTROL … #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR … #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define regDIG1_TMDS_CTL0_1_GEN_CNTL … #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define regDIG1_TMDS_CTL2_3_GEN_CNTL … #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define regDIG1_DIG_VERSION … #define regDIG1_DIG_VERSION_BASE_IDX … // addressBlock: dcn_dcec_dio_dp2_dispdec // base address: 0x920 #define regDP2_DP_LINK_CNTL … #define regDP2_DP_LINK_CNTL_BASE_IDX … #define regDP2_DP_PIXEL_FORMAT … #define regDP2_DP_PIXEL_FORMAT_BASE_IDX … #define regDP2_DP_MSA_COLORIMETRY … #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX … #define regDP2_DP_CONFIG … #define regDP2_DP_CONFIG_BASE_IDX … #define regDP2_DP_VID_STREAM_CNTL … #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX … #define regDP2_DP_STEER_FIFO … #define regDP2_DP_STEER_FIFO_BASE_IDX … #define regDP2_DP_MSA_MISC … #define regDP2_DP_MSA_MISC_BASE_IDX … #define regDP2_DP_DPHY_INTERNAL_CTRL … #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define regDP2_DP_VID_TIMING … #define regDP2_DP_VID_TIMING_BASE_IDX … #define regDP2_DP_VID_N … #define regDP2_DP_VID_N_BASE_IDX … #define regDP2_DP_VID_M … #define regDP2_DP_VID_M_BASE_IDX … #define regDP2_DP_LINK_FRAMING_CNTL … #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX … #define regDP2_DP_HBR2_EYE_PATTERN … #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX … #define regDP2_DP_VID_MSA_VBID … #define regDP2_DP_VID_MSA_VBID_BASE_IDX … #define regDP2_DP_VID_INTERRUPT_CNTL … #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define regDP2_DP_DPHY_CNTL … #define regDP2_DP_DPHY_CNTL_BASE_IDX … #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL … #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define regDP2_DP_DPHY_SYM0 … #define regDP2_DP_DPHY_SYM0_BASE_IDX … #define regDP2_DP_DPHY_SYM1 … #define regDP2_DP_DPHY_SYM1_BASE_IDX … #define regDP2_DP_DPHY_SYM2 … #define regDP2_DP_DPHY_SYM2_BASE_IDX … #define regDP2_DP_DPHY_8B10B_CNTL … #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX … #define regDP2_DP_DPHY_PRBS_CNTL … #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX … #define regDP2_DP_DPHY_SCRAM_CNTL … #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define regDP2_DP_DPHY_CRC_EN … #define regDP2_DP_DPHY_CRC_EN_BASE_IDX … #define regDP2_DP_DPHY_CRC_CNTL … #define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX … #define regDP2_DP_DPHY_CRC_RESULT … #define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX … #define regDP2_DP_DPHY_CRC_MST_CNTL … #define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define regDP2_DP_DPHY_CRC_MST_STATUS … #define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define regDP2_DP_DPHY_FAST_TRAINING … #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX … #define regDP2_DP_DPHY_FAST_TRAINING_STATUS … #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define regDP2_DP_TU_CNTL … #define regDP2_DP_TU_CNTL_BASE_IDX … #define regDP2_DP_PIXEL_FORMAT_DB_CNTL … #define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX … #define regDP2_DP_CP_LINK_VERIFICATION_PATTERN … #define regDP2_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX … #define regDP2_DP_SEC_CNTL … #define regDP2_DP_SEC_CNTL_BASE_IDX … #define regDP2_DP_SEC_CNTL1 … #define regDP2_DP_SEC_CNTL1_BASE_IDX … #define regDP2_DP_SEC_FRAMING1 … #define regDP2_DP_SEC_FRAMING1_BASE_IDX … #define regDP2_DP_SEC_FRAMING2 … #define regDP2_DP_SEC_FRAMING2_BASE_IDX … #define regDP2_DP_SEC_FRAMING3 … #define regDP2_DP_SEC_FRAMING3_BASE_IDX … #define regDP2_DP_SEC_FRAMING4 … #define regDP2_DP_SEC_FRAMING4_BASE_IDX … #define regDP2_DP_SEC_AUD_N … #define regDP2_DP_SEC_AUD_N_BASE_IDX … #define regDP2_DP_SEC_AUD_N_READBACK … #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX … #define regDP2_DP_SEC_AUD_M … #define regDP2_DP_SEC_AUD_M_BASE_IDX … #define regDP2_DP_SEC_AUD_M_READBACK … #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX … #define regDP2_DP_SEC_TIMESTAMP … #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX … #define regDP2_DP_SEC_PACKET_CNTL … #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX … #define regDP2_DP_MSE_RATE_CNTL … #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX … #define regDP2_DP_CP_MSE_STATUS … #define regDP2_DP_CP_MSE_STATUS_BASE_IDX … #define regDP2_DP_MSE_RATE_UPDATE … #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX … #define regDP2_DP_MSE_SAT0 … #define regDP2_DP_MSE_SAT0_BASE_IDX … #define regDP2_DP_MSE_SAT1 … #define regDP2_DP_MSE_SAT1_BASE_IDX … #define regDP2_DP_MSE_SAT2 … #define regDP2_DP_MSE_SAT2_BASE_IDX … #define regDP2_DP_MSE_SAT_UPDATE … #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX … #define regDP2_DP_MSE_LINK_TIMING … #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX … #define regDP2_DP_MSE_MISC_CNTL … #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX … #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL … #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL … #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define regDP2_DP_MSE_SAT0_STATUS … #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX … #define regDP2_DP_MSE_SAT1_STATUS … #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX … #define regDP2_DP_MSE_SAT2_STATUS … #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX … #define regDP2_DP_DPIA_SPARE … #define regDP2_DP_DPIA_SPARE_BASE_IDX … #define regDP2_DP_HBLANK_CONTROL … #define regDP2_DP_HBLANK_CONTROL_BASE_IDX … #define regDP2_DP_MSA_TIMING_PARAM1 … #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX … #define regDP2_DP_MSA_TIMING_PARAM2 … #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX … #define regDP2_DP_MSA_TIMING_PARAM3 … #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX … #define regDP2_DP_MSA_TIMING_PARAM4 … #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX … #define regDP2_DP_MSO_CNTL … #define regDP2_DP_MSO_CNTL_BASE_IDX … #define regDP2_DP_MSO_CNTL1 … #define regDP2_DP_MSO_CNTL1_BASE_IDX … #define regDP2_DP_STEER_FIFO_CNTL … #define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX … #define regDP2_DP_SEC_CNTL2 … #define regDP2_DP_SEC_CNTL2_BASE_IDX … #define regDP2_DP_SEC_CNTL3 … #define regDP2_DP_SEC_CNTL3_BASE_IDX … #define regDP2_DP_SEC_CNTL4 … #define regDP2_DP_SEC_CNTL4_BASE_IDX … #define regDP2_DP_SEC_CNTL5 … #define regDP2_DP_SEC_CNTL5_BASE_IDX … #define regDP2_DP_SEC_CNTL6 … #define regDP2_DP_SEC_CNTL6_BASE_IDX … #define regDP2_DP_SEC_CNTL7 … #define regDP2_DP_SEC_CNTL7_BASE_IDX … #define regDP2_DP_DB_CNTL … #define regDP2_DP_DB_CNTL_BASE_IDX … #define regDP2_DP_MSA_VBID_MISC … #define regDP2_DP_MSA_VBID_MISC_BASE_IDX … #define regDP2_DP_SEC_METADATA_TRANSMISSION … #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define regDP2_DP_ALPM_CNTL … #define regDP2_DP_ALPM_CNTL_BASE_IDX … #define regDP2_DP_GSP8_CNTL … #define regDP2_DP_GSP8_CNTL_BASE_IDX … #define regDP2_DP_GSP9_CNTL … #define regDP2_DP_GSP9_CNTL_BASE_IDX … #define regDP2_DP_GSP10_CNTL … #define regDP2_DP_GSP10_CNTL_BASE_IDX … #define regDP2_DP_GSP11_CNTL … #define regDP2_DP_GSP11_CNTL_BASE_IDX … #define regDP2_DP_GSP_EN_DB_STATUS … #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX … #define regDP2_DP_AUXLESS_ALPM_CNTL1 … #define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX … #define regDP2_DP_AUXLESS_ALPM_CNTL2 … #define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX … #define regDP2_DP_AUXLESS_ALPM_CNTL3 … #define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX … #define regDP2_DP_AUXLESS_ALPM_CNTL4 … #define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX … #define regDP2_DP_AUXLESS_ALPM_CNTL5 … #define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX … #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS … #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL … #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 … #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 … #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL … #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig2_dispdec // base address: 0x920 #define regDIG2_DIG_FE_CNTL … #define regDIG2_DIG_FE_CNTL_BASE_IDX … #define regDIG2_DIG_FE_CLK_CNTL … #define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX … #define regDIG2_DIG_FE_EN_CNTL … #define regDIG2_DIG_FE_EN_CNTL_BASE_IDX … #define regDIG2_DIG_OUTPUT_CRC_CNTL … #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define regDIG2_DIG_OUTPUT_CRC_RESULT … #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define regDIG2_DIG_CLOCK_PATTERN … #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX … #define regDIG2_DIG_TEST_PATTERN … #define regDIG2_DIG_TEST_PATTERN_BASE_IDX … #define regDIG2_DIG_RANDOM_PATTERN_SEED … #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define regDIG2_DIG_FIFO_CTRL0 … #define regDIG2_DIG_FIFO_CTRL0_BASE_IDX … #define regDIG2_DIG_FIFO_CTRL1 … #define regDIG2_DIG_FIFO_CTRL1_BASE_IDX … #define regDIG2_HDMI_METADATA_PACKET_CONTROL … #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define regDIG2_HDMI_CONTROL … #define regDIG2_HDMI_CONTROL_BASE_IDX … #define regDIG2_HDMI_STATUS … #define regDIG2_HDMI_STATUS_BASE_IDX … #define regDIG2_HDMI_AUDIO_PACKET_CONTROL … #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define regDIG2_HDMI_ACR_PACKET_CONTROL … #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define regDIG2_HDMI_VBI_PACKET_CONTROL … #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define regDIG2_HDMI_INFOFRAME_CONTROL0 … #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define regDIG2_HDMI_INFOFRAME_CONTROL1 … #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … #define regDIG2_HDMI_GC … #define regDIG2_HDMI_GC_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 … #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX … #define regDIG2_HDMI_DB_CONTROL … #define regDIG2_HDMI_DB_CONTROL_BASE_IDX … #define regDIG2_HDMI_ACR_32_0 … #define regDIG2_HDMI_ACR_32_0_BASE_IDX … #define regDIG2_HDMI_ACR_32_1 … #define regDIG2_HDMI_ACR_32_1_BASE_IDX … #define regDIG2_HDMI_ACR_44_0 … #define regDIG2_HDMI_ACR_44_0_BASE_IDX … #define regDIG2_HDMI_ACR_44_1 … #define regDIG2_HDMI_ACR_44_1_BASE_IDX … #define regDIG2_HDMI_ACR_48_0 … #define regDIG2_HDMI_ACR_48_0_BASE_IDX … #define regDIG2_HDMI_ACR_48_1 … #define regDIG2_HDMI_ACR_48_1_BASE_IDX … #define regDIG2_HDMI_ACR_STATUS_0 … #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX … #define regDIG2_HDMI_ACR_STATUS_1 … #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX … #define regDIG2_AFMT_CNTL … #define regDIG2_AFMT_CNTL_BASE_IDX … #define regDIG2_DIG_BE_CLK_CNTL … #define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX … #define regDIG2_DIG_BE_CNTL … #define regDIG2_DIG_BE_CNTL_BASE_IDX … #define regDIG2_DIG_BE_EN_CNTL … #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX … #define regDIG2_TMDS_CNTL … #define regDIG2_TMDS_CNTL_BASE_IDX … #define regDIG2_TMDS_CONTROL_CHAR … #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX … #define regDIG2_TMDS_CONTROL0_FEEDBACK … #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define regDIG2_TMDS_STEREOSYNC_CTL_SEL … #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 … #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 … #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define regDIG2_TMDS_CTL_BITS … #define regDIG2_TMDS_CTL_BITS_BASE_IDX … #define regDIG2_TMDS_DCBALANCER_CONTROL … #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR … #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define regDIG2_TMDS_CTL0_1_GEN_CNTL … #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define regDIG2_TMDS_CTL2_3_GEN_CNTL … #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define regDIG2_DIG_VERSION … #define regDIG2_DIG_VERSION_BASE_IDX … // addressBlock: dcn_dcec_dio_dp3_dispdec // base address: 0xdb0 #define regDP3_DP_LINK_CNTL … #define regDP3_DP_LINK_CNTL_BASE_IDX … #define regDP3_DP_PIXEL_FORMAT … #define regDP3_DP_PIXEL_FORMAT_BASE_IDX … #define regDP3_DP_MSA_COLORIMETRY … #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX … #define regDP3_DP_CONFIG … #define regDP3_DP_CONFIG_BASE_IDX … #define regDP3_DP_VID_STREAM_CNTL … #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX … #define regDP3_DP_STEER_FIFO … #define regDP3_DP_STEER_FIFO_BASE_IDX … #define regDP3_DP_MSA_MISC … #define regDP3_DP_MSA_MISC_BASE_IDX … #define regDP3_DP_DPHY_INTERNAL_CTRL … #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define regDP3_DP_VID_TIMING … #define regDP3_DP_VID_TIMING_BASE_IDX … #define regDP3_DP_VID_N … #define regDP3_DP_VID_N_BASE_IDX … #define regDP3_DP_VID_M … #define regDP3_DP_VID_M_BASE_IDX … #define regDP3_DP_LINK_FRAMING_CNTL … #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX … #define regDP3_DP_HBR2_EYE_PATTERN … #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX … #define regDP3_DP_VID_MSA_VBID … #define regDP3_DP_VID_MSA_VBID_BASE_IDX … #define regDP3_DP_VID_INTERRUPT_CNTL … #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define regDP3_DP_DPHY_CNTL … #define regDP3_DP_DPHY_CNTL_BASE_IDX … #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL … #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define regDP3_DP_DPHY_SYM0 … #define regDP3_DP_DPHY_SYM0_BASE_IDX … #define regDP3_DP_DPHY_SYM1 … #define regDP3_DP_DPHY_SYM1_BASE_IDX … #define regDP3_DP_DPHY_SYM2 … #define regDP3_DP_DPHY_SYM2_BASE_IDX … #define regDP3_DP_DPHY_8B10B_CNTL … #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX … #define regDP3_DP_DPHY_PRBS_CNTL … #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX … #define regDP3_DP_DPHY_SCRAM_CNTL … #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define regDP3_DP_DPHY_CRC_EN … #define regDP3_DP_DPHY_CRC_EN_BASE_IDX … #define regDP3_DP_DPHY_CRC_CNTL … #define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX … #define regDP3_DP_DPHY_CRC_RESULT … #define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX … #define regDP3_DP_DPHY_CRC_MST_CNTL … #define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define regDP3_DP_DPHY_CRC_MST_STATUS … #define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define regDP3_DP_DPHY_FAST_TRAINING … #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX … #define regDP3_DP_DPHY_FAST_TRAINING_STATUS … #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define regDP3_DP_TU_CNTL … #define regDP3_DP_TU_CNTL_BASE_IDX … #define regDP3_DP_PIXEL_FORMAT_DB_CNTL … #define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX … #define regDP3_DP_CP_LINK_VERIFICATION_PATTERN … #define regDP3_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX … #define regDP3_DP_SEC_CNTL … #define regDP3_DP_SEC_CNTL_BASE_IDX … #define regDP3_DP_SEC_CNTL1 … #define regDP3_DP_SEC_CNTL1_BASE_IDX … #define regDP3_DP_SEC_FRAMING1 … #define regDP3_DP_SEC_FRAMING1_BASE_IDX … #define regDP3_DP_SEC_FRAMING2 … #define regDP3_DP_SEC_FRAMING2_BASE_IDX … #define regDP3_DP_SEC_FRAMING3 … #define regDP3_DP_SEC_FRAMING3_BASE_IDX … #define regDP3_DP_SEC_FRAMING4 … #define regDP3_DP_SEC_FRAMING4_BASE_IDX … #define regDP3_DP_SEC_AUD_N … #define regDP3_DP_SEC_AUD_N_BASE_IDX … #define regDP3_DP_SEC_AUD_N_READBACK … #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX … #define regDP3_DP_SEC_AUD_M … #define regDP3_DP_SEC_AUD_M_BASE_IDX … #define regDP3_DP_SEC_AUD_M_READBACK … #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX … #define regDP3_DP_SEC_TIMESTAMP … #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX … #define regDP3_DP_SEC_PACKET_CNTL … #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX … #define regDP3_DP_MSE_RATE_CNTL … #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX … #define regDP3_DP_CP_MSE_STATUS … #define regDP3_DP_CP_MSE_STATUS_BASE_IDX … #define regDP3_DP_MSE_RATE_UPDATE … #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX … #define regDP3_DP_MSE_SAT0 … #define regDP3_DP_MSE_SAT0_BASE_IDX … #define regDP3_DP_MSE_SAT1 … #define regDP3_DP_MSE_SAT1_BASE_IDX … #define regDP3_DP_MSE_SAT2 … #define regDP3_DP_MSE_SAT2_BASE_IDX … #define regDP3_DP_MSE_SAT_UPDATE … #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX … #define regDP3_DP_MSE_LINK_TIMING … #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX … #define regDP3_DP_MSE_MISC_CNTL … #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX … #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL … #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL … #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define regDP3_DP_MSE_SAT0_STATUS … #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX … #define regDP3_DP_MSE_SAT1_STATUS … #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX … #define regDP3_DP_MSE_SAT2_STATUS … #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX … #define regDP3_DP_DPIA_SPARE … #define regDP3_DP_DPIA_SPARE_BASE_IDX … #define regDP3_DP_HBLANK_CONTROL … #define regDP3_DP_HBLANK_CONTROL_BASE_IDX … #define regDP3_DP_MSA_TIMING_PARAM1 … #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX … #define regDP3_DP_MSA_TIMING_PARAM2 … #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX … #define regDP3_DP_MSA_TIMING_PARAM3 … #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX … #define regDP3_DP_MSA_TIMING_PARAM4 … #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX … #define regDP3_DP_MSO_CNTL … #define regDP3_DP_MSO_CNTL_BASE_IDX … #define regDP3_DP_MSO_CNTL1 … #define regDP3_DP_MSO_CNTL1_BASE_IDX … #define regDP3_DP_STEER_FIFO_CNTL … #define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX … #define regDP3_DP_SEC_CNTL2 … #define regDP3_DP_SEC_CNTL2_BASE_IDX … #define regDP3_DP_SEC_CNTL3 … #define regDP3_DP_SEC_CNTL3_BASE_IDX … #define regDP3_DP_SEC_CNTL4 … #define regDP3_DP_SEC_CNTL4_BASE_IDX … #define regDP3_DP_SEC_CNTL5 … #define regDP3_DP_SEC_CNTL5_BASE_IDX … #define regDP3_DP_SEC_CNTL6 … #define regDP3_DP_SEC_CNTL6_BASE_IDX … #define regDP3_DP_SEC_CNTL7 … #define regDP3_DP_SEC_CNTL7_BASE_IDX … #define regDP3_DP_DB_CNTL … #define regDP3_DP_DB_CNTL_BASE_IDX … #define regDP3_DP_MSA_VBID_MISC … #define regDP3_DP_MSA_VBID_MISC_BASE_IDX … #define regDP3_DP_SEC_METADATA_TRANSMISSION … #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define regDP3_DP_ALPM_CNTL … #define regDP3_DP_ALPM_CNTL_BASE_IDX … #define regDP3_DP_GSP8_CNTL … #define regDP3_DP_GSP8_CNTL_BASE_IDX … #define regDP3_DP_GSP9_CNTL … #define regDP3_DP_GSP9_CNTL_BASE_IDX … #define regDP3_DP_GSP10_CNTL … #define regDP3_DP_GSP10_CNTL_BASE_IDX … #define regDP3_DP_GSP11_CNTL … #define regDP3_DP_GSP11_CNTL_BASE_IDX … #define regDP3_DP_GSP_EN_DB_STATUS … #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX … #define regDP3_DP_AUXLESS_ALPM_CNTL1 … #define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX … #define regDP3_DP_AUXLESS_ALPM_CNTL2 … #define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX … #define regDP3_DP_AUXLESS_ALPM_CNTL3 … #define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX … #define regDP3_DP_AUXLESS_ALPM_CNTL4 … #define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX … #define regDP3_DP_AUXLESS_ALPM_CNTL5 … #define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX … #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS … #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL … #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 … #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 … #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL … #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig3_dispdec // base address: 0xdb0 #define regDIG3_DIG_FE_CNTL … #define regDIG3_DIG_FE_CNTL_BASE_IDX … #define regDIG3_DIG_FE_CLK_CNTL … #define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX … #define regDIG3_DIG_FE_EN_CNTL … #define regDIG3_DIG_FE_EN_CNTL_BASE_IDX … #define regDIG3_DIG_OUTPUT_CRC_CNTL … #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define regDIG3_DIG_OUTPUT_CRC_RESULT … #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define regDIG3_DIG_CLOCK_PATTERN … #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX … #define regDIG3_DIG_TEST_PATTERN … #define regDIG3_DIG_TEST_PATTERN_BASE_IDX … #define regDIG3_DIG_RANDOM_PATTERN_SEED … #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define regDIG3_DIG_FIFO_CTRL0 … #define regDIG3_DIG_FIFO_CTRL0_BASE_IDX … #define regDIG3_DIG_FIFO_CTRL1 … #define regDIG3_DIG_FIFO_CTRL1_BASE_IDX … #define regDIG3_HDMI_METADATA_PACKET_CONTROL … #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define regDIG3_HDMI_CONTROL … #define regDIG3_HDMI_CONTROL_BASE_IDX … #define regDIG3_HDMI_STATUS … #define regDIG3_HDMI_STATUS_BASE_IDX … #define regDIG3_HDMI_AUDIO_PACKET_CONTROL … #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define regDIG3_HDMI_ACR_PACKET_CONTROL … #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define regDIG3_HDMI_VBI_PACKET_CONTROL … #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define regDIG3_HDMI_INFOFRAME_CONTROL0 … #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define regDIG3_HDMI_INFOFRAME_CONTROL1 … #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … #define regDIG3_HDMI_GC … #define regDIG3_HDMI_GC_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 … #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX … #define regDIG3_HDMI_DB_CONTROL … #define regDIG3_HDMI_DB_CONTROL_BASE_IDX … #define regDIG3_HDMI_ACR_32_0 … #define regDIG3_HDMI_ACR_32_0_BASE_IDX … #define regDIG3_HDMI_ACR_32_1 … #define regDIG3_HDMI_ACR_32_1_BASE_IDX … #define regDIG3_HDMI_ACR_44_0 … #define regDIG3_HDMI_ACR_44_0_BASE_IDX … #define regDIG3_HDMI_ACR_44_1 … #define regDIG3_HDMI_ACR_44_1_BASE_IDX … #define regDIG3_HDMI_ACR_48_0 … #define regDIG3_HDMI_ACR_48_0_BASE_IDX … #define regDIG3_HDMI_ACR_48_1 … #define regDIG3_HDMI_ACR_48_1_BASE_IDX … #define regDIG3_HDMI_ACR_STATUS_0 … #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX … #define regDIG3_HDMI_ACR_STATUS_1 … #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX … #define regDIG3_AFMT_CNTL … #define regDIG3_AFMT_CNTL_BASE_IDX … #define regDIG3_DIG_BE_CLK_CNTL … #define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX … #define regDIG3_DIG_BE_CNTL … #define regDIG3_DIG_BE_CNTL_BASE_IDX … #define regDIG3_DIG_BE_EN_CNTL … #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX … #define regDIG3_TMDS_CNTL … #define regDIG3_TMDS_CNTL_BASE_IDX … #define regDIG3_TMDS_CONTROL_CHAR … #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX … #define regDIG3_TMDS_CONTROL0_FEEDBACK … #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define regDIG3_TMDS_STEREOSYNC_CTL_SEL … #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 … #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 … #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define regDIG3_TMDS_CTL_BITS … #define regDIG3_TMDS_CTL_BITS_BASE_IDX … #define regDIG3_TMDS_DCBALANCER_CONTROL … #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR … #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define regDIG3_TMDS_CTL0_1_GEN_CNTL … #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define regDIG3_TMDS_CTL2_3_GEN_CNTL … #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define regDIG3_DIG_VERSION … #define regDIG3_DIG_VERSION_BASE_IDX … // addressBlock: dcn_dcec_dio_dig0_afmt_afmt_dispdec // base address: 0x154cc #define regAFMT0_AFMT_ACP … #define regAFMT0_AFMT_ACP_BASE_IDX … #define regAFMT0_AFMT_VBI_PACKET_CONTROL … #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 … #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define regAFMT0_AFMT_AUDIO_INFO0 … #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX … #define regAFMT0_AFMT_AUDIO_INFO1 … #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX … #define regAFMT0_AFMT_60958_0 … #define regAFMT0_AFMT_60958_0_BASE_IDX … #define regAFMT0_AFMT_60958_1 … #define regAFMT0_AFMT_60958_1_BASE_IDX … #define regAFMT0_AFMT_AUDIO_CRC_CONTROL … #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define regAFMT0_AFMT_RAMP_CONTROL0 … #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX … #define regAFMT0_AFMT_RAMP_CONTROL1 … #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX … #define regAFMT0_AFMT_RAMP_CONTROL2 … #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX … #define regAFMT0_AFMT_RAMP_CONTROL3 … #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX … #define regAFMT0_AFMT_60958_2 … #define regAFMT0_AFMT_60958_2_BASE_IDX … #define regAFMT0_AFMT_AUDIO_CRC_RESULT … #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define regAFMT0_AFMT_STATUS … #define regAFMT0_AFMT_STATUS_BASE_IDX … #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL … #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define regAFMT0_AFMT_INFOFRAME_CONTROL0 … #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define regAFMT0_AFMT_INTERRUPT_STATUS … #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX … #define regAFMT0_AFMT_AUDIO_SRC_CONTROL … #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL … #define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX … #define regAFMT0_AFMT_MEM_PWR … #define regAFMT0_AFMT_MEM_PWR_BASE_IDX … // addressBlock: dcn_dcec_dio_dig1_afmt_afmt_dispdec // base address: 0x1595c #define regAFMT1_AFMT_ACP … #define regAFMT1_AFMT_ACP_BASE_IDX … #define regAFMT1_AFMT_VBI_PACKET_CONTROL … #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 … #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define regAFMT1_AFMT_AUDIO_INFO0 … #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX … #define regAFMT1_AFMT_AUDIO_INFO1 … #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX … #define regAFMT1_AFMT_60958_0 … #define regAFMT1_AFMT_60958_0_BASE_IDX … #define regAFMT1_AFMT_60958_1 … #define regAFMT1_AFMT_60958_1_BASE_IDX … #define regAFMT1_AFMT_AUDIO_CRC_CONTROL … #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define regAFMT1_AFMT_RAMP_CONTROL0 … #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX … #define regAFMT1_AFMT_RAMP_CONTROL1 … #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX … #define regAFMT1_AFMT_RAMP_CONTROL2 … #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX … #define regAFMT1_AFMT_RAMP_CONTROL3 … #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX … #define regAFMT1_AFMT_60958_2 … #define regAFMT1_AFMT_60958_2_BASE_IDX … #define regAFMT1_AFMT_AUDIO_CRC_RESULT … #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define regAFMT1_AFMT_STATUS … #define regAFMT1_AFMT_STATUS_BASE_IDX … #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL … #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define regAFMT1_AFMT_INFOFRAME_CONTROL0 … #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define regAFMT1_AFMT_INTERRUPT_STATUS … #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX … #define regAFMT1_AFMT_AUDIO_SRC_CONTROL … #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL … #define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX … #define regAFMT1_AFMT_MEM_PWR … #define regAFMT1_AFMT_MEM_PWR_BASE_IDX … // addressBlock: dcn_dcec_dio_dig2_afmt_afmt_dispdec // base address: 0x15dec #define regAFMT2_AFMT_ACP … #define regAFMT2_AFMT_ACP_BASE_IDX … #define regAFMT2_AFMT_VBI_PACKET_CONTROL … #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 … #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define regAFMT2_AFMT_AUDIO_INFO0 … #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX … #define regAFMT2_AFMT_AUDIO_INFO1 … #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX … #define regAFMT2_AFMT_60958_0 … #define regAFMT2_AFMT_60958_0_BASE_IDX … #define regAFMT2_AFMT_60958_1 … #define regAFMT2_AFMT_60958_1_BASE_IDX … #define regAFMT2_AFMT_AUDIO_CRC_CONTROL … #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define regAFMT2_AFMT_RAMP_CONTROL0 … #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX … #define regAFMT2_AFMT_RAMP_CONTROL1 … #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX … #define regAFMT2_AFMT_RAMP_CONTROL2 … #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX … #define regAFMT2_AFMT_RAMP_CONTROL3 … #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX … #define regAFMT2_AFMT_60958_2 … #define regAFMT2_AFMT_60958_2_BASE_IDX … #define regAFMT2_AFMT_AUDIO_CRC_RESULT … #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define regAFMT2_AFMT_STATUS … #define regAFMT2_AFMT_STATUS_BASE_IDX … #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL … #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define regAFMT2_AFMT_INFOFRAME_CONTROL0 … #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define regAFMT2_AFMT_INTERRUPT_STATUS … #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX … #define regAFMT2_AFMT_AUDIO_SRC_CONTROL … #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL … #define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX … #define regAFMT2_AFMT_MEM_PWR … #define regAFMT2_AFMT_MEM_PWR_BASE_IDX … // addressBlock: dcn_dcec_dio_dig3_afmt_afmt_dispdec // base address: 0x1627c #define regAFMT3_AFMT_ACP … #define regAFMT3_AFMT_ACP_BASE_IDX … #define regAFMT3_AFMT_VBI_PACKET_CONTROL … #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 … #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define regAFMT3_AFMT_AUDIO_INFO0 … #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX … #define regAFMT3_AFMT_AUDIO_INFO1 … #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX … #define regAFMT3_AFMT_60958_0 … #define regAFMT3_AFMT_60958_0_BASE_IDX … #define regAFMT3_AFMT_60958_1 … #define regAFMT3_AFMT_60958_1_BASE_IDX … #define regAFMT3_AFMT_AUDIO_CRC_CONTROL … #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define regAFMT3_AFMT_RAMP_CONTROL0 … #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX … #define regAFMT3_AFMT_RAMP_CONTROL1 … #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX … #define regAFMT3_AFMT_RAMP_CONTROL2 … #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX … #define regAFMT3_AFMT_RAMP_CONTROL3 … #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX … #define regAFMT3_AFMT_60958_2 … #define regAFMT3_AFMT_60958_2_BASE_IDX … #define regAFMT3_AFMT_AUDIO_CRC_RESULT … #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define regAFMT3_AFMT_STATUS … #define regAFMT3_AFMT_STATUS_BASE_IDX … #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL … #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define regAFMT3_AFMT_INFOFRAME_CONTROL0 … #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define regAFMT3_AFMT_INTERRUPT_STATUS … #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX … #define regAFMT3_AFMT_AUDIO_SRC_CONTROL … #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL … #define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX … #define regAFMT3_AFMT_MEM_PWR … #define regAFMT3_AFMT_MEM_PWR_BASE_IDX … // addressBlock: dcn_dcec_dio_dig0_dme_dme_dispdec // base address: 0x15544 #define regDME0_DME_CONTROL … #define regDME0_DME_CONTROL_BASE_IDX … #define regDME0_DME_MEMORY_CONTROL … #define regDME0_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig0_vpg_vpg_dispdec // base address: 0x154a0 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG0_VPG_GENERIC_PACKET_DATA … #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG0_VPG_GENERIC_STATUS … #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG0_VPG_MEM_PWR … #define regVPG0_VPG_MEM_PWR_BASE_IDX … #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG0_VPG_ISRC1_2_DATA … #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG0_VPG_MPEG_INFO0 … #define regVPG0_VPG_MPEG_INFO0_BASE_IDX … #define regVPG0_VPG_MPEG_INFO1 … #define regVPG0_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_dio_dig1_dme_dme_dispdec // base address: 0x159d4 #define regDME1_DME_CONTROL … #define regDME1_DME_CONTROL_BASE_IDX … #define regDME1_DME_MEMORY_CONTROL … #define regDME1_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig1_vpg_vpg_dispdec // base address: 0x15930 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG1_VPG_GENERIC_PACKET_DATA … #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG1_VPG_GENERIC_STATUS … #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG1_VPG_MEM_PWR … #define regVPG1_VPG_MEM_PWR_BASE_IDX … #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG1_VPG_ISRC1_2_DATA … #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG1_VPG_MPEG_INFO0 … #define regVPG1_VPG_MPEG_INFO0_BASE_IDX … #define regVPG1_VPG_MPEG_INFO1 … #define regVPG1_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_dio_dig2_dme_dme_dispdec // base address: 0x15e64 #define regDME2_DME_CONTROL … #define regDME2_DME_CONTROL_BASE_IDX … #define regDME2_DME_MEMORY_CONTROL … #define regDME2_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig2_vpg_vpg_dispdec // base address: 0x15dc0 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG2_VPG_GENERIC_PACKET_DATA … #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG2_VPG_GENERIC_STATUS … #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG2_VPG_MEM_PWR … #define regVPG2_VPG_MEM_PWR_BASE_IDX … #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG2_VPG_ISRC1_2_DATA … #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG2_VPG_MPEG_INFO0 … #define regVPG2_VPG_MPEG_INFO0_BASE_IDX … #define regVPG2_VPG_MPEG_INFO1 … #define regVPG2_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_dio_dig3_dme_dme_dispdec // base address: 0x162f4 #define regDME3_DME_CONTROL … #define regDME3_DME_CONTROL_BASE_IDX … #define regDME3_DME_MEMORY_CONTROL … #define regDME3_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dio_dig3_vpg_vpg_dispdec // base address: 0x16250 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG3_VPG_GENERIC_PACKET_DATA … #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG3_VPG_GENERIC_STATUS … #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG3_VPG_MEM_PWR … #define regVPG3_VPG_MEM_PWR_BASE_IDX … #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG3_VPG_ISRC1_2_DATA … #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG3_VPG_MPEG_INFO0 … #define regVPG3_VPG_MPEG_INFO0_BASE_IDX … #define regVPG3_VPG_MPEG_INFO1 … #define regVPG3_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_dio_hdcp1kp_dispdec // base address: 0x14cd8 // addressBlock: dcn_dcec_dio_dout_i2c_dispdec // base address: 0x0 #define regDC_I2C_CONTROL … #define regDC_I2C_CONTROL_BASE_IDX … #define regDC_I2C_ARBITRATION … #define regDC_I2C_ARBITRATION_BASE_IDX … #define regDC_I2C_INTERRUPT_CONTROL … #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define regDC_I2C_SW_STATUS … #define regDC_I2C_SW_STATUS_BASE_IDX … #define regDC_I2C_DDC1_HW_STATUS … #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC2_HW_STATUS … #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC3_HW_STATUS … #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC4_HW_STATUS … #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC5_HW_STATUS … #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC6_HW_STATUS … #define regDC_I2C_DDC6_HW_STATUS_BASE_IDX … #define regDC_I2C_DDC1_SPEED … #define regDC_I2C_DDC1_SPEED_BASE_IDX … #define regDC_I2C_DDC1_SETUP … #define regDC_I2C_DDC1_SETUP_BASE_IDX … #define regDC_I2C_DDC2_SPEED … #define regDC_I2C_DDC2_SPEED_BASE_IDX … #define regDC_I2C_DDC2_SETUP … #define regDC_I2C_DDC2_SETUP_BASE_IDX … #define regDC_I2C_DDC3_SPEED … #define regDC_I2C_DDC3_SPEED_BASE_IDX … #define regDC_I2C_DDC3_SETUP … #define regDC_I2C_DDC3_SETUP_BASE_IDX … #define regDC_I2C_DDC4_SPEED … #define regDC_I2C_DDC4_SPEED_BASE_IDX … #define regDC_I2C_DDC4_SETUP … #define regDC_I2C_DDC4_SETUP_BASE_IDX … #define regDC_I2C_DDC5_SPEED … #define regDC_I2C_DDC5_SPEED_BASE_IDX … #define regDC_I2C_DDC5_SETUP … #define regDC_I2C_DDC5_SETUP_BASE_IDX … #define regDC_I2C_DDC6_SPEED … #define regDC_I2C_DDC6_SPEED_BASE_IDX … #define regDC_I2C_DDC6_SETUP … #define regDC_I2C_DDC6_SETUP_BASE_IDX … #define regDC_I2C_TRANSACTION0 … #define regDC_I2C_TRANSACTION0_BASE_IDX … #define regDC_I2C_TRANSACTION1 … #define regDC_I2C_TRANSACTION1_BASE_IDX … #define regDC_I2C_TRANSACTION2 … #define regDC_I2C_TRANSACTION2_BASE_IDX … #define regDC_I2C_TRANSACTION3 … #define regDC_I2C_TRANSACTION3_BASE_IDX … #define regDC_I2C_DATA … #define regDC_I2C_DATA_BASE_IDX … #define regDC_I2C_DDCVGA_HW_STATUS … #define regDC_I2C_DDCVGA_HW_STATUS_BASE_IDX … #define regDC_I2C_DDCVGA_SPEED … #define regDC_I2C_DDCVGA_SPEED_BASE_IDX … #define regDC_I2C_DDCVGA_SETUP … #define regDC_I2C_DDCVGA_SETUP_BASE_IDX … #define regDC_I2C_EDID_DETECT_CTRL … #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX … #define regDC_I2C_READ_REQUEST_INTERRUPT … #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX … // addressBlock: dcn_dcec_dio_dio_misc_dispdec // base address: 0x0 #define regDIO_DCN_STATUS … #define regDIO_DCN_STATUS_BASE_IDX … #define regDIO_SCRATCH0 … #define regDIO_SCRATCH0_BASE_IDX … #define regDIO_SCRATCH1 … #define regDIO_SCRATCH1_BASE_IDX … #define regDIO_SCRATCH2 … #define regDIO_SCRATCH2_BASE_IDX … #define regDIO_SCRATCH3 … #define regDIO_SCRATCH3_BASE_IDX … #define regDIO_SCRATCH4 … #define regDIO_SCRATCH4_BASE_IDX … #define regDIO_SCRATCH5 … #define regDIO_SCRATCH5_BASE_IDX … #define regDIO_SCRATCH6 … #define regDIO_SCRATCH6_BASE_IDX … #define regDIO_SCRATCH7 … #define regDIO_SCRATCH7_BASE_IDX … #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS … #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX … #define regDIO_MEM_PWR_STATUS … #define regDIO_MEM_PWR_STATUS_BASE_IDX … #define regDIO_MEM_PWR_CTRL … #define regDIO_MEM_PWR_CTRL_BASE_IDX … #define regDIO_MEM_PWR_CTRL2 … #define regDIO_MEM_PWR_CTRL2_BASE_IDX … #define regDIO_CLK_CNTL … #define regDIO_CLK_CNTL_BASE_IDX … #define regDIO_POWER_MANAGEMENT_CNTL … #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX … #define regDIO_STEREOSYNC_SEL … #define regDIO_STEREOSYNC_SEL_BASE_IDX … #define regDIO_SOFT_RESET … #define regDIO_SOFT_RESET_BASE_IDX … #define regHDCP_CLK_STATUS … #define regHDCP_CLK_STATUS_BASE_IDX … #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL … #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX … #define regDIO_PSP_INTERRUPT_STATUS … #define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX … #define regDIO_PSP_INTERRUPT_CLEAR … #define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX … #define regDIO_STATUS … #define regDIO_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dio_dig_stream_mapper_dispdec // base address: 0x0 #define regDIG0_STREAM_MAPPER_CONTROL … #define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG1_STREAM_MAPPER_CONTROL … #define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG2_STREAM_MAPPER_CONTROL … #define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG3_STREAM_MAPPER_CONTROL … #define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG4_STREAM_MAPPER_CONTROL … #define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG5_STREAM_MAPPER_CONTROL … #define regDIG5_STREAM_MAPPER_CONTROL_BASE_IDX … #define regDIG6_STREAM_MAPPER_CONTROL … #define regDIG6_STREAM_MAPPER_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_dispdec // base address: 0x0 #define regDC_GENERICA … #define regDC_GENERICA_BASE_IDX … #define regDC_GENERICB … #define regDC_GENERICB_BASE_IDX … #define regDCIO_CLOCK_CNTL … #define regDCIO_CLOCK_CNTL_BASE_IDX … #define regDC_REF_CLK_CNTL … #define regDC_REF_CLK_CNTL_BASE_IDX … #define regUNIPHYA_LINK_CNTL … #define regUNIPHYA_LINK_CNTL_BASE_IDX … #define regUNIPHYA_CHANNEL_XBAR_CNTL … #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYB_LINK_CNTL … #define regUNIPHYB_LINK_CNTL_BASE_IDX … #define regUNIPHYB_CHANNEL_XBAR_CNTL … #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYC_LINK_CNTL … #define regUNIPHYC_LINK_CNTL_BASE_IDX … #define regUNIPHYC_CHANNEL_XBAR_CNTL … #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYD_LINK_CNTL … #define regUNIPHYD_LINK_CNTL_BASE_IDX … #define regUNIPHYD_CHANNEL_XBAR_CNTL … #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYE_LINK_CNTL … #define regUNIPHYE_LINK_CNTL_BASE_IDX … #define regUNIPHYE_CHANNEL_XBAR_CNTL … #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYF_LINK_CNTL … #define regUNIPHYF_LINK_CNTL_BASE_IDX … #define regUNIPHYF_CHANNEL_XBAR_CNTL … #define regUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX … #define regUNIPHYG_LINK_CNTL … #define regUNIPHYG_LINK_CNTL_BASE_IDX … #define regUNIPHYG_CHANNEL_XBAR_CNTL … #define regUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX … #define regDCIO_WRCMD_DELAY … #define regDCIO_WRCMD_DELAY_BASE_IDX … #define regDC_PINSTRAPS … #define regDC_PINSTRAPS_BASE_IDX … #define regCC_DC_MISC_STRAPS … #define regCC_DC_MISC_STRAPS_BASE_IDX … #define regDCIO_SPARE … #define regDCIO_SPARE_BASE_IDX … #define regINTERCEPT_STATE … #define regINTERCEPT_STATE_BASE_IDX … #define regDCIO_PATTERN_GEN_PAT … #define regDCIO_PATTERN_GEN_PAT_BASE_IDX … #define regDCIO_PATTERN_GEN_EN … #define regDCIO_PATTERN_GEN_EN_BASE_IDX … #define regDCIO_BL_PWM_FRAME_START_DISP_SEL … #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … #define regDCIO_GSL_GENLK_PAD_CNTL … #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX … #define regDCIO_GSL_SWAPLOCK_PAD_CNTL … #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX … #define regDBG_OUT_CNTL … #define regDBG_OUT_CNTL_BASE_IDX … #define regDCIO_SOFT_RESET … #define regDCIO_SOFT_RESET_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_chip_dispdec // base address: 0x0 #define regDC_GPIO_GENERIC_MASK … #define regDC_GPIO_GENERIC_MASK_BASE_IDX … #define regDC_GPIO_GENERIC_A … #define regDC_GPIO_GENERIC_A_BASE_IDX … #define regDC_GPIO_GENERIC_EN … #define regDC_GPIO_GENERIC_EN_BASE_IDX … #define regDC_GPIO_GENERIC_Y … #define regDC_GPIO_GENERIC_Y_BASE_IDX … #define regDC_GPIO_DDC1_MASK … #define regDC_GPIO_DDC1_MASK_BASE_IDX … #define regDC_GPIO_DDC1_A … #define regDC_GPIO_DDC1_A_BASE_IDX … #define regDC_GPIO_DDC1_EN … #define regDC_GPIO_DDC1_EN_BASE_IDX … #define regDC_GPIO_DDC1_Y … #define regDC_GPIO_DDC1_Y_BASE_IDX … #define regDC_GPIO_DDC2_MASK … #define regDC_GPIO_DDC2_MASK_BASE_IDX … #define regDC_GPIO_DDC2_A … #define regDC_GPIO_DDC2_A_BASE_IDX … #define regDC_GPIO_DDC2_EN … #define regDC_GPIO_DDC2_EN_BASE_IDX … #define regDC_GPIO_DDC2_Y … #define regDC_GPIO_DDC2_Y_BASE_IDX … #define regDC_GPIO_DDC3_MASK … #define regDC_GPIO_DDC3_MASK_BASE_IDX … #define regDC_GPIO_DDC3_A … #define regDC_GPIO_DDC3_A_BASE_IDX … #define regDC_GPIO_DDC3_EN … #define regDC_GPIO_DDC3_EN_BASE_IDX … #define regDC_GPIO_DDC3_Y … #define regDC_GPIO_DDC3_Y_BASE_IDX … #define regDC_GPIO_DDC4_MASK … #define regDC_GPIO_DDC4_MASK_BASE_IDX … #define regDC_GPIO_DDC4_A … #define regDC_GPIO_DDC4_A_BASE_IDX … #define regDC_GPIO_DDC4_EN … #define regDC_GPIO_DDC4_EN_BASE_IDX … #define regDC_GPIO_DDC4_Y … #define regDC_GPIO_DDC4_Y_BASE_IDX … #define regDC_GPIO_DDC5_MASK … #define regDC_GPIO_DDC5_MASK_BASE_IDX … #define regDC_GPIO_DDC5_A … #define regDC_GPIO_DDC5_A_BASE_IDX … #define regDC_GPIO_DDC5_EN … #define regDC_GPIO_DDC5_EN_BASE_IDX … #define regDC_GPIO_DDC5_Y … #define regDC_GPIO_DDC5_Y_BASE_IDX … #define regDC_GPIO_DDC6_MASK … #define regDC_GPIO_DDC6_MASK_BASE_IDX … #define regDC_GPIO_DDC6_A … #define regDC_GPIO_DDC6_A_BASE_IDX … #define regDC_GPIO_DDC6_EN … #define regDC_GPIO_DDC6_EN_BASE_IDX … #define regDC_GPIO_DDC6_Y … #define regDC_GPIO_DDC6_Y_BASE_IDX … #define regDC_GPIO_DDCVGA_MASK … #define regDC_GPIO_DDCVGA_MASK_BASE_IDX … #define regDC_GPIO_DDCVGA_A … #define regDC_GPIO_DDCVGA_A_BASE_IDX … #define regDC_GPIO_DDCVGA_EN … #define regDC_GPIO_DDCVGA_EN_BASE_IDX … #define regDC_GPIO_DDCVGA_Y … #define regDC_GPIO_DDCVGA_Y_BASE_IDX … #define regDC_GPIO_SYNCA_MASK … #define regDC_GPIO_SYNCA_MASK_BASE_IDX … #define regDC_GPIO_GENLK_MASK … #define regDC_GPIO_GENLK_MASK_BASE_IDX … #define regDC_GPIO_GENLK_A … #define regDC_GPIO_GENLK_A_BASE_IDX … #define regDC_GPIO_GENLK_EN … #define regDC_GPIO_GENLK_EN_BASE_IDX … #define regDC_GPIO_GENLK_Y … #define regDC_GPIO_GENLK_Y_BASE_IDX … #define regDC_GPIO_HPD_MASK … #define regDC_GPIO_HPD_MASK_BASE_IDX … #define regDC_GPIO_HPD_A … #define regDC_GPIO_HPD_A_BASE_IDX … #define regDC_GPIO_HPD_EN … #define regDC_GPIO_HPD_EN_BASE_IDX … #define regDC_GPIO_HPD_Y … #define regDC_GPIO_HPD_Y_BASE_IDX … #define regDC_GPIO_DRIVE_STRENGTH_S0 … #define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX … #define regDC_GPIO_DRIVE_STRENGTH_S1 … #define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX … #define regDC_GPIO_PWRSEQ0_EN … #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX … #define regDC_GPIO_PAD_STRENGTH_1 … #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX … #define regDC_GPIO_RESERVED … #define regDC_GPIO_RESERVED_BASE_IDX … #define regPHY_AUX_CNTL … #define regPHY_AUX_CNTL_BASE_IDX … #define regDC_GPIO_DRIVE_TXIMPSEL … #define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX … #define regDC_GPIO_PWRSEQ1_EN … #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX … #define regDC_GPIO_I2S_SPDIF_MASK … #define regDC_GPIO_I2S_SPDIF_MASK_BASE_IDX … #define regDC_GPIO_I2S_SPDIF_A … #define regDC_GPIO_I2S_SPDIF_A_BASE_IDX … #define regDC_GPIO_I2S_SPDIF_EN … #define regDC_GPIO_I2S_SPDIF_EN_BASE_IDX … #define regDC_GPIO_I2S_SPDIF_Y … #define regDC_GPIO_I2S_SPDIF_Y_BASE_IDX … #define regDC_GPIO_I2S_SPDIF_STRENGTH … #define regDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX … #define regDC_GPIO_TX12_EN … #define regDC_GPIO_TX12_EN_BASE_IDX … #define regDC_GPIO_AUX_CTRL_0 … #define regDC_GPIO_AUX_CTRL_0_BASE_IDX … #define regDC_GPIO_AUX_CTRL_1 … #define regDC_GPIO_AUX_CTRL_1_BASE_IDX … #define regDC_GPIO_RXEN … #define regDC_GPIO_RXEN_BASE_IDX … #define regDC_GPIO_PULLUPEN … #define regDC_GPIO_PULLUPEN_BASE_IDX … #define regDC_GPIO_AUX_CTRL_3 … #define regDC_GPIO_AUX_CTRL_3_BASE_IDX … #define regDC_GPIO_AUX_CTRL_4 … #define regDC_GPIO_AUX_CTRL_4_BASE_IDX … #define regDC_GPIO_AUX_CTRL_5 … #define regDC_GPIO_AUX_CTRL_5_BASE_IDX … #define regAUXI2C_PAD_ALL_PWR_OK … #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_uniphy0_dispdec // base address: 0x0 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 … #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_uniphy1_dispdec // base address: 0x360 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 … #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_uniphy2_dispdec // base address: 0x6c0 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 … #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … // addressBlock: dcn_dcec_dcio_dcio_uniphy3_dispdec // base address: 0xa20 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 … #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … // addressBlock: dcn_dcec_pwrseq0_dispdec_pwrseq_dispdec // base address: 0x0 #define regDC_GPIO_PWRSEQ_EN … #define regDC_GPIO_PWRSEQ_EN_BASE_IDX … #define regDC_GPIO_PWRSEQ_CTRL … #define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX … #define regDC_GPIO_PWRSEQ_MASK … #define regDC_GPIO_PWRSEQ_MASK_BASE_IDX … #define regDC_GPIO_PWRSEQ_A_Y … #define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX … #define regPANEL_PWRSEQ_CNTL … #define regPANEL_PWRSEQ_CNTL_BASE_IDX … #define regPANEL_PWRSEQ_STATE … #define regPANEL_PWRSEQ_STATE_BASE_IDX … #define regPANEL_PWRSEQ_DELAY1 … #define regPANEL_PWRSEQ_DELAY1_BASE_IDX … #define regPANEL_PWRSEQ_DELAY2 … #define regPANEL_PWRSEQ_DELAY2_BASE_IDX … #define regPANEL_PWRSEQ_REF_DIV1 … #define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX … #define regBL_PWM_CNTL … #define regBL_PWM_CNTL_BASE_IDX … #define regBL_PWM_CNTL2 … #define regBL_PWM_CNTL2_BASE_IDX … #define regBL_PWM_PERIOD_CNTL … #define regBL_PWM_PERIOD_CNTL_BASE_IDX … #define regBL_PWM_GRP1_REG_LOCK … #define regBL_PWM_GRP1_REG_LOCK_BASE_IDX … #define regPANEL_PWRSEQ_REF_DIV2 … #define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX … #define regPWRSEQ_DBG_SEL … #define regPWRSEQ_DBG_SEL_BASE_IDX … #define regPWRSEQ_SPARE … #define regPWRSEQ_SPARE_BASE_IDX … // addressBlock: dcn_dcec_dsc0_dispdec_dscc_dispdec // base address: 0x0 #define regDSCC0_DSCC_CONFIG0 … #define regDSCC0_DSCC_CONFIG0_BASE_IDX … #define regDSCC0_DSCC_CONFIG1 … #define regDSCC0_DSCC_CONFIG1_BASE_IDX … #define regDSCC0_DSCC_CONFIG2 … #define regDSCC0_DSCC_CONFIG2_BASE_IDX … #define regDSCC0_DSCC_STATUS … #define regDSCC0_DSCC_STATUS_BASE_IDX … #define regDSCC0_DSCC_INTERRUPT_CONTROL0 … #define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX … #define regDSCC0_DSCC_INTERRUPT_CONTROL1 … #define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX … #define regDSCC0_DSCC_INTERRUPT_STATUS0 … #define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX … #define regDSCC0_DSCC_INTERRUPT_STATUS1 … #define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG0 … #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG1 … #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG2 … #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG3 … #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG4 … #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG5 … #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG6 … #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG7 … #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG8 … #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG9 … #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG10 … #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG11 … #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG12 … #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG13 … #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG14 … #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG15 … #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG16 … #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG17 … #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG18 … #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG19 … #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG20 … #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG21 … #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX … #define regDSCC0_DSCC_PPS_CONFIG22 … #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX … #define regDSCC0_DSCC_MEM_POWER_CONTROL0 … #define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX … #define regDSCC0_DSCC_MEM_POWER_CONTROL1 … #define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX … #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER … #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER … #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER … #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER … #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER … #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER … #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC0_DSCC_MAX_ABS_ERROR0 … #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX … #define regDSCC0_DSCC_MAX_ABS_ERROR1 … #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 … #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 … #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_INDEX0 … #define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_INDEX1 … #define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_INDEX2 … #define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_INDEX3 … #define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE … #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_DATA0 … #define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_DATA1 … #define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_DATA2 … #define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX … #define regDSCC0_DSCC_TEST_DEBUG_DATA3 … #define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX … #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 … #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 … #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX … // addressBlock: dcn_dcec_dsc0_dispdec_dsccif_dispdec // base address: 0x0 #define regDSCCIF0_DSCCIF_CONFIG0 … #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX … // addressBlock: dcn_dcec_dsc0_dispdec_dsc_top_dispdec // base address: 0x0 #define regDSC_TOP0_DSC_TOP_CONTROL … #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX … #define regDSC_TOP0_DSC_DEBUG_CONTROL … #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX … #define regDSC_TOP0_DSC_SPARE_DEBUG … #define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX … #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX … #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX … #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA … #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dsc1_dispdec_dscc_dispdec // base address: 0x170 #define regDSCC1_DSCC_CONFIG0 … #define regDSCC1_DSCC_CONFIG0_BASE_IDX … #define regDSCC1_DSCC_CONFIG1 … #define regDSCC1_DSCC_CONFIG1_BASE_IDX … #define regDSCC1_DSCC_CONFIG2 … #define regDSCC1_DSCC_CONFIG2_BASE_IDX … #define regDSCC1_DSCC_STATUS … #define regDSCC1_DSCC_STATUS_BASE_IDX … #define regDSCC1_DSCC_INTERRUPT_CONTROL0 … #define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX … #define regDSCC1_DSCC_INTERRUPT_CONTROL1 … #define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX … #define regDSCC1_DSCC_INTERRUPT_STATUS0 … #define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX … #define regDSCC1_DSCC_INTERRUPT_STATUS1 … #define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG0 … #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG1 … #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG2 … #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG3 … #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG4 … #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG5 … #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG6 … #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG7 … #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG8 … #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG9 … #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG10 … #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG11 … #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG12 … #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG13 … #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG14 … #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG15 … #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG16 … #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG17 … #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG18 … #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG19 … #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG20 … #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG21 … #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX … #define regDSCC1_DSCC_PPS_CONFIG22 … #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX … #define regDSCC1_DSCC_MEM_POWER_CONTROL0 … #define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX … #define regDSCC1_DSCC_MEM_POWER_CONTROL1 … #define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX … #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER … #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER … #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER … #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER … #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER … #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER … #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC1_DSCC_MAX_ABS_ERROR0 … #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX … #define regDSCC1_DSCC_MAX_ABS_ERROR1 … #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 … #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 … #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_INDEX0 … #define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_INDEX1 … #define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_INDEX2 … #define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_INDEX3 … #define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE … #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_DATA0 … #define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_DATA1 … #define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_DATA2 … #define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX … #define regDSCC1_DSCC_TEST_DEBUG_DATA3 … #define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX … #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 … #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 … #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX … // addressBlock: dcn_dcec_dsc1_dispdec_dsccif_dispdec // base address: 0x170 #define regDSCCIF1_DSCCIF_CONFIG0 … #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX … // addressBlock: dcn_dcec_dsc1_dispdec_dsc_top_dispdec // base address: 0x170 #define regDSC_TOP1_DSC_TOP_CONTROL … #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX … #define regDSC_TOP1_DSC_DEBUG_CONTROL … #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX … #define regDSC_TOP1_DSC_SPARE_DEBUG … #define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX … #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX … #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX … #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA … #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dsc2_dispdec_dscc_dispdec // base address: 0x2e0 #define regDSCC2_DSCC_CONFIG0 … #define regDSCC2_DSCC_CONFIG0_BASE_IDX … #define regDSCC2_DSCC_CONFIG1 … #define regDSCC2_DSCC_CONFIG1_BASE_IDX … #define regDSCC2_DSCC_CONFIG2 … #define regDSCC2_DSCC_CONFIG2_BASE_IDX … #define regDSCC2_DSCC_STATUS … #define regDSCC2_DSCC_STATUS_BASE_IDX … #define regDSCC2_DSCC_INTERRUPT_CONTROL0 … #define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX … #define regDSCC2_DSCC_INTERRUPT_CONTROL1 … #define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX … #define regDSCC2_DSCC_INTERRUPT_STATUS0 … #define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX … #define regDSCC2_DSCC_INTERRUPT_STATUS1 … #define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG0 … #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG1 … #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG2 … #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG3 … #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG4 … #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG5 … #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG6 … #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG7 … #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG8 … #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG9 … #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG10 … #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG11 … #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG12 … #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG13 … #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG14 … #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG15 … #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG16 … #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG17 … #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG18 … #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG19 … #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG20 … #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG21 … #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX … #define regDSCC2_DSCC_PPS_CONFIG22 … #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX … #define regDSCC2_DSCC_MEM_POWER_CONTROL0 … #define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX … #define regDSCC2_DSCC_MEM_POWER_CONTROL1 … #define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX … #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER … #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER … #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER … #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER … #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER … #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER … #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC2_DSCC_MAX_ABS_ERROR0 … #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX … #define regDSCC2_DSCC_MAX_ABS_ERROR1 … #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 … #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 … #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_INDEX0 … #define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_INDEX1 … #define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_INDEX2 … #define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_INDEX3 … #define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE … #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_DATA0 … #define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_DATA1 … #define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_DATA2 … #define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX … #define regDSCC2_DSCC_TEST_DEBUG_DATA3 … #define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX … #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 … #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 … #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX … // addressBlock: dcn_dcec_dsc2_dispdec_dsccif_dispdec // base address: 0x2e0 #define regDSCCIF2_DSCCIF_CONFIG0 … #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX … // addressBlock: dcn_dcec_dsc2_dispdec_dsc_top_dispdec // base address: 0x2e0 #define regDSC_TOP2_DSC_TOP_CONTROL … #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX … #define regDSC_TOP2_DSC_DEBUG_CONTROL … #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX … #define regDSC_TOP2_DSC_SPARE_DEBUG … #define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX … #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX … #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX … #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA … #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dsc3_dispdec_dscc_dispdec // base address: 0x450 #define regDSCC3_DSCC_CONFIG0 … #define regDSCC3_DSCC_CONFIG0_BASE_IDX … #define regDSCC3_DSCC_CONFIG1 … #define regDSCC3_DSCC_CONFIG1_BASE_IDX … #define regDSCC3_DSCC_CONFIG2 … #define regDSCC3_DSCC_CONFIG2_BASE_IDX … #define regDSCC3_DSCC_STATUS … #define regDSCC3_DSCC_STATUS_BASE_IDX … #define regDSCC3_DSCC_INTERRUPT_CONTROL0 … #define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX … #define regDSCC3_DSCC_INTERRUPT_CONTROL1 … #define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX … #define regDSCC3_DSCC_INTERRUPT_STATUS0 … #define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX … #define regDSCC3_DSCC_INTERRUPT_STATUS1 … #define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG0 … #define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG1 … #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG2 … #define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG3 … #define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG4 … #define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG5 … #define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG6 … #define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG7 … #define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG8 … #define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG9 … #define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG10 … #define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG11 … #define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG12 … #define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG13 … #define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG14 … #define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG15 … #define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG16 … #define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG17 … #define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG18 … #define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG19 … #define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG20 … #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG21 … #define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX … #define regDSCC3_DSCC_PPS_CONFIG22 … #define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX … #define regDSCC3_DSCC_MEM_POWER_CONTROL0 … #define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX … #define regDSCC3_DSCC_MEM_POWER_CONTROL1 … #define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX … #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER … #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER … #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER … #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER … #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER … #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX … #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER … #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX … #define regDSCC3_DSCC_MAX_ABS_ERROR0 … #define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX … #define regDSCC3_DSCC_MAX_ABS_ERROR1 … #define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 … #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 … #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_INDEX0 … #define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_INDEX1 … #define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_INDEX2 … #define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_INDEX3 … #define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE … #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_DATA0 … #define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_DATA1 … #define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_DATA2 … #define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX … #define regDSCC3_DSCC_TEST_DEBUG_DATA3 … #define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX … #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 … #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX … #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 … #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX … // addressBlock: dcn_dcec_dsc3_dispdec_dsccif_dispdec // base address: 0x450 #define regDSCCIF3_DSCCIF_CONFIG0 … #define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX … // addressBlock: dcn_dcec_dsc3_dispdec_dsc_top_dispdec // base address: 0x450 #define regDSC_TOP3_DSC_TOP_CONTROL … #define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX … #define regDSC_TOP3_DSC_DEBUG_CONTROL … #define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX … #define regDSC_TOP3_DSC_SPARE_DEBUG … #define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX … #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX … #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX … #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA … #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dcn_dcec_dcoh_dcoh_top_dispdec // base address: 0x0 #define regDCOH_TOP_CLOCK_CONTROL … #define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX … #define regDCOH_TOP_SPARE … #define regDCOH_TOP_SPARE_BASE_IDX … // addressBlock: dcn_dcec_dcoh_phy_mux0_dispdec // base address: 0x13168 #define regPHY_MUX0_PHY_MUX_CONTROL … #define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX … #define regPHY_MUX0_PORT_TYPE … #define regPHY_MUX0_PORT_TYPE_BASE_IDX … // addressBlock: dcn_dcec_dcoh_phy_mux1_dispdec // base address: 0x13174 #define regPHY_MUX1_PHY_MUX_CONTROL … #define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX … #define regPHY_MUX1_PORT_TYPE … #define regPHY_MUX1_PORT_TYPE_BASE_IDX … // addressBlock: dcn_dcec_dcoh_phy_mux2_dispdec // base address: 0x13180 #define regPHY_MUX2_PHY_MUX_CONTROL … #define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX … #define regPHY_MUX2_PORT_TYPE … #define regPHY_MUX2_PORT_TYPE_BASE_IDX … // addressBlock: dcn_dcec_dcoh_phy_mux3_dispdec // base address: 0x1318c #define regPHY_MUX3_PHY_MUX_CONTROL … #define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX … #define regPHY_MUX3_PORT_TYPE … #define regPHY_MUX3_PORT_TYPE_BASE_IDX … // addressBlock: dcn_dcec_dcoh_dp_aux0_dispdec // base address: 0x0 #define regDP_AUX0_AUX_CONTROL … #define regDP_AUX0_AUX_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_SW_CONTROL … #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_ARB_CONTROL … #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_INTERRUPT_CONTROL … #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_SW_STATUS … #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX … #define regDP_AUX0_AUX_LS_STATUS … #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX … #define regDP_AUX0_AUX_SW_DATA … #define regDP_AUX0_AUX_SW_DATA_BASE_IDX … #define regDP_AUX0_AUX_LS_DATA … #define regDP_AUX0_AUX_LS_DATA_BASE_IDX … #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL … #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_DPHY_TX_CONTROL … #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX … #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 … #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 … #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define regDP_AUX0_AUX_DPHY_TX_STATUS … #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX … #define regDP_AUX0_AUX_DPHY_RX_STATUS … #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX … #define regDP_AUX0_AUX_PHY_WAKE_CNTL … #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX … #define regDP_AUX0_AUX_PHY_WAKE_STATUS … #define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcoh_dp_aux1_dispdec // base address: 0x70 #define regDP_AUX1_AUX_CONTROL … #define regDP_AUX1_AUX_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_SW_CONTROL … #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_ARB_CONTROL … #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_INTERRUPT_CONTROL … #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_SW_STATUS … #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX … #define regDP_AUX1_AUX_LS_STATUS … #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX … #define regDP_AUX1_AUX_SW_DATA … #define regDP_AUX1_AUX_SW_DATA_BASE_IDX … #define regDP_AUX1_AUX_LS_DATA … #define regDP_AUX1_AUX_LS_DATA_BASE_IDX … #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL … #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_DPHY_TX_CONTROL … #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX … #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 … #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 … #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define regDP_AUX1_AUX_DPHY_TX_STATUS … #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX … #define regDP_AUX1_AUX_DPHY_RX_STATUS … #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX … #define regDP_AUX1_AUX_PHY_WAKE_CNTL … #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX … #define regDP_AUX1_AUX_PHY_WAKE_STATUS … #define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcoh_dp_aux2_dispdec // base address: 0xe0 #define regDP_AUX2_AUX_CONTROL … #define regDP_AUX2_AUX_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_SW_CONTROL … #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_ARB_CONTROL … #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_INTERRUPT_CONTROL … #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_SW_STATUS … #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX … #define regDP_AUX2_AUX_LS_STATUS … #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX … #define regDP_AUX2_AUX_SW_DATA … #define regDP_AUX2_AUX_SW_DATA_BASE_IDX … #define regDP_AUX2_AUX_LS_DATA … #define regDP_AUX2_AUX_LS_DATA_BASE_IDX … #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL … #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_DPHY_TX_CONTROL … #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX … #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 … #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 … #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define regDP_AUX2_AUX_DPHY_TX_STATUS … #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX … #define regDP_AUX2_AUX_DPHY_RX_STATUS … #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX … #define regDP_AUX2_AUX_PHY_WAKE_CNTL … #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX … #define regDP_AUX2_AUX_PHY_WAKE_STATUS … #define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcoh_dp_aux3_dispdec // base address: 0x150 #define regDP_AUX3_AUX_CONTROL … #define regDP_AUX3_AUX_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_SW_CONTROL … #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_ARB_CONTROL … #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_INTERRUPT_CONTROL … #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_SW_STATUS … #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX … #define regDP_AUX3_AUX_LS_STATUS … #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX … #define regDP_AUX3_AUX_SW_DATA … #define regDP_AUX3_AUX_SW_DATA_BASE_IDX … #define regDP_AUX3_AUX_LS_DATA … #define regDP_AUX3_AUX_LS_DATA_BASE_IDX … #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL … #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_DPHY_TX_CONTROL … #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX … #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 … #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 … #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define regDP_AUX3_AUX_DPHY_TX_STATUS … #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX … #define regDP_AUX3_AUX_DPHY_RX_STATUS … #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX … #define regDP_AUX3_AUX_PHY_WAKE_CNTL … #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX … #define regDP_AUX3_AUX_PHY_WAKE_STATUS … #define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX … // addressBlock: dcn_dcec_dcoh_hpd0_dispdec // base address: 0x0 #define regHPD0_DC_HPD_INT_STATUS … #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX … #define regHPD0_DC_HPD_INT_CONTROL … #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX … #define regHPD0_DC_HPD_CONTROL … #define regHPD0_DC_HPD_CONTROL_BASE_IDX … #define regHPD0_DC_HPD_FAST_TRAIN_CNTL … #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL … #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dcoh_hpd1_dispdec // base address: 0x20 #define regHPD1_DC_HPD_INT_STATUS … #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX … #define regHPD1_DC_HPD_INT_CONTROL … #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX … #define regHPD1_DC_HPD_CONTROL … #define regHPD1_DC_HPD_CONTROL_BASE_IDX … #define regHPD1_DC_HPD_FAST_TRAIN_CNTL … #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL … #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dcoh_hpd2_dispdec // base address: 0x40 #define regHPD2_DC_HPD_INT_STATUS … #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX … #define regHPD2_DC_HPD_INT_CONTROL … #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX … #define regHPD2_DC_HPD_CONTROL … #define regHPD2_DC_HPD_CONTROL_BASE_IDX … #define regHPD2_DC_HPD_FAST_TRAIN_CNTL … #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL … #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dcn_dcec_dcoh_hpd3_dispdec // base address: 0x60 #define regHPD3_DC_HPD_INT_STATUS … #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX … #define regHPD3_DC_HPD_INT_CONTROL … #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX … #define regHPD3_DC_HPD_CONTROL … #define regHPD3_DC_HPD_CONTROL_BASE_IDX … #define regHPD3_DC_HPD_FAST_TRAIN_CNTL … #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL … #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dcn_dcec_hpo_hpo_top_dispdec // base address: 0x2790c #define regHPO_TOP_CLOCK_CONTROL … #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX … #define regHPO_TOP_HW_CONTROL … #define regHPO_TOP_HW_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_mapper_dispdec // base address: 0x27958 #define regDP_STREAM_MAPPER_CONTROL0 … #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX … #define regDP_STREAM_MAPPER_CONTROL1 … #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX … #define regDP_STREAM_MAPPER_CONTROL2 … #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX … #define regDP_STREAM_MAPPER_CONTROL3 … #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX … #define regDP_STREAM_MAPPER_CONTROL4 … #define regDP_STREAM_MAPPER_CONTROL4_BASE_IDX … #define regDP_STREAM_MAPPER_CONTROL5 … #define regDP_STREAM_MAPPER_CONTROL5_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec // base address: 0x2656c #define regHDMI_LINK_ENC_CONTROL … #define regHDMI_LINK_ENC_CONTROL_BASE_IDX … #define regHDMI_LINK_ENC_CLK_CTRL … #define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec // base address: 0x26594 #define regHDMI_FRL_ENC_CONFIG … #define regHDMI_FRL_ENC_CONFIG_BASE_IDX … #define regHDMI_FRL_ENC_CONFIG2 … #define regHDMI_FRL_ENC_CONFIG2_BASE_IDX … #define regHDMI_FRL_ENC_METER_BUFFER_STATUS … #define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX … #define regHDMI_FRL_ENC_MEM_CTRL … #define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec // base address: 0x2634c #define regHDMI_STREAM_ENC_CLOCK_CONTROL … #define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX … #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL … #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 … #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c #define regAFMT4_AFMT_ACP … #define regAFMT4_AFMT_ACP_BASE_IDX … #define regAFMT4_AFMT_VBI_PACKET_CONTROL … #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 … #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define regAFMT4_AFMT_AUDIO_INFO0 … #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX … #define regAFMT4_AFMT_AUDIO_INFO1 … #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX … #define regAFMT4_AFMT_60958_0 … #define regAFMT4_AFMT_60958_0_BASE_IDX … #define regAFMT4_AFMT_60958_1 … #define regAFMT4_AFMT_60958_1_BASE_IDX … #define regAFMT4_AFMT_AUDIO_CRC_CONTROL … #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define regAFMT4_AFMT_RAMP_CONTROL0 … #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX … #define regAFMT4_AFMT_RAMP_CONTROL1 … #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX … #define regAFMT4_AFMT_RAMP_CONTROL2 … #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX … #define regAFMT4_AFMT_RAMP_CONTROL3 … #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX … #define regAFMT4_AFMT_60958_2 … #define regAFMT4_AFMT_60958_2_BASE_IDX … #define regAFMT4_AFMT_AUDIO_CRC_RESULT … #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define regAFMT4_AFMT_STATUS … #define regAFMT4_AFMT_STATUS_BASE_IDX … #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL … #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define regAFMT4_AFMT_INFOFRAME_CONTROL0 … #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define regAFMT4_AFMT_INTERRUPT_STATUS … #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX … #define regAFMT4_AFMT_AUDIO_SRC_CONTROL … #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL … #define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX … #define regAFMT4_AFMT_MEM_PWR … #define regAFMT4_AFMT_MEM_PWR_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dme_dme_dispdec // base address: 0x264f0 #define regDME4_DME_CONTROL … #define regDME4_DME_CONTROL_BASE_IDX … #define regDME4_DME_MEMORY_CONTROL … #define regDME4_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_vpg_vpg_dispdec // base address: 0x264c4 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG4_VPG_GENERIC_PACKET_DATA … #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG4_VPG_GENERIC_STATUS … #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG4_VPG_MEM_PWR … #define regVPG4_VPG_MEM_PWR_BASE_IDX … #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG4_VPG_ISRC1_2_DATA … #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG4_VPG_MPEG_INFO0 … #define regVPG4_VPG_MPEG_INFO0_BASE_IDX … #define regVPG4_VPG_MPEG_INFO1 … #define regVPG4_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec // base address: 0x2637c #define regHDMI_TB_ENC_CONTROL … #define regHDMI_TB_ENC_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_PIXEL_FORMAT … #define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX … #define regHDMI_TB_ENC_PACKET_CONTROL … #define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_ACR_PACKET_CONTROL … #define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 … #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX … #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 … #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX … #define regHDMI_TB_ENC_GC_CONTROL … #define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 … #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX … #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE … #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX … #define regHDMI_TB_ENC_DB_CONTROL … #define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_ACR_32_0 … #define regHDMI_TB_ENC_ACR_32_0_BASE_IDX … #define regHDMI_TB_ENC_ACR_32_1 … #define regHDMI_TB_ENC_ACR_32_1_BASE_IDX … #define regHDMI_TB_ENC_ACR_44_0 … #define regHDMI_TB_ENC_ACR_44_0_BASE_IDX … #define regHDMI_TB_ENC_ACR_44_1 … #define regHDMI_TB_ENC_ACR_44_1_BASE_IDX … #define regHDMI_TB_ENC_ACR_48_0 … #define regHDMI_TB_ENC_ACR_48_0_BASE_IDX … #define regHDMI_TB_ENC_ACR_48_1 … #define regHDMI_TB_ENC_ACR_48_1_BASE_IDX … #define regHDMI_TB_ENC_ACR_STATUS_0 … #define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX … #define regHDMI_TB_ENC_ACR_STATUS_1 … #define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX … #define regHDMI_TB_ENC_BUFFER_CONTROL … #define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_MEM_CTRL … #define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX … #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL … #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_H_ACTIVE_BLANK … #define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX … #define regHDMI_TB_ENC_HC_ACTIVE_BLANK … #define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX … #define regHDMI_TB_ENC_CRC_CNTL … #define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX … #define regHDMI_TB_ENC_CRC_RESULT_0 … #define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX … #define regHDMI_TB_ENC_ENCRYPTION_CONTROL … #define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX … #define regHDMI_TB_ENC_MODE … #define regHDMI_TB_ENC_MODE_BASE_IDX … #define regHDMI_TB_ENC_INPUT_FIFO_STATUS … #define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX … #define regHDMI_TB_ENC_CRC_RESULT_1 … #define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL … #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL … #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX … #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL … #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX … #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 … #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX … #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 … #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX … #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE … #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc0_apg_apg_dispdec // base address: 0x1abc0 #define regAPG0_APG_CONTROL … #define regAPG0_APG_CONTROL_BASE_IDX … #define regAPG0_APG_CONTROL2 … #define regAPG0_APG_CONTROL2_BASE_IDX … #define regAPG0_APG_DBG_GEN_CONTROL … #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX … #define regAPG0_APG_PACKET_CONTROL … #define regAPG0_APG_PACKET_CONTROL_BASE_IDX … #define regAPG0_APG_DBG_ACP … #define regAPG0_APG_DBG_ACP_BASE_IDX … #define regAPG0_APG_AUDIO_INFO … #define regAPG0_APG_AUDIO_INFO_BASE_IDX … #define regAPG0_APG_DBG_AUDIO_INFO … #define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX … #define regAPG0_APG_DBG_60958_0 … #define regAPG0_APG_DBG_60958_0_BASE_IDX … #define regAPG0_APG_DBG_60958_1 … #define regAPG0_APG_DBG_60958_1_BASE_IDX … #define regAPG0_APG_DBG_60958_2 … #define regAPG0_APG_DBG_60958_2_BASE_IDX … #define regAPG0_APG_AUDIO_CRC_CONTROL … #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX … #define regAPG0_APG_AUDIO_CRC_CONTROL2 … #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX … #define regAPG0_APG_AUDIO_CRC_RESULT … #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX … #define regAPG0_APG_DBG_RAMP_CONTROL0 … #define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX … #define regAPG0_APG_DBG_RAMP_CONTROL1 … #define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX … #define regAPG0_APG_DBG_RAMP_CONTROL2 … #define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX … #define regAPG0_APG_DBG_RAMP_CONTROL3 … #define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX … #define regAPG0_APG_STATUS … #define regAPG0_APG_STATUS_BASE_IDX … #define regAPG0_APG_STATUS2 … #define regAPG0_APG_STATUS2_BASE_IDX … #define regAPG0_APG_DBG_AUDIO_DTO_CNTL … #define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX … #define regAPG0_APG_MEM_PWR … #define regAPG0_APG_MEM_PWR_BASE_IDX … #define regAPG0_APG_SPARE … #define regAPG0_APG_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc0_dme_dme_dispdec // base address: 0x1ac38 #define regDME5_DME_CONTROL … #define regDME5_DME_CONTROL_BASE_IDX … #define regDME5_DME_MEMORY_CONTROL … #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc0_vpg_vpg_dispdec // base address: 0x1ac44 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG5_VPG_GENERIC_PACKET_DATA … #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG5_VPG_GENERIC_STATUS … #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG5_VPG_MEM_PWR … #define regVPG5_VPG_MEM_PWR_BASE_IDX … #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG5_VPG_ISRC1_2_DATA … #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG5_VPG_MPEG_INFO0 … #define regVPG5_VPG_MPEG_INFO0_BASE_IDX … #define regVPG5_VPG_MPEG_INFO1 … #define regVPG5_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_sym32_enc0_dispdec // base address: 0x1ac74 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS … #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS … #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL … #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE … #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc1_dispdec // base address: 0x1aedc #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL … #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL … #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX … #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL … #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX … #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 … #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX … #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 … #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX … #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE … #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc1_apg_apg_dispdec // base address: 0x1af10 #define regAPG1_APG_CONTROL … #define regAPG1_APG_CONTROL_BASE_IDX … #define regAPG1_APG_CONTROL2 … #define regAPG1_APG_CONTROL2_BASE_IDX … #define regAPG1_APG_DBG_GEN_CONTROL … #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX … #define regAPG1_APG_PACKET_CONTROL … #define regAPG1_APG_PACKET_CONTROL_BASE_IDX … #define regAPG1_APG_DBG_ACP … #define regAPG1_APG_DBG_ACP_BASE_IDX … #define regAPG1_APG_AUDIO_INFO … #define regAPG1_APG_AUDIO_INFO_BASE_IDX … #define regAPG1_APG_DBG_AUDIO_INFO … #define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX … #define regAPG1_APG_DBG_60958_0 … #define regAPG1_APG_DBG_60958_0_BASE_IDX … #define regAPG1_APG_DBG_60958_1 … #define regAPG1_APG_DBG_60958_1_BASE_IDX … #define regAPG1_APG_DBG_60958_2 … #define regAPG1_APG_DBG_60958_2_BASE_IDX … #define regAPG1_APG_AUDIO_CRC_CONTROL … #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX … #define regAPG1_APG_AUDIO_CRC_CONTROL2 … #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX … #define regAPG1_APG_AUDIO_CRC_RESULT … #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX … #define regAPG1_APG_DBG_RAMP_CONTROL0 … #define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX … #define regAPG1_APG_DBG_RAMP_CONTROL1 … #define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX … #define regAPG1_APG_DBG_RAMP_CONTROL2 … #define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX … #define regAPG1_APG_DBG_RAMP_CONTROL3 … #define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX … #define regAPG1_APG_STATUS … #define regAPG1_APG_STATUS_BASE_IDX … #define regAPG1_APG_STATUS2 … #define regAPG1_APG_STATUS2_BASE_IDX … #define regAPG1_APG_DBG_AUDIO_DTO_CNTL … #define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX … #define regAPG1_APG_MEM_PWR … #define regAPG1_APG_MEM_PWR_BASE_IDX … #define regAPG1_APG_SPARE … #define regAPG1_APG_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc1_dme_dme_dispdec // base address: 0x1af88 #define regDME6_DME_CONTROL … #define regDME6_DME_CONTROL_BASE_IDX … #define regDME6_DME_MEMORY_CONTROL … #define regDME6_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc1_vpg_vpg_dispdec // base address: 0x1af94 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG6_VPG_GENERIC_PACKET_DATA … #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG6_VPG_GENERIC_STATUS … #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG6_VPG_MEM_PWR … #define regVPG6_VPG_MEM_PWR_BASE_IDX … #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG6_VPG_ISRC1_2_DATA … #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG6_VPG_MPEG_INFO0 … #define regVPG6_VPG_MPEG_INFO0_BASE_IDX … #define regVPG6_VPG_MPEG_INFO1 … #define regVPG6_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_sym32_enc1_dispdec // base address: 0x1afc4 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS … #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS … #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL … #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE … #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc2_dispdec // base address: 0x1b22c #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL … #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL … #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX … #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL … #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX … #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 … #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX … #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 … #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX … #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE … #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc2_apg_apg_dispdec // base address: 0x1b260 #define regAPG2_APG_CONTROL … #define regAPG2_APG_CONTROL_BASE_IDX … #define regAPG2_APG_CONTROL2 … #define regAPG2_APG_CONTROL2_BASE_IDX … #define regAPG2_APG_DBG_GEN_CONTROL … #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX … #define regAPG2_APG_PACKET_CONTROL … #define regAPG2_APG_PACKET_CONTROL_BASE_IDX … #define regAPG2_APG_DBG_ACP … #define regAPG2_APG_DBG_ACP_BASE_IDX … #define regAPG2_APG_AUDIO_INFO … #define regAPG2_APG_AUDIO_INFO_BASE_IDX … #define regAPG2_APG_DBG_AUDIO_INFO … #define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX … #define regAPG2_APG_DBG_60958_0 … #define regAPG2_APG_DBG_60958_0_BASE_IDX … #define regAPG2_APG_DBG_60958_1 … #define regAPG2_APG_DBG_60958_1_BASE_IDX … #define regAPG2_APG_DBG_60958_2 … #define regAPG2_APG_DBG_60958_2_BASE_IDX … #define regAPG2_APG_AUDIO_CRC_CONTROL … #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX … #define regAPG2_APG_AUDIO_CRC_CONTROL2 … #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX … #define regAPG2_APG_AUDIO_CRC_RESULT … #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX … #define regAPG2_APG_DBG_RAMP_CONTROL0 … #define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX … #define regAPG2_APG_DBG_RAMP_CONTROL1 … #define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX … #define regAPG2_APG_DBG_RAMP_CONTROL2 … #define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX … #define regAPG2_APG_DBG_RAMP_CONTROL3 … #define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX … #define regAPG2_APG_STATUS … #define regAPG2_APG_STATUS_BASE_IDX … #define regAPG2_APG_STATUS2 … #define regAPG2_APG_STATUS2_BASE_IDX … #define regAPG2_APG_DBG_AUDIO_DTO_CNTL … #define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX … #define regAPG2_APG_MEM_PWR … #define regAPG2_APG_MEM_PWR_BASE_IDX … #define regAPG2_APG_SPARE … #define regAPG2_APG_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc2_dme_dme_dispdec // base address: 0x1b2d8 #define regDME7_DME_CONTROL … #define regDME7_DME_CONTROL_BASE_IDX … #define regDME7_DME_MEMORY_CONTROL … #define regDME7_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc2_vpg_vpg_dispdec // base address: 0x1b2e4 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG7_VPG_GENERIC_PACKET_DATA … #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG7_VPG_GENERIC_STATUS … #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG7_VPG_MEM_PWR … #define regVPG7_VPG_MEM_PWR_BASE_IDX … #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG7_VPG_ISRC1_2_DATA … #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG7_VPG_MPEG_INFO0 … #define regVPG7_VPG_MPEG_INFO0_BASE_IDX … #define regVPG7_VPG_MPEG_INFO1 … #define regVPG7_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_sym32_enc2_dispdec // base address: 0x1b314 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS … #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS … #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL … #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE … #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc3_dispdec // base address: 0x1b57c #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL … #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL … #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX … #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL … #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX … #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 … #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX … #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 … #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX … #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE … #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc3_apg_apg_dispdec // base address: 0x1b5b0 #define regAPG3_APG_CONTROL … #define regAPG3_APG_CONTROL_BASE_IDX … #define regAPG3_APG_CONTROL2 … #define regAPG3_APG_CONTROL2_BASE_IDX … #define regAPG3_APG_DBG_GEN_CONTROL … #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX … #define regAPG3_APG_PACKET_CONTROL … #define regAPG3_APG_PACKET_CONTROL_BASE_IDX … #define regAPG3_APG_DBG_ACP … #define regAPG3_APG_DBG_ACP_BASE_IDX … #define regAPG3_APG_AUDIO_INFO … #define regAPG3_APG_AUDIO_INFO_BASE_IDX … #define regAPG3_APG_DBG_AUDIO_INFO … #define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX … #define regAPG3_APG_DBG_60958_0 … #define regAPG3_APG_DBG_60958_0_BASE_IDX … #define regAPG3_APG_DBG_60958_1 … #define regAPG3_APG_DBG_60958_1_BASE_IDX … #define regAPG3_APG_DBG_60958_2 … #define regAPG3_APG_DBG_60958_2_BASE_IDX … #define regAPG3_APG_AUDIO_CRC_CONTROL … #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX … #define regAPG3_APG_AUDIO_CRC_CONTROL2 … #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX … #define regAPG3_APG_AUDIO_CRC_RESULT … #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX … #define regAPG3_APG_DBG_RAMP_CONTROL0 … #define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX … #define regAPG3_APG_DBG_RAMP_CONTROL1 … #define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX … #define regAPG3_APG_DBG_RAMP_CONTROL2 … #define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX … #define regAPG3_APG_DBG_RAMP_CONTROL3 … #define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX … #define regAPG3_APG_STATUS … #define regAPG3_APG_STATUS_BASE_IDX … #define regAPG3_APG_STATUS2 … #define regAPG3_APG_STATUS2_BASE_IDX … #define regAPG3_APG_DBG_AUDIO_DTO_CNTL … #define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX … #define regAPG3_APG_MEM_PWR … #define regAPG3_APG_MEM_PWR_BASE_IDX … #define regAPG3_APG_SPARE … #define regAPG3_APG_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc3_dme_dme_dispdec // base address: 0x1b628 #define regDME8_DME_CONTROL … #define regDME8_DME_CONTROL_BASE_IDX … #define regDME8_DME_MEMORY_CONTROL … #define regDME8_DME_MEMORY_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_stream_enc3_vpg_vpg_dispdec // base address: 0x1b634 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL … #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX … #define regVPG8_VPG_GENERIC_PACKET_DATA … #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX … #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL … #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX … #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL … #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX … #define regVPG8_VPG_GENERIC_STATUS … #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX … #define regVPG8_VPG_MEM_PWR … #define regVPG8_VPG_MEM_PWR_BASE_IDX … #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL … #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … #define regVPG8_VPG_ISRC1_2_DATA … #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX … #define regVPG8_VPG_MPEG_INFO0 … #define regVPG8_VPG_MPEG_INFO0_BASE_IDX … #define regVPG8_VPG_MPEG_INFO1 … #define regVPG8_VPG_MPEG_INFO1_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_sym32_enc3_dispdec // base address: 0x1b664 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS … #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS … #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL … #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE … #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_link_enc0_dispdec // base address: 0x1ad7c #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL … #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE … #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_dphy_sym320_dispdec // base address: 0x1add0 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL … #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_link_enc1_dispdec // base address: 0x1b0cc #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL … #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE … #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_dphy_sym321_dispdec // base address: 0x1b120 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL … #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_link_enc2_dispdec // base address: 0x1b41c #define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL … #define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_LINK_ENC2_DP_LINK_ENC_SPARE … #define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_dphy_sym322_dispdec // base address: 0x1b470 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL … #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_link_enc3_dispdec // base address: 0x1b76c #define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL … #define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX … #define regDP_LINK_ENC3_DP_LINK_ENC_SPARE … #define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX … // addressBlock: dcn_dcec_hpo_dp_dphy_sym323_dispdec // base address: 0x1b7c0 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL … #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX … // addressBlock: dcn_dcec_dlpc_dlpc_dispdec // base address: 0x0 #define regDLPC_ENABLE … #define regDLPC_ENABLE_BASE_IDX … #define regDLPC_CURRENT_COUNT … #define regDLPC_CURRENT_COUNT_BASE_IDX … #define regDLPC_OPTC_SNAPSHOT … #define regDLPC_OPTC_SNAPSHOT_BASE_IDX … #define regDLPC_PWRUP … #define regDLPC_PWRUP_BASE_IDX … #define regDLPC_OTG_RESYNC … #define regDLPC_OTG_RESYNC_BASE_IDX … #define regDLPC_DCN_ZSC_LONO_PWRUP … #define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX … #define regDLPC_SPARE … #define regDLPC_SPARE_BASE_IDX … #define regDLPC_COUNTER_INIT_VALUE … #define regDLPC_COUNTER_INIT_VALUE_BASE_IDX … // addressBlock: dcn_dpcssys_dpcssys_cr0_dispdec // base address: 0x0 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR … #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX … #define regDPCSSYS_CR0_DPCSSYS_CR_DATA … #define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX … // addressBlock: dcn_dpcssys_dpcssys_cr1_dispdec // base address: 0x360 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR … #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX … #define regDPCSSYS_CR1_DPCSSYS_CR_DATA … #define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX … // addressBlock: dcn_dpcssys_dpcssys_cr2_dispdec // base address: 0x6c0 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR … #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX … #define regDPCSSYS_CR2_DPCSSYS_CR_DATA … #define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX … // addressBlock: dcn_dpcssys_dpcssys_cr3_dispdec // base address: 0xa20 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR … #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX … #define regDPCSSYS_CR3_DPCSSYS_CR_DATA … #define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX … // addressBlock: dcn_dpcssys_dpcs0_rdpcstx0_dispdec // base address: 0x0 #define regRDPCSTX0_RDPCSTX_CNTL … #define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX … #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL … #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL … #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_CR_ADDR … #define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_CR_DATA … #define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL … #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX … #define regRDPCSTX0_RDPCSTX_SCRATCH0 … #define regRDPCSTX0_RDPCSTX_SCRATCH0_BASE_IDX … #define regRDPCSTX0_RDPCSTX_SPARE … #define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX … #define regRDPCSTX0_RDPCSTX_CNTL2 … #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX … #define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE … #define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL … #define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX … #define regRDPCSTX0_RDPCSTX_CNTL4 … #define regRDPCSTX0_RDPCSTX_CNTL4_BASE_IDX … #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG … #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL0 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL1 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL2 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL3 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL4 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL5 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL6 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL7 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL8 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL9 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL10 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL11 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL12 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL13 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL14 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_FUSE0 … #define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_FUSE1 … #define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_FUSE2 … #define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_FUSE3 … #define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL … #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX … #define regRDPCSTX0_RDPCSTX_SCRATCH1 … #define regRDPCSTX0_RDPCSTX_SCRATCH1_BASE_IDX … #define regRDPCSTX0_RDPCSTX_SCRATCH2 … #define regRDPCSTX0_RDPCSTX_SCRATCH2_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL15 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL16 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX … #define regRDPCSTX0_RDPCSTX_PHY_CNTL17 … #define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX … #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 … #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX … #define regRDPCSTX0_RDPCS_CNTL3 … #define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD … #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX … // addressBlock: dcn_dpcssys_dpcs0_rdpcstx1_dispdec // base address: 0x360 #define regRDPCSTX1_RDPCSTX_CNTL … #define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX … #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL … #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL … #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_CR_ADDR … #define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_CR_DATA … #define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL … #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX … #define regRDPCSTX1_RDPCSTX_SCRATCH0 … #define regRDPCSTX1_RDPCSTX_SCRATCH0_BASE_IDX … #define regRDPCSTX1_RDPCSTX_SPARE … #define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX … #define regRDPCSTX1_RDPCSTX_CNTL2 … #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX … #define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE … #define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL … #define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX … #define regRDPCSTX1_RDPCSTX_CNTL4 … #define regRDPCSTX1_RDPCSTX_CNTL4_BASE_IDX … #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG … #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL0 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL1 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL2 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL3 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL4 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL5 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL6 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL7 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL8 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL9 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL10 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL11 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL12 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL13 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL14 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_FUSE0 … #define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_FUSE1 … #define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_FUSE2 … #define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_FUSE3 … #define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL … #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX … #define regRDPCSTX1_RDPCSTX_SCRATCH1 … #define regRDPCSTX1_RDPCSTX_SCRATCH1_BASE_IDX … #define regRDPCSTX1_RDPCSTX_SCRATCH2 … #define regRDPCSTX1_RDPCSTX_SCRATCH2_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL15 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL16 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX … #define regRDPCSTX1_RDPCSTX_PHY_CNTL17 … #define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX … #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 … #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX … #define regRDPCSTX1_RDPCS_CNTL3 … #define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD … #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX … // addressBlock: dcn_dpcssys_dpcs0_rdpcstx2_dispdec // base address: 0x6c0 #define regRDPCSTX2_RDPCSTX_CNTL … #define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX … #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL … #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL … #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_CR_ADDR … #define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_CR_DATA … #define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL … #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX … #define regRDPCSTX2_RDPCSTX_SCRATCH0 … #define regRDPCSTX2_RDPCSTX_SCRATCH0_BASE_IDX … #define regRDPCSTX2_RDPCSTX_SPARE … #define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX … #define regRDPCSTX2_RDPCSTX_CNTL2 … #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX … #define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE … #define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL … #define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX … #define regRDPCSTX2_RDPCSTX_CNTL4 … #define regRDPCSTX2_RDPCSTX_CNTL4_BASE_IDX … #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG … #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL0 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL1 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL2 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL3 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL4 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL5 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL6 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL7 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL8 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL9 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL10 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL11 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL12 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL13 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL14 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_FUSE0 … #define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_FUSE1 … #define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_FUSE2 … #define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_FUSE3 … #define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL … #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX … #define regRDPCSTX2_RDPCSTX_SCRATCH1 … #define regRDPCSTX2_RDPCSTX_SCRATCH1_BASE_IDX … #define regRDPCSTX2_RDPCSTX_SCRATCH2 … #define regRDPCSTX2_RDPCSTX_SCRATCH2_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL15 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL16 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX … #define regRDPCSTX2_RDPCSTX_PHY_CNTL17 … #define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX … #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 … #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX … #define regRDPCSTX2_RDPCS_CNTL3 … #define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD … #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX … // addressBlock: dcn_dpcssys_dpcs0_rdpcstx3_dispdec // base address: 0xa20 #define regRDPCSTX3_RDPCSTX_CNTL … #define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX … #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL … #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL … #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_CR_ADDR … #define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_CR_DATA … #define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL … #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX … #define regRDPCSTX3_RDPCSTX_SCRATCH0 … #define regRDPCSTX3_RDPCSTX_SCRATCH0_BASE_IDX … #define regRDPCSTX3_RDPCSTX_SPARE … #define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX … #define regRDPCSTX3_RDPCSTX_CNTL2 … #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX … #define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE … #define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL … #define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX … #define regRDPCSTX3_RDPCSTX_CNTL4 … #define regRDPCSTX3_RDPCSTX_CNTL4_BASE_IDX … #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG … #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL0 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL1 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL2 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL3 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL4 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL5 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL6 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL7 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL8 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL9 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL10 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL11 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL12 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL13 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL14 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_FUSE0 … #define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_FUSE1 … #define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_FUSE2 … #define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_FUSE3 … #define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL … #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX … #define regRDPCSTX3_RDPCSTX_SCRATCH1 … #define regRDPCSTX3_RDPCSTX_SCRATCH1_BASE_IDX … #define regRDPCSTX3_RDPCSTX_SCRATCH2 … #define regRDPCSTX3_RDPCSTX_SCRATCH2_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL15 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL16 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX … #define regRDPCSTX3_RDPCSTX_PHY_CNTL17 … #define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX … #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 … #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX … #define regRDPCSTX3_RDPCS_CNTL3 … #define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD … #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azcontroller_azdec // base address: 0x0 #define regAZCONTROLLER0_CORB_WRITE_POINTER … #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX … #define regAZCONTROLLER0_CORB_READ_POINTER … #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX … #define regAZCONTROLLER0_CORB_CONTROL … #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX … #define regAZCONTROLLER0_CORB_STATUS … #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX … #define regAZCONTROLLER0_CORB_SIZE … #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX … #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS … #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS … #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER0_RIRB_WRITE_POINTER … #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX … #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT … #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX … #define regAZCONTROLLER0_RIRB_CONTROL … #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX … #define regAZCONTROLLER0_RIRB_STATUS … #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX … #define regAZCONTROLLER0_RIRB_SIZE … #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE … #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS … #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX … #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS … #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS … #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS … #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azendpoint_azdec // base address: 0x0 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azinputendpoint_azdec // base address: 0x0 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA … #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX … #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX … #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azroot_azdec // base address: 0x0 #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream0_azdec // base address: 0x0 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream1_azdec // base address: 0x20 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream2_azdec // base address: 0x40 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream3_azdec // base address: 0x60 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream4_azdec // base address: 0x80 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream5_azdec // base address: 0xa0 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream6_azdec // base address: 0xc0 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_host_hda_azstream7_azdec // base address: 0xe0 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azcontroller_azdec // base address: 0x1300000 #define regGLOBAL_CAPABILITIES … #define regGLOBAL_CAPABILITIES_BASE_IDX … #define regMINOR_VERSION … #define regMINOR_VERSION_BASE_IDX … #define regMAJOR_VERSION … #define regMAJOR_VERSION_BASE_IDX … #define regOUTPUT_PAYLOAD_CAPABILITY … #define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define regINPUT_PAYLOAD_CAPABILITY … #define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define regGLOBAL_CONTROL … #define regGLOBAL_CONTROL_BASE_IDX … #define regWAKE_ENABLE … #define regWAKE_ENABLE_BASE_IDX … #define regSTATE_CHANGE_STATUS … #define regSTATE_CHANGE_STATUS_BASE_IDX … #define regGLOBAL_STATUS … #define regGLOBAL_STATUS_BASE_IDX … #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY … #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX … #define regINPUT_STREAM_PAYLOAD_CAPABILITY … #define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX … #define regINTERRUPT_CONTROL … #define regINTERRUPT_CONTROL_BASE_IDX … #define regINTERRUPT_STATUS … #define regINTERRUPT_STATUS_BASE_IDX … #define regWALL_CLOCK_COUNTER … #define regWALL_CLOCK_COUNTER_BASE_IDX … #define regSTREAM_SYNCHRONIZATION … #define regSTREAM_SYNCHRONIZATION_BASE_IDX … #define regCORB_LOWER_BASE_ADDRESS … #define regCORB_LOWER_BASE_ADDRESS_BASE_IDX … #define regCORB_UPPER_BASE_ADDRESS … #define regCORB_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER1_CORB_WRITE_POINTER … #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX … #define regAZCONTROLLER1_CORB_READ_POINTER … #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX … #define regAZCONTROLLER1_CORB_CONTROL … #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX … #define regAZCONTROLLER1_CORB_STATUS … #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX … #define regAZCONTROLLER1_CORB_SIZE … #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX … #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS … #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS … #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER1_RIRB_WRITE_POINTER … #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX … #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT … #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX … #define regAZCONTROLLER1_RIRB_CONTROL … #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX … #define regAZCONTROLLER1_RIRB_STATUS … #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX … #define regAZCONTROLLER1_RIRB_SIZE … #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE … #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS … #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX … #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS … #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS … #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS … #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azendpoint_azdec // base address: 0x1300000 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_hda_azinputendpoint_azdec // base address: 0x1300000 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA … #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX … #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX … #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_hda_azroot_azdec // base address: 0x1300000 #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream0_azdec // base address: 0x1300000 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream1_azdec // base address: 0x1300020 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream2_azdec // base address: 0x1300040 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream3_azdec // base address: 0x1300060 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream4_azdec // base address: 0x1300080 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream5_azdec // base address: 0x13000a0 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream6_azdec // base address: 0x13000c0 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_hda_azstream7_azdec // base address: 0x13000e0 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dcn_dcec_dio_hdcp1kp_pkdbdec // base address: 0x32000000 // addressBlock: cnvc_cfg_cnvc_cfgdebugind // base address: 0x0 #define ixID2_CNVC_FLOW_CONTROL … #define ixID4_CNVC_FLOW_CONTROL_2 … #define ixID5_CNVC_REG_TO_FP_INPUT … #define ixID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0 … #define ixID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0 … #define ixID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1 … #define ixID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1 … // addressBlock: cm_cmdebugind // base address: 0x0 #define ixID1_CM_FLOW_CONTROL … #define ixID2_CM_BYPASS … #define ixID3_CM_REG_TO_FP_CSC_INPUT … #define ixID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0 … #define ixID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0 … #define ixID6_CM_REG_TO_FP_BIAS_INPUT … #define ixID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0 … #define ixID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0 … #define ixID9_CM_STATUS … #define ixIDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1 … #define ixIDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1 … #define ixIDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1 … #define ixIDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1 … // addressBlock: mcif_wb0_mcif_wbdebugind // base address: 0x0 #define ixID01_WB_FMT_DBG … #define ixID02_WB_FMT_DBG … #define ixID03_WB_FMT_DBG … #define ixID04_WB_MGR_DBG … #define ixID05_WB_MGR_DBG … #define ixID06_WB_MGR_DBG … #define ixID07_WB_MGR_DBG … #define ixID08_WB_ARB_DBG … #define ixID09_WB_ARB_DBG … #define ixID0A_WB_ARB_DBG … #define ixID0B_WB_ARB_DBG … #define ixID0C_WB_ARB_DBG … #define ixID0D_WB_ARB_DBG … #define ixID0E_WB_ARB_DBG … #define ixID0F_P010_WB_FMT_DBG_Y … #define ixID10_P010_WB_FMT_DBG_C … #define ixID11_WB_ARB_P010_DBG … #define ixID12_WB_ARB_P010_DBG … // addressBlock: mpc_ocsc_mpc_ocscdebugind // base address: 0x0 #define ixID1_MPC_OUT0_CSC_MODE_DB … #define ixID2_MPC_OUT1_CSC_MODE_DB … #define ixID3_MPC_OUT2_CSC_MODE_DB … #define ixID4_MPC_OUT3_CSC_MODE_DB … // addressBlock: mpcc0_mpccdebugind // base address: 0x0 #define ixMPCC0_ID01_MPCC_SEL_DB … #define ixMPCC0_ID02_MPCC_TOP_GAIN_DB … #define ixMPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB … #define ixMPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB … #define ixMPCC0_ID05_MPCC_BG_R_CR_DB … #define ixMPCC0_ID06_MPCC_BG_G_Y_DB … #define ixMPCC0_ID07_MPCC_BG_B_CB_DB … #define ixMPCC0_ID08_MPCC_CONTROL_DB … #define ixMPCC0_ID09_MPCC_SM_CONTROL_DB … #define ixMPCC0_ID17_MPCC_TOP_PIX … #define ixMPCC0_ID18_MPCC_recout_start … #define ixMPCC0_ID19_MPCC_recout_size … #define ixMPCC0_ID20_MPCC_mpc_size … #define ixMPCC0_ID21_MPCC_TOP_sideband … #define ixMPCC0_ID22_MPCC_BOT_PIX … #define ixMPCC0_ID23_MPCC_BOT_sideband … #define ixMPCC0_ID24_MPCC_OPP_PIX … #define ixMPCC0_ID25_MPCC_OPP_sideband … // addressBlock: mpcc1_mpccdebugind // base address: 0x0 #define ixMPCC1_ID01_MPCC_SEL_DB … #define ixMPCC1_ID02_MPCC_TOP_GAIN_DB … #define ixMPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB … #define ixMPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB … #define ixMPCC1_ID05_MPCC_BG_R_CR_DB … #define ixMPCC1_ID06_MPCC_BG_G_Y_DB … #define ixMPCC1_ID07_MPCC_BG_B_CB_DB … #define ixMPCC1_ID08_MPCC_CONTROL_DB … #define ixMPCC1_ID09_MPCC_SM_CONTROL_DB … #define ixMPCC1_ID17_MPCC_TOP_PIX … #define ixMPCC1_ID18_MPCC_recout_start … #define ixMPCC1_ID19_MPCC_recout_size … #define ixMPCC1_ID20_MPCC_mpc_size … #define ixMPCC1_ID21_MPCC_TOP_sideband … #define ixMPCC1_ID22_MPCC_BOT_PIX … #define ixMPCC1_ID23_MPCC_BOT_sideband … #define ixMPCC1_ID24_MPCC_OPP_PIX … #define ixMPCC1_ID25_MPCC_OPP_sideband … // addressBlock: mpcc2_mpccdebugind // base address: 0x0 #define ixMPCC2_ID01_MPCC_SEL_DB … #define ixMPCC2_ID02_MPCC_TOP_GAIN_DB … #define ixMPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB … #define ixMPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB … #define ixMPCC2_ID05_MPCC_BG_R_CR_DB … #define ixMPCC2_ID06_MPCC_BG_G_Y_DB … #define ixMPCC2_ID07_MPCC_BG_B_CB_DB … #define ixMPCC2_ID08_MPCC_CONTROL_DB … #define ixMPCC2_ID09_MPCC_SM_CONTROL_DB … #define ixMPCC2_ID17_MPCC_TOP_PIX … #define ixMPCC2_ID18_MPCC_recout_start … #define ixMPCC2_ID19_MPCC_recout_size … #define ixMPCC2_ID20_MPCC_mpc_size … #define ixMPCC2_ID21_MPCC_TOP_sideband … #define ixMPCC2_ID22_MPCC_BOT_PIX … #define ixMPCC2_ID23_MPCC_BOT_sideband … #define ixMPCC2_ID24_MPCC_OPP_PIX … #define ixMPCC2_ID25_MPCC_OPP_sideband … // addressBlock: mpcc3_mpccdebugind // base address: 0x0 #define ixMPCC3_ID01_MPCC_SEL_DB … #define ixMPCC3_ID02_MPCC_TOP_GAIN_DB … #define ixMPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB … #define ixMPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB … #define ixMPCC3_ID05_MPCC_BG_R_CR_DB … #define ixMPCC3_ID06_MPCC_BG_G_Y_DB … #define ixMPCC3_ID07_MPCC_BG_B_CB_DB … #define ixMPCC3_ID08_MPCC_CONTROL_DB … #define ixMPCC3_ID09_MPCC_SM_CONTROL_DB … #define ixMPCC3_ID17_MPCC_TOP_PIX … #define ixMPCC3_ID18_MPCC_recout_start … #define ixMPCC3_ID19_MPCC_recout_size … #define ixMPCC3_ID20_MPCC_mpc_size … #define ixMPCC3_ID21_MPCC_TOP_sideband … #define ixMPCC3_ID22_MPCC_BOT_PIX … #define ixMPCC3_ID23_MPCC_BOT_sideband … #define ixMPCC3_ID24_MPCC_OPP_PIX … #define ixMPCC3_ID25_MPCC_OPP_sideband … // addressBlock: mpcc_ogam0_mpcc_ogamdebugind // base address: 0x0 #define ixMPCC_OGAM0_ID01_MPCC_OGAM_CONTROL … // addressBlock: mpcc_mcm0_mpcc_mcmdebugind // base address: 0x0 #define ixMPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER … #define ixMPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER … #define ixMPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT … #define ixMPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP … #define ixMPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP … // addressBlock: mpcc_ogam1_mpcc_ogamdebugind // base address: 0x0 #define ixMPCC_OGAM1_ID01_MPCC_OGAM_CONTROL … // addressBlock: mpcc_mcm1_mpcc_mcmdebugind // base address: 0x0 #define ixMPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER … #define ixMPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER … #define ixMPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT … #define ixMPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP … #define ixMPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP … // addressBlock: mpcc_ogam2_mpcc_ogamdebugind // base address: 0x0 #define ixMPCC_OGAM2_ID01_MPCC_OGAM_CONTROL … // addressBlock: mpcc_mcm2_mpcc_mcmdebugind // base address: 0x0 #define ixMPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER … #define ixMPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER … #define ixMPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT … #define ixMPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP … #define ixMPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP … // addressBlock: mpcc_ogam3_mpcc_ogamdebugind // base address: 0x0 #define ixMPCC_OGAM3_ID01_MPCC_OGAM_CONTROL … // addressBlock: mpcc_mcm3_mpcc_mcmdebugind // base address: 0x0 #define ixMPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER … #define ixMPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER … #define ixMPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT … #define ixMPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP … #define ixMPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP … // addressBlock: otg0_otgdebugind // base address: 0x0 #define ixOTG0_OTG_DBG_DATA1 … #define ixOTG0_OTG_DBG_DATA2 … #define ixOTG0_OTG_DBG_DATA3 … #define ixOTG0_OTG_DBG_DATA4 … #define ixOTG0_OTG_DBG_DATA5 … #define ixOTG0_OTG_DBG_DATA6 … #define ixOTG0_OTG_DBG_DATA7 … #define ixOTG0_OTG_DBG_DATA8 … #define ixOTG0_OTG_DBG_DATA9 … #define ixOTG0_OTG_DBG_DATA10 … #define ixOTG0_OTG_SCL_INTERFACE … #define ixOTG0_OTG_DOUT_INTERFACE_01_A … #define ixOTG0_OTG_DOUT_INTERFACE_01_B … #define ixOTG0_OTG_DOUT_INTERFACE_02 … // addressBlock: otg1_otgdebugind // base address: 0x0 #define ixOTG1_OTG_DBG_DATA1 … #define ixOTG1_OTG_DBG_DATA2 … #define ixOTG1_OTG_DBG_DATA3 … #define ixOTG1_OTG_DBG_DATA4 … #define ixOTG1_OTG_DBG_DATA5 … #define ixOTG1_OTG_DBG_DATA6 … #define ixOTG1_OTG_DBG_DATA7 … #define ixOTG1_OTG_DBG_DATA8 … #define ixOTG1_OTG_DBG_DATA9 … #define ixOTG1_OTG_DBG_DATA10 … #define ixOTG1_OTG_SCL_INTERFACE … #define ixOTG1_OTG_DOUT_INTERFACE_01_A … #define ixOTG1_OTG_DOUT_INTERFACE_01_B … #define ixOTG1_OTG_DOUT_INTERFACE_02 … // addressBlock: otg2_otgdebugind // base address: 0x0 #define ixOTG2_OTG_DBG_DATA1 … #define ixOTG2_OTG_DBG_DATA2 … #define ixOTG2_OTG_DBG_DATA3 … #define ixOTG2_OTG_DBG_DATA4 … #define ixOTG2_OTG_DBG_DATA5 … #define ixOTG2_OTG_DBG_DATA6 … #define ixOTG2_OTG_DBG_DATA7 … #define ixOTG2_OTG_DBG_DATA8 … #define ixOTG2_OTG_DBG_DATA9 … #define ixOTG2_OTG_DBG_DATA10 … #define ixOTG2_OTG_SCL_INTERFACE … #define ixOTG2_OTG_DOUT_INTERFACE_01_A … #define ixOTG2_OTG_DOUT_INTERFACE_01_B … #define ixOTG2_OTG_DOUT_INTERFACE_02 … #define ixDCIO_DEBUG_ID … #define ixDCIO_DEBUG1B … #define ixDCIO_DEBUG1C … #define ixDCIO_DEBUG1D … #define ixDCIO_DEBUG1E … #define ixDCIO_DEBUG1F … #define ixDCIO_DEBUG20 … #define ixDCIO_DEBUG21 … #define ixDCIO_DEBUG22 … // addressBlock: otg3_otgdebugind // base address: 0x0 #define ixOTG3_OTG_DBG_DATA1 … #define ixOTG3_OTG_DBG_DATA2 … #define ixOTG3_OTG_DBG_DATA3 … #define ixOTG3_OTG_DBG_DATA4 … #define ixOTG3_OTG_DBG_DATA5 … #define ixOTG3_OTG_DBG_DATA6 … #define ixOTG3_OTG_DBG_DATA7 … #define ixOTG3_OTG_DBG_DATA8 … #define ixOTG3_OTG_DBG_DATA9 … #define ixOTG3_OTG_DBG_DATA10 … #define ixOTG3_OTG_SCL_INTERFACE … #define ixOTG3_OTG_DOUT_INTERFACE_01_A … #define ixOTG3_OTG_DOUT_INTERFACE_01_B … #define ixOTG3_OTG_DOUT_INTERFACE_02 … // addressBlock: azendpoint_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 … #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX … #define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC … #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH … // addressBlock: azendpoint_descriptorind // base address: 0x0 #define ixAUDIO_DESCRIPTOR0 … #define ixAUDIO_DESCRIPTOR1 … #define ixAUDIO_DESCRIPTOR2 … #define ixAUDIO_DESCRIPTOR3 … #define ixAUDIO_DESCRIPTOR4 … #define ixAUDIO_DESCRIPTOR5 … #define ixAUDIO_DESCRIPTOR6 … #define ixAUDIO_DESCRIPTOR7 … #define ixAUDIO_DESCRIPTOR8 … #define ixAUDIO_DESCRIPTOR9 … #define ixAUDIO_DESCRIPTOR10 … #define ixAUDIO_DESCRIPTOR11 … #define ixAUDIO_DESCRIPTOR12 … #define ixAUDIO_DESCRIPTOR13 … // addressBlock: azendpoint_sinkinfoind // base address: 0x0 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 … #define ixSINK_DESCRIPTION0 … #define ixSINK_DESCRIPTION1 … #define ixSINK_DESCRIPTION2 … #define ixSINK_DESCRIPTION3 … #define ixSINK_DESCRIPTION4 … #define ixSINK_DESCRIPTION5 … #define ixSINK_DESCRIPTION6 … #define ixSINK_DESCRIPTION7 … #define ixSINK_DESCRIPTION8 … #define ixSINK_DESCRIPTION9 … #define ixSINK_DESCRIPTION10 … #define ixSINK_DESCRIPTION11 … #define ixSINK_DESCRIPTION12 … #define ixSINK_DESCRIPTION13 … #define ixSINK_DESCRIPTION14 … #define ixSINK_DESCRIPTION15 … #define ixSINK_DESCRIPTION16 … #define ixSINK_DESCRIPTION17 … // addressBlock: azf0controller_azinputcrc0resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC0_CHANNEL0 … #define ixAZALIA_INPUT_CRC0_CHANNEL1 … #define ixAZALIA_INPUT_CRC0_CHANNEL2 … #define ixAZALIA_INPUT_CRC0_CHANNEL3 … #define ixAZALIA_INPUT_CRC0_CHANNEL4 … #define ixAZALIA_INPUT_CRC0_CHANNEL5 … #define ixAZALIA_INPUT_CRC0_CHANNEL6 … #define ixAZALIA_INPUT_CRC0_CHANNEL7 … // addressBlock: azf0controller_azinputcrc1resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … #define ixAZALIA_INPUT_CRC1_CHANNEL1 … #define ixAZALIA_INPUT_CRC1_CHANNEL2 … #define ixAZALIA_INPUT_CRC1_CHANNEL3 … #define ixAZALIA_INPUT_CRC1_CHANNEL4 … #define ixAZALIA_INPUT_CRC1_CHANNEL5 … #define ixAZALIA_INPUT_CRC1_CHANNEL6 … #define ixAZALIA_INPUT_CRC1_CHANNEL7 … // addressBlock: azf0controller_azcrc0resultind // base address: 0x0 #define ixAZALIA_CRC0_CHANNEL0 … #define ixAZALIA_CRC0_CHANNEL1 … #define ixAZALIA_CRC0_CHANNEL2 … #define ixAZALIA_CRC0_CHANNEL3 … #define ixAZALIA_CRC0_CHANNEL4 … #define ixAZALIA_CRC0_CHANNEL5 … #define ixAZALIA_CRC0_CHANNEL6 … #define ixAZALIA_CRC0_CHANNEL7 … // addressBlock: azf0controller_azcrc1resultind // base address: 0x0 #define ixAZALIA_CRC1_CHANNEL0 … #define ixAZALIA_CRC1_CHANNEL1 … #define ixAZALIA_CRC1_CHANNEL2 … #define ixAZALIA_CRC1_CHANNEL3 … #define ixAZALIA_CRC1_CHANNEL4 … #define ixAZALIA_CRC1_CHANNEL5 … #define ixAZALIA_CRC1_CHANNEL6 … #define ixAZALIA_CRC1_CHANNEL7 … // addressBlock: azinputendpoint_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … // addressBlock: azroot_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES … // addressBlock: azf0stream0_streamind // base address: 0x0 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream1_streamind // base address: 0x0 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream2_streamind // base address: 0x0 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream3_streamind // base address: 0x0 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream4_streamind // base address: 0x0 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream5_streamind // base address: 0x0 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream6_streamind // base address: 0x0 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream7_streamind // base address: 0x0 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream8_streamind // base address: 0x0 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream9_streamind // base address: 0x0 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream10_streamind // base address: 0x0 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream11_streamind // base address: 0x0 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream12_streamind // base address: 0x0 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream13_streamind // base address: 0x0 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream14_streamind // base address: 0x0 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream15_streamind // base address: 0x0 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0endpoint0_endpointind // base address: 0x0 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint1_endpointind // base address: 0x0 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint2_endpointind // base address: 0x0 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint3_endpointind // base address: 0x0 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint4_endpointind // base address: 0x0 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint5_endpointind // base address: 0x0 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint6_endpointind // base address: 0x0 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0endpoint7_endpointind // base address: 0x0 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS … // addressBlock: azf0inputendpoint0_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint1_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint2_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint3_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint4_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint5_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint6_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint7_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #endif
Codebase Browser
linux