dcn401_clk_mgr.c | Explore in Territory

// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.

#include "dccg.h"
#include "clk_mgr_internal.h"
#include "dcn401/dcn401_clk_mgr_smu_msg.h"
#include "dcn20/dcn20_clk_mgr.h"
#include "dce100/dce_clk_mgr.h"
#include "dcn31/dcn31_clk_mgr.h"
#include "dcn32/dcn32_clk_mgr.h"
#include "dcn401/dcn401_clk_mgr.h"
#include "reg_helper.h"
#include "core_types.h"
#include "dm_helpers.h"
#include "link.h"
#include "atomfirmware.h"

#include "dcn401_smu14_driver_if.h"

#include "dcn/dcn_4_1_0_offset.h"
#include "dcn/dcn_4_1_0_sh_mask.h"

#include "dml/dcn401/dcn401_fpu.h"

#define mmCLK01_CLK0_CLK_PLL_REQ …
#define mmCLK01_CLK0_CLK0_DFS_CNTL …
#define mmCLK01_CLK0_CLK1_DFS_CNTL …
#define mmCLK01_CLK0_CLK2_DFS_CNTL …
#define mmCLK01_CLK0_CLK3_DFS_CNTL …
#define mmCLK01_CLK0_CLK4_DFS_CNTL …

#define CLK0_CLK_PLL_REQ__FbMult_int_MASK …
#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK …
#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK …
#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT …
#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT …
#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT …

#undef FN
#define FN(reg_name, field_name) …

#define REG(reg) …

#define BASE_INNER(seg) …

#define BASE(seg) …

#define SR(reg_name) …

#define CLK_SR_DCN401(reg_name, block, inst) …

static const struct clk_mgr_registers clk_mgr_regs_dcn401 = …;

static const struct clk_mgr_shift clk_mgr_shift_dcn401 = …;

static const struct clk_mgr_mask clk_mgr_mask_dcn401 = …;

#define TO_DCN401_CLK_MGR(clk_mgr) …

static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
{ … }

static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
{ … }

/* Query SMU for all clock states for a particular clock */
static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
		unsigned int *num_levels)
{ … }

static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
{ … }

void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
{ … }

static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
			struct dc_state *context,
			int ref_dtbclk_khz)
{ … }

static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
		struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
{ … }

static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
{ … }

static void dcn401_update_clocks_update_dentist(
		struct clk_mgr_internal *clk_mgr,
		struct dc_state *context)
{ … }

static void dcn401_update_clocks_legacy(struct clk_mgr *clk_mgr_base,
			struct dc_state *context,
			bool safe_to_lower)
{ … }

static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
{ … }

static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
		struct clk_mgr *clk_mgr_base,
		struct dc_state *context,
		bool safe_to_lower)
{ … }

static unsigned int dcn401_build_update_display_clocks_sequence(
		struct clk_mgr *clk_mgr_base,
		struct dc_state *context,
		bool safe_to_lower)
{ … }

static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
		struct dc_state *context,
		bool safe_to_lower)
{ … }


static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
{ … }

static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{ … }

static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
{ … }
static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{ … }

/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
{ … }

/* Set max memclk to highest DPM value */
static void dcn401_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
{ … }

/* Get current memclk states, update bounding box */
static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
{ … }

static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
					struct dc_clocks *b)
{ … }

static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)
{ … }

static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
{ … }


static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{ … }

static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
{ … }

static struct clk_mgr_funcs dcn401_funcs = …;

struct clk_mgr_internal *dcn401_clk_mgr_construct(
		struct dc_context *ctx,
		struct dccg *dccg)
{ … }

void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
{ … }
linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
