/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DCN20_DCCG_H__ #define __DCN20_DCCG_H__ #include "dccg.h" #define DCCG_COMMON_REG_LIST_DCN_BASE() … #define DCCG_REG_LIST_DCN2() … #define DCCG_SF(reg_name, field_name, post_fix) … #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix) … #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix) … #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) … #define DCCG_MASK_SH_LIST_DCN2(mask_sh) … #define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) … #define DCCG_REG_FIELD_LIST(type) … #define DCCG3_REG_FIELD_LIST(type) … #define DCCG31_REG_FIELD_LIST(type) … #define DCCG314_REG_FIELD_LIST(type) … #define DCCG32_REG_FIELD_LIST(type) … #define DCCG35_REG_FIELD_LIST(type) …\ #define DCCG401_REG_FIELD_LIST(type) … struct dccg_shift { … }; struct dccg_mask { … }; struct dccg_registers { … }; struct dcn_dccg { … }; void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); void dccg2_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz); void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, bool en); void dccg2_otg_add_pixel(struct dccg *dccg, uint32_t otg_inst); void dccg2_otg_drop_pixel(struct dccg *dccg, uint32_t otg_inst); void dccg2_init(struct dccg *dccg); struct dccg *dccg2_create( struct dc_context *ctx, const struct dccg_registers *regs, const struct dccg_shift *dccg_shift, const struct dccg_mask *dccg_mask); void dcn_dccg_destroy(struct dccg **dccg); #endif //__DCN20_DCCG_H__
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