linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.

#include <drm/display/drm_dsc_helper.h>

#include "reg_helper.h"
#include "dcn401_dsc.h"
#include "dsc/dscc_types.h"
#include "dsc/rc_calc.h"

#define MAX_THROUGHPUT_PER_DSC_100HZ …
#define MAX_DSC_UNIT_COMBINE …

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

/* Object I/F functions */
//static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
static void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
static bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
static void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
		struct dsc_optc_config *dsc_optc_cfg);
//static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
static void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
static void dsc401_disable(struct display_stream_compressor *dsc);
static void dsc401_disconnect(struct display_stream_compressor *dsc);
static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);

const struct dsc_funcs dcn401_dsc_funcs = …;

/* Macro definitios for REG_SET macros*/
#define CTX …

#define REG(reg) …

#undef FN
#define FN(reg_name, field_name) …
#define DC_LOGGER …

enum dsc_bits_per_comp { … };

/* API functions (external or via structure->function_pointer) */

void dsc401_construct(struct dcn401_dsc *dsc,
		struct dc_context *ctx,
		int inst,
		const struct dcn401_dsc_registers *dsc_regs,
		const struct dcn401_dsc_shift *dsc_shift,
		const struct dcn401_dsc_mask *dsc_mask)
{ … }

static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
{ … }

/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
 * into a dcn_dsc_state struct.
 */
static void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
{ … }


static bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
{ … }

static void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
		struct dsc_optc_config *dsc_optc_cfg)
{ … }

static void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
{ … }


static void dsc401_disable(struct display_stream_compressor *dsc)
{ … }

static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
{ … }

static void dsc401_disconnect(struct display_stream_compressor *dsc)
{ … }

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
{ … }

void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)
{ … }