/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ // header file of functions being implemented #include "dcn32/dcn32_resource.h" #include "dcn20/dcn20_resource.h" #include "dml/dcn32/display_mode_vba_util_32.h" #include "dml/dcn32/dcn32_fpu.h" #include "dc_state_priv.h" #include "dc_stream_priv.h" static bool is_dual_plane(enum surface_pixel_format format) { … } uint32_t dcn32_helper_calculate_mall_bytes_for_cursor( struct dc *dc, struct pipe_ctx *pipe_ctx, bool ignore_cursor_buf) { … } /** * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways needed for SubVP * * Gets total allocation required for the phantom viewport calculated by DML in bytes and * converts to number of cache ways. * * @dc: current dc state * @context: new dc state * * Return: number of ways required for SubVP */ uint32_t dcn32_helper_calculate_num_ways_for_subvp( struct dc *dc, struct dc_state *context) { … } void dcn32_merge_pipes_for_subvp(struct dc *dc, struct dc_state *context) { … } bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, struct dc_state *context) { … } bool dcn32_subvp_in_use(struct dc *dc, struct dc_state *context) { … } bool dcn32_mpo_in_use(struct dc_state *context) { … } bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context) { … } bool dcn32_is_center_timing(struct pipe_ctx *pipe) { … } bool dcn32_is_psr_capable(struct pipe_ctx *pipe) { … } static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[]) { … } /** * dcn32_determine_det_override(): Determine DET allocation for each pipe * * This function determines how much DET to allocate for each pipe. The total number of * DET segments will be split equally among each of the streams, and after that the DET * segments per stream will be split equally among the planes for the given stream. * * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the * number of DET for that given plane will be split among the pipes driving that plane. * * * High level algorithm: * 1. Split total DET among number of streams * 2. For each stream, split DET among the planes * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation * among those pipes. * 4. Assign the DET override to the DML pipes. * * @dc: Current DC state * @context: New DC state to be programmed * @pipes: Array of DML pipes * * Return: void */ void dcn32_determine_det_override(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { … } void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { … } #define MAX_STRETCHED_V_BLANK … /* * Scaling factor for v_blank stretch calculations considering timing in * micro-seconds and pixel clock in 100hz. * Note: the parenthesis are necessary to ensure the correct order of * operation where V_SCALE is used. */ #define V_SCALE … static int get_frame_rate_at_max_stretch_100hz( struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us) { … } static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch( struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us, int current_refresh_rate) { … } static int get_refresh_rate(struct dc_stream_state *fpo_candidate_stream) { … } /** * dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch() - Determines if config can * support FPO * * @dc: current dc state * @context: new dc state * * Return: Pointer to FPO stream candidate if config can support FPO, otherwise NULL */ struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) { … } bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height) { … } /** * disallow_subvp_in_active_plus_blank() - Function to determine disallowed subvp + drr/vblank configs * * @pipe: subvp pipe to be used for the subvp + drr/vblank config * * Since subvp is being enabled on more configs (such as 1080p60), we want * to explicitly block any configs that we don't want to enable. We do not * want to enable any 1080p60 (SubVP) + drr / vblank configs since these * are already convered by FPO. * * Return: True if disallowed, false otherwise */ static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe) { … } /** * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible * * @dc: Current DC state * @context: New DC state to be programmed * * SubVP + DRR is admissible under the following conditions: * - Config must have 2 displays (i.e., 2 non-phantom master pipes) * - One display is SubVP * - Other display must have Freesync enabled * - The potential DRR display must not be PSR capable * * Return: True if admissible, false otherwise */ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context) { … } /** * dcn32_subvp_vblank_admissable() - Determine if SubVP + Vblank config is admissible * * @dc: Current DC state * @context: New DC state to be programmed * @vlevel: Voltage level calculated by DML * * SubVP + Vblank is admissible under the following conditions: * - Config must have 2 displays (i.e., 2 non-phantom master pipes) * - One display is SubVP * - Other display must not have Freesync capability * - DML must have output DRAM clock change support as SubVP + Vblank * - The potential vblank display must not be PSR capable * * Return: True if admissible, false otherwise */ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) { … } void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { … } void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context) { … }
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