/* * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "reg_helper.h" #include "core_types.h" #include "link_encoder.h" #include "dcn10_link_encoder.h" #include "stream_encoder.h" #include "dc_bios_types.h" #include "gpio_service_interface.h" #define CTX … #define DC_LOGGER … #define REG(reg) … #undef FN #define FN(reg_name, field_name) … /* * @brief * Trigger Source Select * ASIC-dependent, actual values for register programming */ #define DCN10_DIG_FE_SOURCE_SELECT_INVALID … #define DCN10_DIG_FE_SOURCE_SELECT_DIGA … #define DCN10_DIG_FE_SOURCE_SELECT_DIGB … #define DCN10_DIG_FE_SOURCE_SELECT_DIGC … #define DCN10_DIG_FE_SOURCE_SELECT_DIGD … #define DCN10_DIG_FE_SOURCE_SELECT_DIGE … #define DCN10_DIG_FE_SOURCE_SELECT_DIGF … #define DCN10_DIG_FE_SOURCE_SELECT_DIGG … enum { … }; static const struct link_encoder_funcs dcn10_lnk_enc_funcs = …; static enum bp_result link_transmitter_control( struct dcn10_link_encoder *enc10, struct bp_transmitter_control *cntl) { … } static void enable_phy_bypass_mode( struct dcn10_link_encoder *enc10, bool enable) { … } static void disable_prbs_symbols( struct dcn10_link_encoder *enc10, bool disable) { … } static void disable_prbs_mode( struct dcn10_link_encoder *enc10) { … } static void program_pattern_symbols( struct dcn10_link_encoder *enc10, uint16_t pattern_symbols[8]) { … } static void set_dp_phy_pattern_d102( struct dcn10_link_encoder *enc10) { … } static void set_link_training_complete( struct dcn10_link_encoder *enc10, bool complete) { … } void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( struct link_encoder *enc, uint32_t index) { … } static void setup_panel_mode( struct dcn10_link_encoder *enc10, enum dp_panel_mode panel_mode) { … } static void set_dp_phy_pattern_symbol_error( struct dcn10_link_encoder *enc10) { … } static void set_dp_phy_pattern_prbs7( struct dcn10_link_encoder *enc10) { … } static void set_dp_phy_pattern_80bit_custom( struct dcn10_link_encoder *enc10, const uint8_t *pattern) { … } static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( struct dcn10_link_encoder *enc10, unsigned int cp2520_pattern) { … } static void set_dp_phy_pattern_passthrough_mode( struct dcn10_link_encoder *enc10, enum dp_panel_mode panel_mode) { … } /* return value is bit-vector */ static uint8_t get_frontend_source( enum engine_id engine) { … } unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) { … } void enc1_configure_encoder( struct dcn10_link_encoder *enc10, const struct dc_link_settings *link_settings) { … } void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, bool exit_link_training_required) { … } void dcn10_psr_program_secondary_packet(struct link_encoder *enc, unsigned int sdp_transmit_line_num_deadline) { … } bool dcn10_is_dig_enabled(struct link_encoder *enc) { … } static void link_encoder_disable(struct dcn10_link_encoder *enc10) { … } static void hpd_initialize( struct dcn10_link_encoder *enc10) { … } bool dcn10_link_encoder_validate_dvi_output( const struct dcn10_link_encoder *enc10, enum signal_type connector_signal, enum signal_type signal, const struct dc_crtc_timing *crtc_timing) { … } static bool dcn10_link_encoder_validate_hdmi_output( const struct dcn10_link_encoder *enc10, const struct dc_crtc_timing *crtc_timing, const struct dc_edid_caps *edid_caps, int adjusted_pix_clk_100hz) { … } bool dcn10_link_encoder_validate_dp_output( const struct dcn10_link_encoder *enc10, const struct dc_crtc_timing *crtc_timing) { … } void dcn10_link_encoder_construct( struct dcn10_link_encoder *enc10, const struct encoder_init_data *init_data, const struct encoder_feature_support *enc_features, const struct dcn10_link_enc_registers *link_regs, const struct dcn10_link_enc_aux_registers *aux_regs, const struct dcn10_link_enc_hpd_registers *hpd_regs, const struct dcn10_link_enc_shift *link_shift, const struct dcn10_link_enc_mask *link_mask) { … } bool dcn10_link_encoder_validate_output_with_stream( struct link_encoder *enc, const struct dc_stream_state *stream) { … } void dcn10_link_encoder_hw_init( struct link_encoder *enc) { … } void dcn10_link_encoder_destroy(struct link_encoder **enc) { … } void dcn10_link_encoder_setup( struct link_encoder *enc, enum signal_type signal) { … } /* TODO: still need depth or just pass in adjusted pixel clock? */ void dcn10_link_encoder_enable_tmds_output( struct link_encoder *enc, enum clock_source_id clock_source, enum dc_color_depth color_depth, enum signal_type signal, uint32_t pixel_clock) { … } void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( struct link_encoder *enc, enum clock_source_id clock_source, enum dc_color_depth color_depth, enum signal_type signal, uint32_t pixel_clock) { … } /* enables DP PHY output */ void dcn10_link_encoder_enable_dp_output( struct link_encoder *enc, const struct dc_link_settings *link_settings, enum clock_source_id clock_source) { … } /* enables DP PHY output in MST mode */ void dcn10_link_encoder_enable_dp_mst_output( struct link_encoder *enc, const struct dc_link_settings *link_settings, enum clock_source_id clock_source) { … } /* * @brief * Disable transmitter and its encoder */ void dcn10_link_encoder_disable_output( struct link_encoder *enc, enum signal_type signal) { … } void dcn10_link_encoder_dp_set_lane_settings( struct link_encoder *enc, const struct dc_link_settings *link_settings, const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) { … } /* set DP PHY test and training patterns */ void dcn10_link_encoder_dp_set_phy_pattern( struct link_encoder *enc, const struct encoder_set_dp_phy_pattern_param *param) { … } static void fill_stream_allocation_row_info( const struct link_mst_stream_allocation *stream_allocation, uint32_t *src, uint32_t *slots) { … } /* programs DP MST VC payload allocation */ void dcn10_link_encoder_update_mst_stream_allocation_table( struct link_encoder *enc, const struct link_mst_stream_allocation_table *table) { … } void dcn10_link_encoder_connect_dig_be_to_fe( struct link_encoder *enc, enum engine_id engine, bool connect) { … } #define HPD_REG(reg) … #define HPD_REG_READ(reg_name) … #define HPD_REG_UPDATE_N(reg_name, n, ...) … #define HPD_REG_UPDATE(reg_name, field, val) … void dcn10_link_encoder_enable_hpd(struct link_encoder *enc) { … } void dcn10_link_encoder_disable_hpd(struct link_encoder *enc) { … } #define AUX_REG(reg) … #define AUX_REG_READ(reg_name) … #define AUX_REG_UPDATE_N(reg_name, n, ...) … #define AUX_REG_UPDATE(reg_name, field, val) … #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) … void dcn10_aux_initialize(struct dcn10_link_encoder *enc10) { … } enum signal_type dcn10_get_dig_mode( struct link_encoder *enc) { … } void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings) { … }
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