linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "reg_helper.h"

#include "core_types.h"
#include "link_encoder.h"
#include "dcn20_link_encoder.h"
#include "stream_encoder.h"
#include "dc_bios_types.h"

#include "gpio_service_interface.h"

#define CTX …
#define DC_LOGGER …

#define REG(reg) …

#undef FN
#define FN(reg_name, field_name) …

#define IND_REG(index) …

#ifndef MAX
#define MAX …
#endif
#ifndef MIN
#define MIN …
#endif

static struct mpll_cfg dcn2_mpll_cfg[] = …;

void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
{ … }

void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
{ … }

bool enc2_fec_is_active(struct link_encoder *enc)
{ … }

/* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
 * into a dcn_dsc_state struct.
 */
void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
{ … }

static bool update_cfg_data(
		struct dcn10_link_encoder *enc10,
		const struct dc_link_settings *link_settings,
		struct dpcssys_phy_seq_cfg *cfg)
{ … }

void dcn20_link_encoder_enable_dp_output(
	struct link_encoder *enc,
	const struct dc_link_settings *link_settings,
	enum clock_source_id clock_source)
{ … }

void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
	struct dc_link_settings *link_settings)
{ … }

bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
{ … }

#define AUX_REG(reg) …

#define AUX_REG_READ(reg_name) …

#define AUX_REG_WRITE(reg_name, val) …
void enc2_hw_init(struct link_encoder *enc)
{ … }

static const struct link_encoder_funcs dcn20_link_enc_funcs = …;

void dcn20_link_encoder_construct(
	struct dcn20_link_encoder *enc20,
	const struct encoder_init_data *init_data,
	const struct encoder_feature_support *enc_features,
	const struct dcn10_link_enc_registers *link_regs,
	const struct dcn10_link_enc_aux_registers *aux_regs,
	const struct dcn10_link_enc_hpd_registers *hpd_regs,
	const struct dcn10_link_enc_shift *link_shift,
	const struct dcn10_link_enc_mask *link_mask)
{ … }