linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4.c

// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.


#include "dml2_pmo_factory.h"
#include "dml2_pmo_dcn4.h"

static const int MIN_VACTIVE_MARGIN_US = …; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding
static const int SUBVP_DRR_MARGIN_US = …;

static const enum dml2_pmo_pstate_strategy full_strategy_list_1_display[][4] = …;

static const int full_strategy_list_1_display_size = …;

static const enum dml2_pmo_pstate_strategy full_strategy_list_2_display[][4] = …;

static const int full_strategy_list_2_display_size = …;

static const enum dml2_pmo_pstate_strategy full_strategy_list_3_display[][4] = …;

static const int full_strategy_list_3_display_size = …;

static const enum dml2_pmo_pstate_strategy full_strategy_list_4_display[][4] = …;

static const int full_strategy_list_4_display_size = …;

static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)
{ … }

static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)
{ … }

static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int stream_index)
{ … }

static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,
	int free_pipes)
{ … }

bool pmo_dcn4_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)
{ … }

bool pmo_dcn4_initialize(struct dml2_pmo_initialize_in_out *in_out)
{ … }

static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
{ … }

static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)
{ … }

bool pmo_dcn4_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)
{ … }

bool pmo_dcn4_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)
{ … }

static int find_highest_odm_load_stream_index(
		const struct dml2_display_cfg *display_config,
		const struct dml2_core_mode_support_result *mode_support_result)
{ … }

bool pmo_dcn4_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)
{ … }

static bool are_timings_trivially_synchronizable(const struct display_configuation_with_meta *display_config, int mask)
{ … }

static void set_bit_in_bitfield(unsigned int *bit_field, unsigned int bit_offset)
{ … }

static bool is_bit_set_in_bitfield(unsigned int bit_field, unsigned int bit_offset)
{ … }

static bool are_all_timings_drr_enabled(const struct display_configuation_with_meta *display_config, int mask)
{ … }

static void insert_into_candidate_list(const enum dml2_pmo_pstate_strategy *per_stream_pstate_strategy, int stream_count, struct dml2_pmo_scratch *scratch)
{ … }

static bool all_planes_match_strategy(const struct display_configuation_with_meta *display_cfg, int plane_mask, enum dml2_pmo_pstate_strategy strategy)
{ … }

static bool subvp_subvp_schedulable(struct dml2_pmo_instance *pmo, const struct display_configuation_with_meta *display_cfg,
	unsigned char *svp_stream_indicies, char svp_stream_count)
{ … }

static bool validate_svp_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, int svp_stream_mask)
{ … }

static bool validate_drr_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, int drr_stream_mask)
{ … }

static bool validate_svp_drr_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, int svp_stream_mask, int drr_stream_mask)
{ … }

static bool validate_svp_vblank_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, int svp_stream_mask, int vblank_stream_mask)
{ … }

static bool validate_drr_vblank_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, int drr_stream_mask, int vblank_stream_mask)
{ … }

static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg, const enum dml2_pmo_pstate_strategy per_stream_pstate_strategy[4])
{ … }

static int get_vactive_pstate_margin(const struct display_configuation_with_meta *display_cfg, int plane_mask)
{ … }

bool pmo_dcn4_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)
{ … }

static void reset_display_configuration(struct display_configuation_with_meta *display_config)
{ … }

static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

static void setup_planes_for_vblank_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

static void setup_planes_for_vactive_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

static bool setup_display_config(struct display_configuation_with_meta *display_config, struct dml2_pmo_scratch *scratch, int strategy_index)
{ … }

static int get_minimum_reserved_time_us_for_planes(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

bool pmo_dcn4_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)
{ … }

bool pmo_dcn4_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)
{ … }