linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/

#include "dml2_pmo_factory.h"
#include "dml2_pmo_dcn4.h"
#include "dml2_debug.h"
#include "lib_float_math.h"
#include "dml2_pmo_dcn4_fams2.h"

static const double MIN_VACTIVE_MARGIN_PCT = …; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding

static const enum dml2_pmo_pstate_strategy base_strategy_list_1_display[][PMO_DCN4_MAX_DISPLAYS] = …;

static const int base_strategy_list_1_display_size = …;

static const enum dml2_pmo_pstate_strategy base_strategy_list_2_display[][PMO_DCN4_MAX_DISPLAYS] = …;

static const int base_strategy_list_2_display_size = …;

static const enum dml2_pmo_pstate_strategy base_strategy_list_3_display[][PMO_DCN4_MAX_DISPLAYS] = …;

static const int base_strategy_list_3_display_size = …;

static const enum dml2_pmo_pstate_strategy base_strategy_list_4_display[][PMO_DCN4_MAX_DISPLAYS] = …;

static const int base_strategy_list_4_display_size = …;


static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)
{ … }

static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)
{ … }

static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int stream_index)
{ … }

static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,
	int free_pipes)
{ … }

bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)
{ … }

static enum dml2_pmo_pstate_strategy convert_strategy_to_drr_variant(const enum dml2_pmo_pstate_strategy base_strategy)
{ … }

static enum dml2_pmo_pstate_strategy(*get_expanded_strategy_list(
	struct dml2_pmo_init_data *init_data,
	int stream_count))[PMO_DCN4_MAX_DISPLAYS]
{ … }

static unsigned int get_num_expanded_strategies(
	struct dml2_pmo_init_data *init_data,
	int stream_count)
{ … }

static void insert_strategy_into_expanded_list(
	const enum dml2_pmo_pstate_strategy per_stream_pstate_strategy[PMO_DCN4_MAX_DISPLAYS],
	int stream_count,
	struct dml2_pmo_init_data *init_data)
{ … }

static void expand_base_strategy(struct dml2_pmo_instance *pmo,
	const enum dml2_pmo_pstate_strategy base_strategy_list[PMO_DCN4_MAX_DISPLAYS],
	unsigned int stream_count)
{ … }

static void expand_variant_strategy(struct dml2_pmo_instance *pmo,
		const enum dml2_pmo_pstate_strategy base_strategy_list[PMO_DCN4_MAX_DISPLAYS],
		unsigned int stream_count)
{ … }

static void expand_base_strategies(
	struct dml2_pmo_instance *pmo,
	const enum dml2_pmo_pstate_strategy(*base_strategies_list)[PMO_DCN4_MAX_DISPLAYS],
	const unsigned int num_base_strategies,
	unsigned int stream_count)
{ … }

bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out)
{ … }

static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
{ … }

static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)
{ … }

bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)
{ … }

bool pmo_dcn4_fams2_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)
{ … }

static int find_highest_odm_load_stream_index(
		const struct dml2_display_cfg *display_config,
		const struct dml2_core_mode_support_result *mode_support_result)
{ … }

bool pmo_dcn4_fams2_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)
{ … }

static void set_bit_in_bitfield(unsigned int *bit_field, unsigned int bit_offset)
{ … }

static bool is_bit_set_in_bitfield(unsigned int bit_field, unsigned int bit_offset)
{ … }

static void build_synchronized_timing_groups(
	struct dml2_pmo_instance *pmo,
	struct display_configuation_with_meta *display_config)
{ … }

static bool all_timings_support_vactive(const struct dml2_pmo_instance *pmo,
		const struct display_configuation_with_meta *display_config,
		unsigned int mask)
{ … }

static bool all_timings_support_vblank(const struct dml2_pmo_instance *pmo,
		const struct display_configuation_with_meta *display_config,
		unsigned int mask)
{ … }

static unsigned int calc_svp_microschedule(const struct dml2_fams2_meta *fams2_meta)
{ … }

static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_config,
	unsigned int mask)
{ … }

static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_config,
	unsigned int mask)
{ … }

static void insert_into_candidate_list(const enum dml2_pmo_pstate_strategy *per_stream_pstate_strategy, int stream_count, struct dml2_pmo_scratch *scratch)
{ … }

static bool all_planes_match_strategy(const struct display_configuation_with_meta *display_cfg, int plane_mask, enum dml2_pmo_pstate_strategy strategy)
{ … }

static void build_method_scheduling_params(
	struct dml2_fams2_per_method_common_meta *stream_method_fams2_meta,
	struct dml2_fams2_meta *stream_fams2_meta)
{ … }

static struct dml2_fams2_per_method_common_meta *get_per_method_common_meta(
	struct dml2_pmo_instance *pmo,
	enum dml2_pmo_pstate_strategy stream_pstate_strategy,
	int stream_idx)
{ … }

static bool is_timing_group_schedulable(
		struct dml2_pmo_instance *pmo,
		const struct display_configuation_with_meta *display_cfg,
		const enum dml2_pmo_pstate_strategy per_stream_pstate_strategy[PMO_DCN4_MAX_DISPLAYS],
		const unsigned int timing_group_idx,
		struct dml2_fams2_per_method_common_meta *group_fams2_meta)
{ … }

static bool is_config_schedulable(
	struct dml2_pmo_instance *pmo,
	const struct display_configuation_with_meta *display_cfg,
	const enum dml2_pmo_pstate_strategy per_stream_pstate_strategy[PMO_DCN4_MAX_DISPLAYS])
{ … }

static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,
		const struct display_configuation_with_meta *display_cfg,
		const enum dml2_pmo_pstate_strategy stream_pstate_strategy,
		unsigned int stream_index)
{ … }

static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_instance *pmo,
		const struct display_configuation_with_meta *display_cfg,
		const enum dml2_pmo_pstate_strategy per_stream_pstate_strategy[PMO_DCN4_MAX_DISPLAYS])
{ … }

static int get_vactive_pstate_margin(const struct display_configuation_with_meta *display_cfg, int plane_mask)
{ … }

static unsigned int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask)
{ … }

static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo,
	struct display_configuation_with_meta *display_config,
	int stream_index)
{ … }

static void build_subvp_meta_per_stream(struct dml2_pmo_instance *pmo,
	struct display_configuation_with_meta *display_config,
	int stream_index)
{ … }

bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)
{ … }

static void reset_display_configuration(struct display_configuation_with_meta *display_config)
{ … }

static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_svp_drr_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_vblank_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_vblank_drr_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_vactive_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static void setup_planes_for_vactive_drr_by_mask(struct display_configuation_with_meta *display_config,
	struct dml2_pmo_instance *pmo,
	int plane_mask)
{ … }

static bool setup_display_config(struct display_configuation_with_meta *display_config, struct dml2_pmo_instance *pmo, int strategy_index)
{ … }

static int get_minimum_reserved_time_us_for_planes(struct display_configuation_with_meta *display_config, int plane_mask)
{ … }

bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)
{ … }

bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)
{ … }

bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)
{ … }

bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out)
{ … }

bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out)
{ … }