/* * DCE_11_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef DCE_11_0_D_H #define DCE_11_0_D_H #define mmPIPE0_PG_CONFIG … #define mmPIPE0_PG_ENABLE … #define mmPIPE0_PG_STATUS … #define mmPIPE1_PG_CONFIG … #define mmPIPE1_PG_ENABLE … #define mmPIPE1_PG_STATUS … #define mmPIPE2_PG_CONFIG … #define mmPIPE2_PG_ENABLE … #define mmPIPE2_PG_STATUS … #define mmDCFEV0_PG_CONFIG … #define mmDCFEV0_PG_ENABLE … #define mmDCFEV0_PG_STATUS … #define mmDCPG_INTERRUPT_STATUS … #define mmDCPG_INTERRUPT_CONTROL … #define mmDC_IP_REQUEST_CNTL … #define mmDC_PGFSM_CONFIG_REG … #define mmDC_PGFSM_WRITE_REG … #define mmDC_PGCNTL_STATUS_REG … #define mmDCPG_TEST_DEBUG_INDEX … #define mmDCPG_TEST_DEBUG_DATA … #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL … #define mmBL1_PWM_USER_LEVEL … #define mmBL1_PWM_TARGET_ABM_LEVEL … #define mmBL1_PWM_CURRENT_ABM_LEVEL … #define mmBL1_PWM_FINAL_DUTY_CYCLE … #define mmBL1_PWM_MINIMUM_DUTY_CYCLE … #define mmBL1_PWM_ABM_CNTL … #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE … #define mmBL1_PWM_GRP2_REG_LOCK … #define mmDC_ABM1_CNTL … #define mmDC_ABM1_IPCSC_COEFF_SEL … #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 … #define mmDC_ABM1_ACE_THRES_12 … #define mmDC_ABM1_ACE_THRES_34 … #define mmDC_ABM1_ACE_CNTL_MISC … #define mmDC_ABM1_DEBUG_MISC … #define mmDC_ABM1_HGLS_REG_READ_PROGRESS … #define mmDC_ABM1_HG_MISC_CTRL … #define mmDC_ABM1_LS_SUM_OF_LUMA … #define mmDC_ABM1_LS_MIN_MAX_LUMA … #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define mmDC_ABM1_LS_PIXEL_COUNT … #define mmDC_ABM1_LS_OVR_SCAN_BIN … #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define mmDC_ABM1_HG_SAMPLE_RATE … #define mmDC_ABM1_LS_SAMPLE_RATE … #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define mmDC_ABM1_HG_RESULT_1 … #define mmDC_ABM1_HG_RESULT_2 … #define mmDC_ABM1_HG_RESULT_3 … #define mmDC_ABM1_HG_RESULT_4 … #define mmDC_ABM1_HG_RESULT_5 … #define mmDC_ABM1_HG_RESULT_6 … #define mmDC_ABM1_HG_RESULT_7 … #define mmDC_ABM1_HG_RESULT_8 … #define mmDC_ABM1_HG_RESULT_9 … #define mmDC_ABM1_HG_RESULT_10 … #define mmDC_ABM1_HG_RESULT_11 … #define mmDC_ABM1_HG_RESULT_12 … #define mmDC_ABM1_HG_RESULT_13 … #define mmDC_ABM1_HG_RESULT_14 … #define mmDC_ABM1_HG_RESULT_15 … #define mmDC_ABM1_HG_RESULT_16 … #define mmDC_ABM1_HG_RESULT_17 … #define mmDC_ABM1_HG_RESULT_18 … #define mmDC_ABM1_HG_RESULT_19 … #define mmDC_ABM1_HG_RESULT_20 … #define mmDC_ABM1_HG_RESULT_21 … #define mmDC_ABM1_HG_RESULT_22 … #define mmDC_ABM1_HG_RESULT_23 … #define mmDC_ABM1_HG_RESULT_24 … #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE … #define mmDC_ABM1_BL_MASTER_LOCK … #define mmABM_TEST_DEBUG_INDEX … #define mmABM_TEST_DEBUG_DATA … #define mmCRTC_H_BLANK_EARLY_NUM … #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC_H_TOTAL … #define mmCRTC0_CRTC_H_TOTAL … #define mmCRTC1_CRTC_H_TOTAL … #define mmCRTC2_CRTC_H_TOTAL … #define mmCRTC3_CRTC_H_TOTAL … #define mmCRTC4_CRTC_H_TOTAL … #define mmCRTC5_CRTC_H_TOTAL … #define mmCRTC_H_BLANK_START_END … #define mmCRTC0_CRTC_H_BLANK_START_END … #define mmCRTC1_CRTC_H_BLANK_START_END … #define mmCRTC2_CRTC_H_BLANK_START_END … #define mmCRTC3_CRTC_H_BLANK_START_END … #define mmCRTC4_CRTC_H_BLANK_START_END … #define mmCRTC5_CRTC_H_BLANK_START_END … #define mmCRTC_H_SYNC_A … #define mmCRTC0_CRTC_H_SYNC_A … #define mmCRTC1_CRTC_H_SYNC_A … #define mmCRTC2_CRTC_H_SYNC_A … #define mmCRTC3_CRTC_H_SYNC_A … #define mmCRTC4_CRTC_H_SYNC_A … #define mmCRTC5_CRTC_H_SYNC_A … #define mmCRTC_H_SYNC_A_CNTL … #define mmCRTC0_CRTC_H_SYNC_A_CNTL … #define mmCRTC1_CRTC_H_SYNC_A_CNTL … #define mmCRTC2_CRTC_H_SYNC_A_CNTL … #define mmCRTC3_CRTC_H_SYNC_A_CNTL … #define mmCRTC4_CRTC_H_SYNC_A_CNTL … #define mmCRTC5_CRTC_H_SYNC_A_CNTL … #define mmCRTC_H_SYNC_B … #define mmCRTC0_CRTC_H_SYNC_B … #define mmCRTC1_CRTC_H_SYNC_B … #define mmCRTC2_CRTC_H_SYNC_B … #define mmCRTC3_CRTC_H_SYNC_B … #define mmCRTC4_CRTC_H_SYNC_B … #define mmCRTC5_CRTC_H_SYNC_B … #define mmCRTC_H_SYNC_B_CNTL … #define mmCRTC0_CRTC_H_SYNC_B_CNTL … #define mmCRTC1_CRTC_H_SYNC_B_CNTL … #define mmCRTC2_CRTC_H_SYNC_B_CNTL … #define mmCRTC3_CRTC_H_SYNC_B_CNTL … #define mmCRTC4_CRTC_H_SYNC_B_CNTL … #define mmCRTC5_CRTC_H_SYNC_B_CNTL … #define mmCRTC_VBI_END … #define mmCRTC0_CRTC_VBI_END … #define mmCRTC1_CRTC_VBI_END … #define mmCRTC2_CRTC_VBI_END … #define mmCRTC3_CRTC_VBI_END … #define mmCRTC4_CRTC_VBI_END … #define mmCRTC5_CRTC_VBI_END … #define mmCRTC_V_TOTAL … #define mmCRTC0_CRTC_V_TOTAL … #define mmCRTC1_CRTC_V_TOTAL … #define mmCRTC2_CRTC_V_TOTAL … #define mmCRTC3_CRTC_V_TOTAL … #define mmCRTC4_CRTC_V_TOTAL … #define mmCRTC5_CRTC_V_TOTAL … #define mmCRTC_V_TOTAL_MIN … #define mmCRTC0_CRTC_V_TOTAL_MIN … #define mmCRTC1_CRTC_V_TOTAL_MIN … #define mmCRTC2_CRTC_V_TOTAL_MIN … #define mmCRTC3_CRTC_V_TOTAL_MIN … #define mmCRTC4_CRTC_V_TOTAL_MIN … #define mmCRTC5_CRTC_V_TOTAL_MIN … #define mmCRTC_V_TOTAL_MAX … #define mmCRTC0_CRTC_V_TOTAL_MAX … #define mmCRTC1_CRTC_V_TOTAL_MAX … #define mmCRTC2_CRTC_V_TOTAL_MAX … #define mmCRTC3_CRTC_V_TOTAL_MAX … #define mmCRTC4_CRTC_V_TOTAL_MAX … #define mmCRTC5_CRTC_V_TOTAL_MAX … #define mmCRTC_V_TOTAL_CONTROL … #define mmCRTC0_CRTC_V_TOTAL_CONTROL … #define mmCRTC1_CRTC_V_TOTAL_CONTROL … #define mmCRTC2_CRTC_V_TOTAL_CONTROL … #define mmCRTC3_CRTC_V_TOTAL_CONTROL … #define mmCRTC4_CRTC_V_TOTAL_CONTROL … #define mmCRTC5_CRTC_V_TOTAL_CONTROL … #define mmCRTC_V_TOTAL_INT_STATUS … #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC_V_BLANK_START_END … #define mmCRTC0_CRTC_V_BLANK_START_END … #define mmCRTC1_CRTC_V_BLANK_START_END … #define mmCRTC2_CRTC_V_BLANK_START_END … #define mmCRTC3_CRTC_V_BLANK_START_END … #define mmCRTC4_CRTC_V_BLANK_START_END … #define mmCRTC5_CRTC_V_BLANK_START_END … #define mmCRTC_V_SYNC_A … #define mmCRTC0_CRTC_V_SYNC_A … #define mmCRTC1_CRTC_V_SYNC_A … #define mmCRTC2_CRTC_V_SYNC_A … #define mmCRTC3_CRTC_V_SYNC_A … #define mmCRTC4_CRTC_V_SYNC_A … #define mmCRTC5_CRTC_V_SYNC_A … #define mmCRTC_V_SYNC_A_CNTL … #define mmCRTC0_CRTC_V_SYNC_A_CNTL … #define mmCRTC1_CRTC_V_SYNC_A_CNTL … #define mmCRTC2_CRTC_V_SYNC_A_CNTL … #define mmCRTC3_CRTC_V_SYNC_A_CNTL … #define mmCRTC4_CRTC_V_SYNC_A_CNTL … #define mmCRTC5_CRTC_V_SYNC_A_CNTL … #define mmCRTC_V_SYNC_B … #define mmCRTC0_CRTC_V_SYNC_B … #define mmCRTC1_CRTC_V_SYNC_B … #define mmCRTC2_CRTC_V_SYNC_B … #define mmCRTC3_CRTC_V_SYNC_B … #define mmCRTC4_CRTC_V_SYNC_B … #define mmCRTC5_CRTC_V_SYNC_B … #define mmCRTC_V_SYNC_B_CNTL … #define mmCRTC0_CRTC_V_SYNC_B_CNTL … #define mmCRTC1_CRTC_V_SYNC_B_CNTL … #define mmCRTC2_CRTC_V_SYNC_B_CNTL … #define mmCRTC3_CRTC_V_SYNC_B_CNTL … #define mmCRTC4_CRTC_V_SYNC_B_CNTL … #define mmCRTC5_CRTC_V_SYNC_B_CNTL … #define mmCRTC_DTMTEST_CNTL … #define mmCRTC0_CRTC_DTMTEST_CNTL … #define mmCRTC1_CRTC_DTMTEST_CNTL … #define mmCRTC2_CRTC_DTMTEST_CNTL … #define mmCRTC3_CRTC_DTMTEST_CNTL … #define mmCRTC4_CRTC_DTMTEST_CNTL … #define mmCRTC5_CRTC_DTMTEST_CNTL … #define mmCRTC_DTMTEST_STATUS_POSITION … #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC_TRIGA_CNTL … #define mmCRTC0_CRTC_TRIGA_CNTL … #define mmCRTC1_CRTC_TRIGA_CNTL … #define mmCRTC2_CRTC_TRIGA_CNTL … #define mmCRTC3_CRTC_TRIGA_CNTL … #define mmCRTC4_CRTC_TRIGA_CNTL … #define mmCRTC5_CRTC_TRIGA_CNTL … #define mmCRTC_TRIGA_MANUAL_TRIG … #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC_TRIGB_CNTL … #define mmCRTC0_CRTC_TRIGB_CNTL … #define mmCRTC1_CRTC_TRIGB_CNTL … #define mmCRTC2_CRTC_TRIGB_CNTL … #define mmCRTC3_CRTC_TRIGB_CNTL … #define mmCRTC4_CRTC_TRIGB_CNTL … #define mmCRTC5_CRTC_TRIGB_CNTL … #define mmCRTC_TRIGB_MANUAL_TRIG … #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC_FLOW_CONTROL … #define mmCRTC0_CRTC_FLOW_CONTROL … #define mmCRTC1_CRTC_FLOW_CONTROL … #define mmCRTC2_CRTC_FLOW_CONTROL … #define mmCRTC3_CRTC_FLOW_CONTROL … #define mmCRTC4_CRTC_FLOW_CONTROL … #define mmCRTC5_CRTC_FLOW_CONTROL … #define mmCRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC_AVSYNC_COUNTER … #define mmCRTC0_CRTC_AVSYNC_COUNTER … #define mmCRTC1_CRTC_AVSYNC_COUNTER … #define mmCRTC2_CRTC_AVSYNC_COUNTER … #define mmCRTC3_CRTC_AVSYNC_COUNTER … #define mmCRTC4_CRTC_AVSYNC_COUNTER … #define mmCRTC5_CRTC_AVSYNC_COUNTER … #define mmCRTC_CONTROL … #define mmCRTC0_CRTC_CONTROL … #define mmCRTC1_CRTC_CONTROL … #define mmCRTC2_CRTC_CONTROL … #define mmCRTC3_CRTC_CONTROL … #define mmCRTC4_CRTC_CONTROL … #define mmCRTC5_CRTC_CONTROL … #define mmCRTC_BLANK_CONTROL … #define mmCRTC0_CRTC_BLANK_CONTROL … #define mmCRTC1_CRTC_BLANK_CONTROL … #define mmCRTC2_CRTC_BLANK_CONTROL … #define mmCRTC3_CRTC_BLANK_CONTROL … #define mmCRTC4_CRTC_BLANK_CONTROL … #define mmCRTC5_CRTC_BLANK_CONTROL … #define mmCRTC_INTERLACE_CONTROL … #define mmCRTC0_CRTC_INTERLACE_CONTROL … #define mmCRTC1_CRTC_INTERLACE_CONTROL … #define mmCRTC2_CRTC_INTERLACE_CONTROL … #define mmCRTC3_CRTC_INTERLACE_CONTROL … #define mmCRTC4_CRTC_INTERLACE_CONTROL … #define mmCRTC5_CRTC_INTERLACE_CONTROL … #define mmCRTC_INTERLACE_STATUS … #define mmCRTC0_CRTC_INTERLACE_STATUS … #define mmCRTC1_CRTC_INTERLACE_STATUS … #define mmCRTC2_CRTC_INTERLACE_STATUS … #define mmCRTC3_CRTC_INTERLACE_STATUS … #define mmCRTC4_CRTC_INTERLACE_STATUS … #define mmCRTC5_CRTC_INTERLACE_STATUS … #define mmCRTC_FIELD_INDICATION_CONTROL … #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC_PIXEL_DATA_READBACK0 … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC_PIXEL_DATA_READBACK1 … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC_STATUS … #define mmCRTC0_CRTC_STATUS … #define mmCRTC1_CRTC_STATUS … #define mmCRTC2_CRTC_STATUS … #define mmCRTC3_CRTC_STATUS … #define mmCRTC4_CRTC_STATUS … #define mmCRTC5_CRTC_STATUS … #define mmCRTC_STATUS_POSITION … #define mmCRTC0_CRTC_STATUS_POSITION … #define mmCRTC1_CRTC_STATUS_POSITION … #define mmCRTC2_CRTC_STATUS_POSITION … #define mmCRTC3_CRTC_STATUS_POSITION … #define mmCRTC4_CRTC_STATUS_POSITION … #define mmCRTC5_CRTC_STATUS_POSITION … #define mmCRTC_NOM_VERT_POSITION … #define mmCRTC0_CRTC_NOM_VERT_POSITION … #define mmCRTC1_CRTC_NOM_VERT_POSITION … #define mmCRTC2_CRTC_NOM_VERT_POSITION … #define mmCRTC3_CRTC_NOM_VERT_POSITION … #define mmCRTC4_CRTC_NOM_VERT_POSITION … #define mmCRTC5_CRTC_NOM_VERT_POSITION … #define mmCRTC_STATUS_FRAME_COUNT … #define mmCRTC0_CRTC_STATUS_FRAME_COUNT … #define mmCRTC1_CRTC_STATUS_FRAME_COUNT … #define mmCRTC2_CRTC_STATUS_FRAME_COUNT … #define mmCRTC3_CRTC_STATUS_FRAME_COUNT … #define mmCRTC4_CRTC_STATUS_FRAME_COUNT … #define mmCRTC5_CRTC_STATUS_FRAME_COUNT … #define mmCRTC_STATUS_VF_COUNT … #define mmCRTC0_CRTC_STATUS_VF_COUNT … #define mmCRTC1_CRTC_STATUS_VF_COUNT … #define mmCRTC2_CRTC_STATUS_VF_COUNT … #define mmCRTC3_CRTC_STATUS_VF_COUNT … #define mmCRTC4_CRTC_STATUS_VF_COUNT … #define mmCRTC5_CRTC_STATUS_VF_COUNT … #define mmCRTC_STATUS_HV_COUNT … #define mmCRTC0_CRTC_STATUS_HV_COUNT … #define mmCRTC1_CRTC_STATUS_HV_COUNT … #define mmCRTC2_CRTC_STATUS_HV_COUNT … #define mmCRTC3_CRTC_STATUS_HV_COUNT … #define mmCRTC4_CRTC_STATUS_HV_COUNT … #define mmCRTC5_CRTC_STATUS_HV_COUNT … #define mmCRTC_COUNT_CONTROL … #define mmCRTC0_CRTC_COUNT_CONTROL … #define mmCRTC1_CRTC_COUNT_CONTROL … #define mmCRTC2_CRTC_COUNT_CONTROL … #define mmCRTC3_CRTC_COUNT_CONTROL … #define mmCRTC4_CRTC_COUNT_CONTROL … #define mmCRTC5_CRTC_COUNT_CONTROL … #define mmCRTC_COUNT_RESET … #define mmCRTC0_CRTC_COUNT_RESET … #define mmCRTC1_CRTC_COUNT_RESET … #define mmCRTC2_CRTC_COUNT_RESET … #define mmCRTC3_CRTC_COUNT_RESET … #define mmCRTC4_CRTC_COUNT_RESET … #define mmCRTC5_CRTC_COUNT_RESET … #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC_VERT_SYNC_CONTROL … #define mmCRTC0_CRTC_VERT_SYNC_CONTROL … #define mmCRTC1_CRTC_VERT_SYNC_CONTROL … #define mmCRTC2_CRTC_VERT_SYNC_CONTROL … #define mmCRTC3_CRTC_VERT_SYNC_CONTROL … #define mmCRTC4_CRTC_VERT_SYNC_CONTROL … #define mmCRTC5_CRTC_VERT_SYNC_CONTROL … #define mmCRTC_STEREO_STATUS … #define mmCRTC0_CRTC_STEREO_STATUS … #define mmCRTC1_CRTC_STEREO_STATUS … #define mmCRTC2_CRTC_STEREO_STATUS … #define mmCRTC3_CRTC_STEREO_STATUS … #define mmCRTC4_CRTC_STEREO_STATUS … #define mmCRTC5_CRTC_STEREO_STATUS … #define mmCRTC_STEREO_CONTROL … #define mmCRTC0_CRTC_STEREO_CONTROL … #define mmCRTC1_CRTC_STEREO_CONTROL … #define mmCRTC2_CRTC_STEREO_CONTROL … #define mmCRTC3_CRTC_STEREO_CONTROL … #define mmCRTC4_CRTC_STEREO_CONTROL … #define mmCRTC5_CRTC_STEREO_CONTROL … #define mmCRTC_SNAPSHOT_STATUS … #define mmCRTC0_CRTC_SNAPSHOT_STATUS … #define mmCRTC1_CRTC_SNAPSHOT_STATUS … #define mmCRTC2_CRTC_SNAPSHOT_STATUS … #define mmCRTC3_CRTC_SNAPSHOT_STATUS … #define mmCRTC4_CRTC_SNAPSHOT_STATUS … #define mmCRTC5_CRTC_SNAPSHOT_STATUS … #define mmCRTC_SNAPSHOT_CONTROL … #define mmCRTC0_CRTC_SNAPSHOT_CONTROL … #define mmCRTC1_CRTC_SNAPSHOT_CONTROL … #define mmCRTC2_CRTC_SNAPSHOT_CONTROL … #define mmCRTC3_CRTC_SNAPSHOT_CONTROL … #define mmCRTC4_CRTC_SNAPSHOT_CONTROL … #define mmCRTC5_CRTC_SNAPSHOT_CONTROL … #define mmCRTC_SNAPSHOT_POSITION … #define mmCRTC0_CRTC_SNAPSHOT_POSITION … #define mmCRTC1_CRTC_SNAPSHOT_POSITION … #define mmCRTC2_CRTC_SNAPSHOT_POSITION … #define mmCRTC3_CRTC_SNAPSHOT_POSITION … #define mmCRTC4_CRTC_SNAPSHOT_POSITION … #define mmCRTC5_CRTC_SNAPSHOT_POSITION … #define mmCRTC_SNAPSHOT_FRAME … #define mmCRTC0_CRTC_SNAPSHOT_FRAME … #define mmCRTC1_CRTC_SNAPSHOT_FRAME … #define mmCRTC2_CRTC_SNAPSHOT_FRAME … #define mmCRTC3_CRTC_SNAPSHOT_FRAME … #define mmCRTC4_CRTC_SNAPSHOT_FRAME … #define mmCRTC5_CRTC_SNAPSHOT_FRAME … #define mmCRTC_START_LINE_CONTROL … #define mmCRTC0_CRTC_START_LINE_CONTROL … #define mmCRTC1_CRTC_START_LINE_CONTROL … #define mmCRTC2_CRTC_START_LINE_CONTROL … #define mmCRTC3_CRTC_START_LINE_CONTROL … #define mmCRTC4_CRTC_START_LINE_CONTROL … #define mmCRTC5_CRTC_START_LINE_CONTROL … #define mmCRTC_INTERRUPT_CONTROL … #define mmCRTC0_CRTC_INTERRUPT_CONTROL … #define mmCRTC1_CRTC_INTERRUPT_CONTROL … #define mmCRTC2_CRTC_INTERRUPT_CONTROL … #define mmCRTC3_CRTC_INTERRUPT_CONTROL … #define mmCRTC4_CRTC_INTERRUPT_CONTROL … #define mmCRTC5_CRTC_INTERRUPT_CONTROL … #define mmCRTC_UPDATE_LOCK … #define mmCRTC0_CRTC_UPDATE_LOCK … #define mmCRTC1_CRTC_UPDATE_LOCK … #define mmCRTC2_CRTC_UPDATE_LOCK … #define mmCRTC3_CRTC_UPDATE_LOCK … #define mmCRTC4_CRTC_UPDATE_LOCK … #define mmCRTC5_CRTC_UPDATE_LOCK … #define mmCRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC_TEST_PATTERN_CONTROL … #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC_TEST_PATTERN_COLOR … #define mmCRTC0_CRTC_TEST_PATTERN_COLOR … #define mmCRTC1_CRTC_TEST_PATTERN_COLOR … #define mmCRTC2_CRTC_TEST_PATTERN_COLOR … #define mmCRTC3_CRTC_TEST_PATTERN_COLOR … #define mmCRTC4_CRTC_TEST_PATTERN_COLOR … #define mmCRTC5_CRTC_TEST_PATTERN_COLOR … #define mmCRTC_MASTER_UPDATE_LOCK … #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC_MASTER_UPDATE_MODE … #define mmCRTC0_CRTC_MASTER_UPDATE_MODE … #define mmCRTC1_CRTC_MASTER_UPDATE_MODE … #define mmCRTC2_CRTC_MASTER_UPDATE_MODE … #define mmCRTC3_CRTC_MASTER_UPDATE_MODE … #define mmCRTC4_CRTC_MASTER_UPDATE_MODE … #define mmCRTC5_CRTC_MASTER_UPDATE_MODE … #define mmCRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC_MVP_STATUS … #define mmCRTC0_CRTC_MVP_STATUS … #define mmCRTC1_CRTC_MVP_STATUS … #define mmCRTC2_CRTC_MVP_STATUS … #define mmCRTC3_CRTC_MVP_STATUS … #define mmCRTC4_CRTC_MVP_STATUS … #define mmCRTC5_CRTC_MVP_STATUS … #define mmCRTC_MASTER_EN … #define mmCRTC0_CRTC_MASTER_EN … #define mmCRTC1_CRTC_MASTER_EN … #define mmCRTC2_CRTC_MASTER_EN … #define mmCRTC3_CRTC_MASTER_EN … #define mmCRTC4_CRTC_MASTER_EN … #define mmCRTC5_CRTC_MASTER_EN … #define mmCRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC_V_UPDATE_INT_STATUS … #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC_OVERSCAN_COLOR … #define mmCRTC0_CRTC_OVERSCAN_COLOR … #define mmCRTC1_CRTC_OVERSCAN_COLOR … #define mmCRTC2_CRTC_OVERSCAN_COLOR … #define mmCRTC3_CRTC_OVERSCAN_COLOR … #define mmCRTC4_CRTC_OVERSCAN_COLOR … #define mmCRTC5_CRTC_OVERSCAN_COLOR … #define mmCRTC_OVERSCAN_COLOR_EXT … #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC_BLANK_DATA_COLOR … #define mmCRTC0_CRTC_BLANK_DATA_COLOR … #define mmCRTC1_CRTC_BLANK_DATA_COLOR … #define mmCRTC2_CRTC_BLANK_DATA_COLOR … #define mmCRTC3_CRTC_BLANK_DATA_COLOR … #define mmCRTC4_CRTC_BLANK_DATA_COLOR … #define mmCRTC5_CRTC_BLANK_DATA_COLOR … #define mmCRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC_BLACK_COLOR … #define mmCRTC0_CRTC_BLACK_COLOR … #define mmCRTC1_CRTC_BLACK_COLOR … #define mmCRTC2_CRTC_BLACK_COLOR … #define mmCRTC3_CRTC_BLACK_COLOR … #define mmCRTC4_CRTC_BLACK_COLOR … #define mmCRTC5_CRTC_BLACK_COLOR … #define mmCRTC_BLACK_COLOR_EXT … #define mmCRTC0_CRTC_BLACK_COLOR_EXT … #define mmCRTC1_CRTC_BLACK_COLOR_EXT … #define mmCRTC2_CRTC_BLACK_COLOR_EXT … #define mmCRTC3_CRTC_BLACK_COLOR_EXT … #define mmCRTC4_CRTC_BLACK_COLOR_EXT … #define mmCRTC5_CRTC_BLACK_COLOR_EXT … #define mmCRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC_CRC_CNTL … #define mmCRTC0_CRTC_CRC_CNTL … #define mmCRTC1_CRTC_CRC_CNTL … #define mmCRTC2_CRTC_CRC_CNTL … #define mmCRTC3_CRTC_CRC_CNTL … #define mmCRTC4_CRTC_CRC_CNTL … #define mmCRTC5_CRTC_CRC_CNTL … #define mmCRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC_CRC0_DATA_RG … #define mmCRTC0_CRTC_CRC0_DATA_RG … #define mmCRTC1_CRTC_CRC0_DATA_RG … #define mmCRTC2_CRTC_CRC0_DATA_RG … #define mmCRTC3_CRTC_CRC0_DATA_RG … #define mmCRTC4_CRTC_CRC0_DATA_RG … #define mmCRTC5_CRTC_CRC0_DATA_RG … #define mmCRTC_CRC0_DATA_B … #define mmCRTC0_CRTC_CRC0_DATA_B … #define mmCRTC1_CRTC_CRC0_DATA_B … #define mmCRTC2_CRTC_CRC0_DATA_B … #define mmCRTC3_CRTC_CRC0_DATA_B … #define mmCRTC4_CRTC_CRC0_DATA_B … #define mmCRTC5_CRTC_CRC0_DATA_B … #define mmCRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC_CRC1_DATA_RG … #define mmCRTC0_CRTC_CRC1_DATA_RG … #define mmCRTC1_CRTC_CRC1_DATA_RG … #define mmCRTC2_CRTC_CRC1_DATA_RG … #define mmCRTC3_CRTC_CRC1_DATA_RG … #define mmCRTC4_CRTC_CRC1_DATA_RG … #define mmCRTC5_CRTC_CRC1_DATA_RG … #define mmCRTC_CRC1_DATA_B … #define mmCRTC0_CRTC_CRC1_DATA_B … #define mmCRTC1_CRTC_CRC1_DATA_B … #define mmCRTC2_CRTC_CRC1_DATA_B … #define mmCRTC3_CRTC_CRC1_DATA_B … #define mmCRTC4_CRTC_CRC1_DATA_B … #define mmCRTC5_CRTC_CRC1_DATA_B … #define mmCRTC_STATIC_SCREEN_CONTROL … #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC_3D_STRUCTURE_CONTROL … #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC_GSL_VSYNC_GAP … #define mmCRTC0_CRTC_GSL_VSYNC_GAP … #define mmCRTC1_CRTC_GSL_VSYNC_GAP … #define mmCRTC2_CRTC_GSL_VSYNC_GAP … #define mmCRTC3_CRTC_GSL_VSYNC_GAP … #define mmCRTC4_CRTC_GSL_VSYNC_GAP … #define mmCRTC5_CRTC_GSL_VSYNC_GAP … #define mmCRTC_GSL_WINDOW … #define mmCRTC0_CRTC_GSL_WINDOW … #define mmCRTC1_CRTC_GSL_WINDOW … #define mmCRTC2_CRTC_GSL_WINDOW … #define mmCRTC3_CRTC_GSL_WINDOW … #define mmCRTC4_CRTC_GSL_WINDOW … #define mmCRTC5_CRTC_GSL_WINDOW … #define mmCRTC_GSL_CONTROL … #define mmCRTC0_CRTC_GSL_CONTROL … #define mmCRTC1_CRTC_GSL_CONTROL … #define mmCRTC2_CRTC_GSL_CONTROL … #define mmCRTC3_CRTC_GSL_CONTROL … #define mmCRTC4_CRTC_GSL_CONTROL … #define mmCRTC5_CRTC_GSL_CONTROL … #define mmCRTC_TEST_DEBUG_INDEX … #define mmCRTC0_CRTC_TEST_DEBUG_INDEX … #define mmCRTC1_CRTC_TEST_DEBUG_INDEX … #define mmCRTC2_CRTC_TEST_DEBUG_INDEX … #define mmCRTC3_CRTC_TEST_DEBUG_INDEX … #define mmCRTC4_CRTC_TEST_DEBUG_INDEX … #define mmCRTC5_CRTC_TEST_DEBUG_INDEX … #define mmCRTC_TEST_DEBUG_DATA … #define mmCRTC0_CRTC_TEST_DEBUG_DATA … #define mmCRTC1_CRTC_TEST_DEBUG_DATA … #define mmCRTC2_CRTC_TEST_DEBUG_DATA … #define mmCRTC3_CRTC_TEST_DEBUG_DATA … #define mmCRTC4_CRTC_TEST_DEBUG_DATA … #define mmCRTC5_CRTC_TEST_DEBUG_DATA … #define mmDAC_ENABLE … #define mmDAC_SOURCE_SELECT … #define mmDAC_CRC_EN … #define mmDAC_CRC_CONTROL … #define mmDAC_CRC_SIG_RGB_MASK … #define mmDAC_CRC_SIG_CONTROL_MASK … #define mmDAC_CRC_SIG_RGB … #define mmDAC_CRC_SIG_CONTROL … #define mmDAC_SYNC_TRISTATE_CONTROL … #define mmDAC_STEREOSYNC_SELECT … #define mmDAC_AUTODETECT_CONTROL … #define mmDAC_AUTODETECT_CONTROL2 … #define mmDAC_AUTODETECT_CONTROL3 … #define mmDAC_AUTODETECT_STATUS … #define mmDAC_AUTODETECT_INT_CONTROL … #define mmDAC_FORCE_OUTPUT_CNTL … #define mmDAC_FORCE_DATA … #define mmDAC_POWERDOWN … #define mmDAC_CONTROL … #define mmDAC_COMPARATOR_ENABLE … #define mmDAC_COMPARATOR_OUTPUT … #define mmDAC_PWR_CNTL … #define mmDAC_DFT_CONFIG … #define mmDAC_FIFO_STATUS … #define mmDAC_TEST_DEBUG_INDEX … #define mmDAC_TEST_DEBUG_DATA … #define mmPERFCOUNTER_CNTL … #define mmDC_PERFMON0_PERFCOUNTER_CNTL … #define mmDC_PERFMON1_PERFCOUNTER_CNTL … #define mmDC_PERFMON2_PERFCOUNTER_CNTL … #define mmDC_PERFMON3_PERFCOUNTER_CNTL … #define mmDC_PERFMON4_PERFCOUNTER_CNTL … #define mmDC_PERFMON5_PERFCOUNTER_CNTL … #define mmDC_PERFMON6_PERFCOUNTER_CNTL … #define mmDC_PERFMON7_PERFCOUNTER_CNTL … #define mmDC_PERFMON8_PERFCOUNTER_CNTL … #define mmDC_PERFMON9_PERFCOUNTER_CNTL … #define mmDC_PERFMON10_PERFCOUNTER_CNTL … #define mmDC_PERFMON11_PERFCOUNTER_CNTL … #define mmPERFCOUNTER_STATE … #define mmDC_PERFMON0_PERFCOUNTER_STATE … #define mmDC_PERFMON1_PERFCOUNTER_STATE … #define mmDC_PERFMON2_PERFCOUNTER_STATE … #define mmDC_PERFMON3_PERFCOUNTER_STATE … #define mmDC_PERFMON4_PERFCOUNTER_STATE … #define mmDC_PERFMON5_PERFCOUNTER_STATE … #define mmDC_PERFMON6_PERFCOUNTER_STATE … #define mmDC_PERFMON7_PERFCOUNTER_STATE … #define mmDC_PERFMON8_PERFCOUNTER_STATE … #define mmDC_PERFMON9_PERFCOUNTER_STATE … #define mmDC_PERFMON10_PERFCOUNTER_STATE … #define mmDC_PERFMON11_PERFCOUNTER_STATE … #define mmPERFMON_CNTL … #define mmDC_PERFMON0_PERFMON_CNTL … #define mmDC_PERFMON1_PERFMON_CNTL … #define mmDC_PERFMON2_PERFMON_CNTL … #define mmDC_PERFMON3_PERFMON_CNTL … #define mmDC_PERFMON4_PERFMON_CNTL … #define mmDC_PERFMON5_PERFMON_CNTL … #define mmDC_PERFMON6_PERFMON_CNTL … #define mmDC_PERFMON7_PERFMON_CNTL … #define mmDC_PERFMON8_PERFMON_CNTL … #define mmDC_PERFMON9_PERFMON_CNTL … #define mmDC_PERFMON10_PERFMON_CNTL … #define mmDC_PERFMON11_PERFMON_CNTL … #define mmPERFMON_CNTL2 … #define mmDC_PERFMON0_PERFMON_CNTL2 … #define mmDC_PERFMON1_PERFMON_CNTL2 … #define mmDC_PERFMON2_PERFMON_CNTL2 … #define mmDC_PERFMON3_PERFMON_CNTL2 … #define mmDC_PERFMON4_PERFMON_CNTL2 … #define mmDC_PERFMON5_PERFMON_CNTL2 … #define mmDC_PERFMON6_PERFMON_CNTL2 … #define mmDC_PERFMON7_PERFMON_CNTL2 … #define mmDC_PERFMON8_PERFMON_CNTL2 … #define mmDC_PERFMON9_PERFMON_CNTL2 … #define mmDC_PERFMON10_PERFMON_CNTL2 … #define mmDC_PERFMON11_PERFMON_CNTL2 … #define mmPERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC … #define mmPERFMON_CVALUE_LOW … #define mmDC_PERFMON0_PERFMON_CVALUE_LOW … #define mmDC_PERFMON1_PERFMON_CVALUE_LOW … #define mmDC_PERFMON2_PERFMON_CVALUE_LOW … #define mmDC_PERFMON3_PERFMON_CVALUE_LOW … #define mmDC_PERFMON4_PERFMON_CVALUE_LOW … #define mmDC_PERFMON5_PERFMON_CVALUE_LOW … #define mmDC_PERFMON6_PERFMON_CVALUE_LOW … #define mmDC_PERFMON7_PERFMON_CVALUE_LOW … #define mmDC_PERFMON8_PERFMON_CVALUE_LOW … #define mmDC_PERFMON9_PERFMON_CVALUE_LOW … #define mmDC_PERFMON10_PERFMON_CVALUE_LOW … #define mmDC_PERFMON11_PERFMON_CVALUE_LOW … #define mmPERFMON_HI … #define mmDC_PERFMON0_PERFMON_HI … #define mmDC_PERFMON1_PERFMON_HI … #define mmDC_PERFMON2_PERFMON_HI … #define mmDC_PERFMON3_PERFMON_HI … #define mmDC_PERFMON4_PERFMON_HI … #define mmDC_PERFMON5_PERFMON_HI … #define mmDC_PERFMON6_PERFMON_HI … #define mmDC_PERFMON7_PERFMON_HI … #define mmDC_PERFMON8_PERFMON_HI … #define mmDC_PERFMON9_PERFMON_HI … #define mmDC_PERFMON10_PERFMON_HI … #define mmDC_PERFMON11_PERFMON_HI … #define mmPERFMON_LOW … #define mmDC_PERFMON0_PERFMON_LOW … #define mmDC_PERFMON1_PERFMON_LOW … #define mmDC_PERFMON2_PERFMON_LOW … #define mmDC_PERFMON3_PERFMON_LOW … #define mmDC_PERFMON4_PERFMON_LOW … #define mmDC_PERFMON5_PERFMON_LOW … #define mmDC_PERFMON6_PERFMON_LOW … #define mmDC_PERFMON7_PERFMON_LOW … #define mmDC_PERFMON8_PERFMON_LOW … #define mmDC_PERFMON9_PERFMON_LOW … #define mmDC_PERFMON10_PERFMON_LOW … #define mmDC_PERFMON11_PERFMON_LOW … #define mmPERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX … #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX … #define mmPERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA … #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA … #define mmREFCLK_CNTL … #define mmDCCG_CBUS_WRCMD_DELAY … #define mmDPREFCLK_CNTL … #define mmDCE_VERSION … #define mmAVSYNC_COUNTER_WRITE … #define mmAVSYNC_COUNTER_CONTROL … #define mmAVSYNC_COUNTER_READ … #define mmDCCG_GTC_CNTL … #define mmDCCG_GTC_DTO_INCR … #define mmDCCG_GTC_DTO_MODULO … #define mmDCCG_GTC_CURRENT … #define mmDCCG_DS_DTO_INCR … #define mmDCCG_DS_DTO_MODULO … #define mmDCCG_DS_CNTL … #define mmDCCG_DS_HW_CAL_INTERVAL … #define mmDCCG_DS_DEBUG_CNTL … #define mmDMCU_SMU_INTERRUPT_CNTL … #define mmSMU_CONTROL … #define mmSMU_INTERRUPT_CONTROL … #define mmDAC_CLK_ENABLE … #define mmDVO_CLK_ENABLE … #define mmDCCG_GATE_DISABLE_CNTL … #define mmDCCG_GATE_DISABLE_CNTL2 … #define mmDISPCLK_CGTT_BLK_CTRL_REG … #define mmSCLK_CGTT_BLK_CTRL_REG … #define mmDPREFCLK_CGTT_BLK_CTRL_REG … #define mmREFCLK_CGTT_BLK_CTRL_REG … #define mmSYMCLK_CGTT_BLK_CTRL_REG … #define mmDCCG_CAC_STATUS … #define mmPIXCLK1_RESYNC_CNTL … #define mmPIXCLK2_RESYNC_CNTL … #define mmPIXCLK0_RESYNC_CNTL … #define mmPHYPLL_PIXCLK_CNTL … #define mmMICROSECOND_TIME_BASE_DIV … #define mmDCCG_DISP_CNTL_REG … #define mmMILLISECOND_TIME_BASE_DIV … #define mmDISPCLK_FREQ_CHANGE_CNTL … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL … #define mmDCCG_PERFMON_CNTL … #define mmDCCG_PERFMON_CNTL2 … #define mmCRTC0_PIXEL_RATE_CNTL … #define mmDP_DTO0_PHASE … #define mmDP_DTO0_MODULO … #define mmCRTC1_PIXEL_RATE_CNTL … #define mmDP_DTO1_PHASE … #define mmDP_DTO1_MODULO … #define mmCRTC2_PIXEL_RATE_CNTL … #define mmDP_DTO2_PHASE … #define mmDP_DTO2_MODULO … #define mmCRTC3_PIXEL_RATE_CNTL … #define mmDP_DTO3_PHASE … #define mmDP_DTO3_MODULO … #define mmCRTC4_PIXEL_RATE_CNTL … #define mmDP_DTO4_PHASE … #define mmDP_DTO4_MODULO … #define mmCRTC5_PIXEL_RATE_CNTL … #define mmDP_DTO5_PHASE … #define mmDP_DTO5_MODULO … #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL … #define mmDCCG_SOFT_RESET … #define mmSYMCLKA_CLOCK_ENABLE … #define mmSYMCLKB_CLOCK_ENABLE … #define mmSYMCLKC_CLOCK_ENABLE … #define mmSYMCLKD_CLOCK_ENABLE … #define mmSYMCLKE_CLOCK_ENABLE … #define mmSYMCLKF_CLOCK_ENABLE … #define mmSYMCLKG_CLOCK_ENABLE … #define mmDPDBG_CLK_FORCE_CONTROL … #define mmDCCG_AUDIO_DTO_SOURCE … #define mmDCCG_AUDIO_DTO0_PHASE … #define mmDCCG_AUDIO_DTO0_MODULE … #define mmDCCG_AUDIO_DTO1_PHASE … #define mmDCCG_AUDIO_DTO1_MODULE … #define mmDCCG_TEST_DEBUG_INDEX … #define mmDCCG_TEST_DEBUG_DATA … #define mmDCCG_TEST_CLK_SEL … #define mmCPLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 … #define mmCPLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 … #define mmCPLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 … #define mmCPLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 … #define mmCPLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 … #define mmCPLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 … #define mmCPLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 … #define mmCPLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 … #define mmCPLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 … #define mmCPLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 … #define mmCPLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 … #define mmCPLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 … #define mmPLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 … #define mmPLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 … #define mmPLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 … #define mmPLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 … #define mmPLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 … #define mmPLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 … #define mmPLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 … #define mmPLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 … #define mmPLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 … #define mmPLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 … #define mmPLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 … #define mmPLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 … #define mmPLL_MACRO_CNTL_RESERVED12 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 … #define mmPLL_MACRO_CNTL_RESERVED13 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 … #define mmPLL_MACRO_CNTL_RESERVED14 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 … #define mmPLL_MACRO_CNTL_RESERVED15 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 … #define mmPLL_MACRO_CNTL_RESERVED16 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 … #define mmPLL_MACRO_CNTL_RESERVED17 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 … #define mmPLL_MACRO_CNTL_RESERVED18 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 … #define mmPLL_MACRO_CNTL_RESERVED19 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 … #define mmPLL_MACRO_CNTL_RESERVED20 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 … #define mmPLL_MACRO_CNTL_RESERVED21 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 … #define mmPLL_MACRO_CNTL_RESERVED22 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 … #define mmPLL_MACRO_CNTL_RESERVED23 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 … #define mmPLL_MACRO_CNTL_RESERVED24 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 … #define mmPLL_MACRO_CNTL_RESERVED25 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 … #define mmPLL_MACRO_CNTL_RESERVED26 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 … #define mmPLL_MACRO_CNTL_RESERVED27 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 … #define mmPLL_MACRO_CNTL_RESERVED28 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 … #define mmPLL_MACRO_CNTL_RESERVED29 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 … #define mmPLL_MACRO_CNTL_RESERVED30 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 … #define mmPLL_MACRO_CNTL_RESERVED31 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 … #define mmPLL_MACRO_CNTL_RESERVED32 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 … #define mmPLL_MACRO_CNTL_RESERVED33 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 … #define mmPLL_MACRO_CNTL_RESERVED34 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 … #define mmPLL_MACRO_CNTL_RESERVED35 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 … #define mmPLL_MACRO_CNTL_RESERVED36 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 … #define mmPLL_MACRO_CNTL_RESERVED37 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 … #define mmPLL_MACRO_CNTL_RESERVED38 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 … #define mmPLL_MACRO_CNTL_RESERVED39 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 … #define mmPLL_MACRO_CNTL_RESERVED40 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 … #define mmPLL_MACRO_CNTL_RESERVED41 … #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 … #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 … #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 … #define mmDENTIST_DISPCLK_CNTL … #define mmDCDEBUG_BUS_CLK1_SEL … #define mmDCDEBUG_BUS_CLK2_SEL … #define mmDCDEBUG_BUS_CLK3_SEL … #define mmDCDEBUG_BUS_CLK4_SEL … #define mmDCDEBUG_BUS_CLK5_SEL … #define mmDCDEBUG_OUT_PIN_OVERRIDE … #define mmDCDEBUG_OUT_CNTL … #define mmDCDEBUG_OUT_DATA … #define mmDMIF_ADDR_CONFIG … #define mmDMIF_CONTROL … #define mmDMIF_STATUS … #define mmDMIF_HW_DEBUG … #define mmDMIF_ARBITRATION_CONTROL … #define mmPIPE0_ARBITRATION_CONTROL3 … #define mmPIPE1_ARBITRATION_CONTROL3 … #define mmPIPE2_ARBITRATION_CONTROL3 … #define mmPIPE3_ARBITRATION_CONTROL3 … #define mmPIPE4_ARBITRATION_CONTROL3 … #define mmPIPE5_ARBITRATION_CONTROL3 … #define mmPIPE6_ARBITRATION_CONTROL3 … #define mmPIPE7_ARBITRATION_CONTROL3 … #define mmDMIF_P_VMID … #define mmDMIF_URG_OVERRIDE … #define mmDMIF_TEST_DEBUG_INDEX … #define mmDMIF_TEST_DEBUG_DATA … #define ixDMIF_DEBUG02_CORE0 … #define ixDMIF_DEBUG02_CORE1 … #define mmDMIF_ADDR_CALC … #define mmDMIF_STATUS2 … #define mmPIPE0_MAX_REQUESTS … #define mmPIPE1_MAX_REQUESTS … #define mmPIPE2_MAX_REQUESTS … #define mmPIPE3_MAX_REQUESTS … #define mmPIPE4_MAX_REQUESTS … #define mmPIPE5_MAX_REQUESTS … #define mmPIPE6_MAX_REQUESTS … #define mmPIPE7_MAX_REQUESTS … #define mmDVMM_REG_RD_STATUS … #define mmDVMM_REG_RD_DATA … #define mmDVMM_PTE_REQ … #define mmDVMM_CNTL … #define mmDVMM_FAULT_STATUS … #define mmDVMM_FAULT_ADDR … #define mmLOW_POWER_TILING_CONTROL … #define mmMCIF_CONTROL … #define mmMCIF_WRITE_COMBINE_CONTROL … #define mmMCIF_TEST_DEBUG_INDEX … #define mmMCIF_TEST_DEBUG_DATA … #define ixIDDCCIF02_DBG_DCCIF_C … #define ixIDDCCIF04_DBG_DCCIF_E … #define ixIDDCCIF05_DBG_DCCIF_F … #define mmMCIF_VMID … #define mmMCIF_MEM_CONTROL … #define mmCC_DC_PIPE_DIS … #define mmMC_DC_INTERFACE_NACK_STATUS … #define mmRBBMIF_TIMEOUT … #define mmRBBMIF_STATUS … #define mmRBBMIF_TIMEOUT_DIS … #define mmRBBMIF_STATUS_FLAG … #define mmDCI_MEM_PWR_STATUS … #define mmDCI_MEM_PWR_STATUS2 … #define mmDCI_CLK_CNTL … #define mmDCI_CLK_RAMP_CNTL … #define mmDCI_MEM_PWR_CNTL … #define mmDCI_MEM_PWR_CNTL2 … #define mmDCI_MEM_PWR_CNTL3 … #define mmDVMM_PTE_PGMEM_CONTROL … #define mmDVMM_PTE_PGMEM_STATE … #define mmDCI_SOFT_RESET … #define mmDCI_MISC … #define mmDCI_TEST_DEBUG_INDEX … #define mmDCI_TEST_DEBUG_DATA … #define mmDCI_DEBUG_CONFIG … #define mmPIPE0_DMIF_BUFFER_CONTROL … #define mmPIPE1_DMIF_BUFFER_CONTROL … #define mmPIPE2_DMIF_BUFFER_CONTROL … #define mmPIPE3_DMIF_BUFFER_CONTROL … #define mmPIPE4_DMIF_BUFFER_CONTROL … #define mmPIPE5_DMIF_BUFFER_CONTROL … #define mmDC_GENERICA … #define mmDC_GENERICB … #define mmDC_PAD_EXTERN_SIG … #define mmDC_REF_CLK_CNTL … #define mmDC_GPIO_DEBUG … #define mmUNIPHYA_LINK_CNTL … #define mmUNIPHYB_LINK_CNTL … #define mmUNIPHYC_LINK_CNTL … #define mmUNIPHYD_LINK_CNTL … #define mmUNIPHYE_LINK_CNTL … #define mmUNIPHYF_LINK_CNTL … #define mmUNIPHYG_LINK_CNTL … #define mmUNIPHYA_CHANNEL_XBAR_CNTL … #define mmUNIPHYB_CHANNEL_XBAR_CNTL … #define mmUNIPHYC_CHANNEL_XBAR_CNTL … #define mmUNIPHYD_CHANNEL_XBAR_CNTL … #define mmUNIPHYE_CHANNEL_XBAR_CNTL … #define mmUNIPHYF_CHANNEL_XBAR_CNTL … #define mmUNIPHYG_CHANNEL_XBAR_CNTL … #define mmUNIPHYLPA_LINK_CNTL … #define mmUNIPHYLPB_LINK_CNTL … #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL … #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL … #define mmUNIPHY_IMPCAL_LINKA … #define mmUNIPHY_IMPCAL_LINKB … #define mmUNIPHY_IMPCAL_LINKC … #define mmUNIPHY_IMPCAL_LINKD … #define mmUNIPHY_IMPCAL_LINKE … #define mmUNIPHY_IMPCAL_LINKF … #define mmUNIPHY_IMPCAL_PERIOD … #define mmAUXP_IMPCAL … #define mmAUXN_IMPCAL … #define mmDCIO_IMPCAL_CNTL … #define mmUNIPHY_IMPCAL_PSW_AB … #define mmDCIO_IMPCAL_CNTL_CD … #define mmUNIPHY_IMPCAL_PSW_CD … #define mmDCIO_IMPCAL_CNTL_EF … #define mmUNIPHY_IMPCAL_PSW_EF … #define mmDCIO_WRCMD_DELAY … #define mmDC_PINSTRAPS … #define mmDC_DVODATA_CONFIG … #define mmLVTMA_PWRSEQ_CNTL … #define mmLVTMA_PWRSEQ_STATE … #define mmLVTMA_PWRSEQ_REF_DIV … #define mmLVTMA_PWRSEQ_DELAY1 … #define mmLVTMA_PWRSEQ_DELAY2 … #define mmBL_PWM_CNTL … #define mmBL_PWM_CNTL2 … #define mmBL_PWM_PERIOD_CNTL … #define mmBL_PWM_GRP1_REG_LOCK … #define mmDCIO_GSL_GENLK_PAD_CNTL … #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL … #define mmDCIO_GSL0_CNTL … #define mmDCIO_GSL1_CNTL … #define mmDCIO_GSL2_CNTL … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE … #define mmDC_GPU_TIMER_START_POSITION_P_FLIP … #define mmDC_GPU_TIMER_READ … #define mmDC_GPU_TIMER_READ_CNTL … #define mmDCIO_CLOCK_CNTL … #define mmDCIO_DEBUG … #define mmDCO_DCFE_EXT_VSYNC_CNTL … #define mmDBG_OUT_CNTL … #define mmDCIO_DEBUG_CONFIG … #define mmDCIO_SOFT_RESET … #define mmDCIO_DPHY_SEL … #define mmDCIO_TEST_DEBUG_INDEX … #define mmDCIO_TEST_DEBUG_DATA … #define ixDCIO_DEBUG1 … #define ixDCIO_DEBUG2 … #define ixDCIO_DEBUG3 … #define ixDCIO_DEBUG4 … #define ixDCIO_DEBUG5 … #define ixDCIO_DEBUG6 … #define ixDCIO_DEBUG7 … #define ixDCIO_DEBUG8 … #define ixDCIO_DEBUG9 … #define ixDCIO_DEBUGA … #define ixDCIO_DEBUGB … #define ixDCIO_DEBUGC … #define ixDCIO_DEBUGD … #define ixDCIO_DEBUGE … #define ixDCIO_DEBUGF … #define ixDCIO_DEBUG10 … #define ixDCIO_DEBUG11 … #define ixDCIO_DEBUG12 … #define ixDCIO_DEBUG13 … #define ixDCIO_DEBUG14 … #define ixDCIO_DEBUG15 … #define ixDCIO_DEBUG16 … #define ixDCIO_DEBUG17 … #define ixDCIO_DEBUG18 … #define ixDCIO_DEBUG19 … #define ixDCIO_DEBUG1A … #define ixDCIO_DEBUG1B … #define ixDCIO_DEBUG_ID … #define mmDC_GPIO_GENERIC_MASK … #define mmDC_GPIO_GENERIC_A … #define mmDC_GPIO_GENERIC_EN … #define mmDC_GPIO_GENERIC_Y … #define mmDC_GPIO_DVODATA_MASK … #define mmDC_GPIO_DVODATA_A … #define mmDC_GPIO_DVODATA_EN … #define mmDC_GPIO_DVODATA_Y … #define mmDC_GPIO_DDC1_MASK … #define mmDC_GPIO_DDC1_A … #define mmDC_GPIO_DDC1_EN … #define mmDC_GPIO_DDC1_Y … #define mmDC_GPIO_DDC2_MASK … #define mmDC_GPIO_DDC2_A … #define mmDC_GPIO_DDC2_EN … #define mmDC_GPIO_DDC2_Y … #define mmDC_GPIO_DDC3_MASK … #define mmDC_GPIO_DDC3_A … #define mmDC_GPIO_DDC3_EN … #define mmDC_GPIO_DDC3_Y … #define mmDC_GPIO_DDC4_MASK … #define mmDC_GPIO_DDC4_A … #define mmDC_GPIO_DDC4_EN … #define mmDC_GPIO_DDC4_Y … #define mmDC_GPIO_DDC5_MASK … #define mmDC_GPIO_DDC5_A … #define mmDC_GPIO_DDC5_EN … #define mmDC_GPIO_DDC5_Y … #define mmDC_GPIO_DDC6_MASK … #define mmDC_GPIO_DDC6_A … #define mmDC_GPIO_DDC6_EN … #define mmDC_GPIO_DDC6_Y … #define mmDC_GPIO_DDCVGA_MASK … #define mmDC_GPIO_DDCVGA_A … #define mmDC_GPIO_DDCVGA_EN … #define mmDC_GPIO_DDCVGA_Y … #define mmDC_GPIO_SYNCA_MASK … #define mmDC_GPIO_SYNCA_A … #define mmDC_GPIO_SYNCA_EN … #define mmDC_GPIO_SYNCA_Y … #define mmDC_GPIO_GENLK_MASK … #define mmDC_GPIO_GENLK_A … #define mmDC_GPIO_GENLK_EN … #define mmDC_GPIO_GENLK_Y … #define mmDC_GPIO_HPD_MASK … #define mmDC_GPIO_HPD_A … #define mmDC_GPIO_HPD_EN … #define mmDC_GPIO_HPD_Y … #define mmDC_GPIO_PWRSEQ_MASK … #define mmDC_GPIO_PWRSEQ_A … #define mmDC_GPIO_PWRSEQ_EN … #define mmDC_GPIO_PWRSEQ_Y … #define mmDC_GPIO_PAD_STRENGTH_1 … #define mmDC_GPIO_PAD_STRENGTH_2 … #define mmPHY_AUX_CNTL … #define mmDC_GPIO_I2CPAD_MASK … #define mmDC_GPIO_I2CPAD_A … #define mmDC_GPIO_I2CPAD_EN … #define mmDC_GPIO_I2CPAD_Y … #define mmDC_GPIO_I2CPAD_STRENGTH … #define mmDVO_VREF_CONTROL … #define mmDVO_SKEW_ADJUST … #define mmDAC_MACRO_CNTL_RESERVED0 … #define mmDAC_MACRO_CNTL_RESERVED1 … #define mmDAC_MACRO_CNTL_RESERVED2 … #define mmDAC_MACRO_CNTL_RESERVED3 … #define mmUNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmUNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmUNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmUNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmUNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmUNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmUNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmUNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmUNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmUNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmUNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmUNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmUNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmUNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmUNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmUNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmUNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmUNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmUNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmUNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmUNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmUNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmUNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmUNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmUNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmUNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmUNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmUNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmUNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmUNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmUNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmUNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED0 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED1 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED2 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED3 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED4 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED5 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED6 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED7 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED8 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED9 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED10 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED11 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED12 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED13 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED14 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED15 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED16 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED17 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED18 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED19 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED20 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED21 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED22 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED23 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED24 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED25 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED26 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED27 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED28 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED29 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED30 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED31 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED32 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED33 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED34 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED35 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED36 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED37 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED38 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED39 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED40 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED41 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED42 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED43 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED44 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED45 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED46 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED47 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED48 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED49 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED50 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED51 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED52 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED53 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED54 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED55 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED56 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED57 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED58 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED59 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED60 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED61 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED62 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED63 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED64 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED65 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED66 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED67 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED68 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED69 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED70 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED71 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED72 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED73 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED74 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED75 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED76 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED77 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED78 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED79 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED80 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED81 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED82 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED83 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED84 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED85 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED86 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED87 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED88 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED89 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED90 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED91 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED92 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED93 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED94 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED95 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED96 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED97 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED98 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED99 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED100 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED101 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED102 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED103 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED104 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED105 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED106 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED107 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED108 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED109 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED110 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED111 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED112 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED113 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED114 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED115 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED116 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED117 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED118 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED119 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED120 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED121 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED122 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED123 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED124 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED125 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED126 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED127 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED128 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED129 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED130 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED131 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED132 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED133 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED134 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED135 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED136 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED137 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED138 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED139 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED140 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED141 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED142 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED143 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED144 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED145 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED146 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED147 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED148 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED149 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED150 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED151 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED152 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED153 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED154 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED155 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED156 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED157 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED158 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED159 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED160 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED161 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED162 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED163 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED164 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED165 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED166 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED167 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED168 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED169 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED170 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED171 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED172 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED173 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED174 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED175 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED176 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED177 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED178 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED179 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED180 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED181 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED182 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED183 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED184 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED185 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED186 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED187 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED188 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED189 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED190 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED191 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED192 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED193 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED194 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED195 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED196 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED197 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED198 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED199 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED200 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED201 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED202 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED203 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED204 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED205 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED206 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED207 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED208 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED209 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED210 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED211 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED212 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED213 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED214 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED215 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED216 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED217 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED218 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED219 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED220 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED221 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED222 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED223 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED224 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED225 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED226 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED227 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED228 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED229 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED230 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED231 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED232 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED233 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED234 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED235 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED236 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED237 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED238 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED239 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED240 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED241 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED242 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED243 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED244 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED245 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED246 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED247 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED248 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED249 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED250 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED251 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED252 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED253 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED254 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED255 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED256 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED257 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED258 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED259 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED260 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED261 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED262 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED263 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED264 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED265 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED266 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED267 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED268 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED269 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED270 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED271 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED272 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED273 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED274 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED275 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED276 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED277 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED278 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED279 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED280 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED281 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED282 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED283 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED284 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED285 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED286 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED287 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED288 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED289 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED290 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED291 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED292 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED293 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED294 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED295 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED296 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED297 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED298 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED299 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED300 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED301 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED302 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED303 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED304 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED305 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED306 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED307 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED308 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED309 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED310 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED311 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED312 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED313 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED314 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED315 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED316 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED317 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED318 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED319 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED320 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED321 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED322 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED323 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED324 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED325 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED326 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED327 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED328 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED329 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED330 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED331 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED332 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED333 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED334 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED335 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED336 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED337 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED338 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED339 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED340 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED341 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED342 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED343 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED344 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED345 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED346 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED347 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED348 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED349 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED350 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED351 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED352 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED353 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED354 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED355 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED356 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED357 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED358 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED359 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED360 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED361 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED362 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED363 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED364 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED365 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED366 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED367 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED368 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED369 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED370 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED371 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED372 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED373 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED374 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED375 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED376 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED377 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED378 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED379 … #define mmDPHY_MACRO_CNTL_RESERVED0 … #define mmDPHY_MACRO_CNTL_RESERVED1 … #define mmDPHY_MACRO_CNTL_RESERVED2 … #define mmDPHY_MACRO_CNTL_RESERVED3 … #define mmDPHY_MACRO_CNTL_RESERVED4 … #define mmDPHY_MACRO_CNTL_RESERVED5 … #define mmDPHY_MACRO_CNTL_RESERVED6 … #define mmDPHY_MACRO_CNTL_RESERVED7 … #define mmDPHY_MACRO_CNTL_RESERVED8 … #define mmDPHY_MACRO_CNTL_RESERVED9 … #define mmDPHY_MACRO_CNTL_RESERVED10 … #define mmDPHY_MACRO_CNTL_RESERVED11 … #define mmDPHY_MACRO_CNTL_RESERVED12 … #define mmDPHY_MACRO_CNTL_RESERVED13 … #define mmDPHY_MACRO_CNTL_RESERVED14 … #define mmDPHY_MACRO_CNTL_RESERVED15 … #define mmDPHY_MACRO_CNTL_RESERVED16 … #define mmDPHY_MACRO_CNTL_RESERVED17 … #define mmDPHY_MACRO_CNTL_RESERVED18 … #define mmDPHY_MACRO_CNTL_RESERVED19 … #define mmDPHY_MACRO_CNTL_RESERVED20 … #define mmDPHY_MACRO_CNTL_RESERVED21 … #define mmDPHY_MACRO_CNTL_RESERVED22 … #define mmDPHY_MACRO_CNTL_RESERVED23 … #define mmDPHY_MACRO_CNTL_RESERVED24 … #define mmDPHY_MACRO_CNTL_RESERVED25 … #define mmDPHY_MACRO_CNTL_RESERVED26 … #define mmDPHY_MACRO_CNTL_RESERVED27 … #define mmDPHY_MACRO_CNTL_RESERVED28 … #define mmDPHY_MACRO_CNTL_RESERVED29 … #define mmDPHY_MACRO_CNTL_RESERVED30 … #define mmDPHY_MACRO_CNTL_RESERVED31 … #define mmDPHY_MACRO_CNTL_RESERVED32 … #define mmDPHY_MACRO_CNTL_RESERVED33 … #define mmDPHY_MACRO_CNTL_RESERVED34 … #define mmDPHY_MACRO_CNTL_RESERVED35 … #define mmDPHY_MACRO_CNTL_RESERVED36 … #define mmDPHY_MACRO_CNTL_RESERVED37 … #define mmDPHY_MACRO_CNTL_RESERVED38 … #define mmDPHY_MACRO_CNTL_RESERVED39 … #define mmDPHY_MACRO_CNTL_RESERVED40 … #define mmDPHY_MACRO_CNTL_RESERVED41 … #define mmDPHY_MACRO_CNTL_RESERVED42 … #define mmDPHY_MACRO_CNTL_RESERVED43 … #define mmDPHY_MACRO_CNTL_RESERVED44 … #define mmDPHY_MACRO_CNTL_RESERVED45 … #define mmDPHY_MACRO_CNTL_RESERVED46 … #define mmDPHY_MACRO_CNTL_RESERVED47 … #define mmDPHY_MACRO_CNTL_RESERVED48 … #define mmDPHY_MACRO_CNTL_RESERVED49 … #define mmDPHY_MACRO_CNTL_RESERVED50 … #define mmDPHY_MACRO_CNTL_RESERVED51 … #define mmDPHY_MACRO_CNTL_RESERVED52 … #define mmDPHY_MACRO_CNTL_RESERVED53 … #define mmDPHY_MACRO_CNTL_RESERVED54 … #define mmDPHY_MACRO_CNTL_RESERVED55 … #define mmDPHY_MACRO_CNTL_RESERVED56 … #define mmDPHY_MACRO_CNTL_RESERVED57 … #define mmDPHY_MACRO_CNTL_RESERVED58 … #define mmDPHY_MACRO_CNTL_RESERVED59 … #define mmDPHY_MACRO_CNTL_RESERVED60 … #define mmDPHY_MACRO_CNTL_RESERVED61 … #define mmDPHY_MACRO_CNTL_RESERVED62 … #define mmDPHY_MACRO_CNTL_RESERVED63 … #define mmGRPH_ENABLE … #define mmDCP0_GRPH_ENABLE … #define mmDCP1_GRPH_ENABLE … #define mmDCP2_GRPH_ENABLE … #define mmDCP3_GRPH_ENABLE … #define mmDCP4_GRPH_ENABLE … #define mmDCP5_GRPH_ENABLE … #define mmGRPH_CONTROL … #define mmDCP0_GRPH_CONTROL … #define mmDCP1_GRPH_CONTROL … #define mmDCP2_GRPH_CONTROL … #define mmDCP3_GRPH_CONTROL … #define mmDCP4_GRPH_CONTROL … #define mmDCP5_GRPH_CONTROL … #define mmGRPH_LUT_10BIT_BYPASS … #define mmDCP0_GRPH_LUT_10BIT_BYPASS … #define mmDCP1_GRPH_LUT_10BIT_BYPASS … #define mmDCP2_GRPH_LUT_10BIT_BYPASS … #define mmDCP3_GRPH_LUT_10BIT_BYPASS … #define mmDCP4_GRPH_LUT_10BIT_BYPASS … #define mmDCP5_GRPH_LUT_10BIT_BYPASS … #define mmGRPH_SWAP_CNTL … #define mmDCP0_GRPH_SWAP_CNTL … #define mmDCP1_GRPH_SWAP_CNTL … #define mmDCP2_GRPH_SWAP_CNTL … #define mmDCP3_GRPH_SWAP_CNTL … #define mmDCP4_GRPH_SWAP_CNTL … #define mmDCP5_GRPH_SWAP_CNTL … #define mmGRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmGRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmGRPH_PITCH … #define mmDCP0_GRPH_PITCH … #define mmDCP1_GRPH_PITCH … #define mmDCP2_GRPH_PITCH … #define mmDCP3_GRPH_PITCH … #define mmDCP4_GRPH_PITCH … #define mmDCP5_GRPH_PITCH … #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmGRPH_SURFACE_OFFSET_X … #define mmDCP0_GRPH_SURFACE_OFFSET_X … #define mmDCP1_GRPH_SURFACE_OFFSET_X … #define mmDCP2_GRPH_SURFACE_OFFSET_X … #define mmDCP3_GRPH_SURFACE_OFFSET_X … #define mmDCP4_GRPH_SURFACE_OFFSET_X … #define mmDCP5_GRPH_SURFACE_OFFSET_X … #define mmGRPH_SURFACE_OFFSET_Y … #define mmDCP0_GRPH_SURFACE_OFFSET_Y … #define mmDCP1_GRPH_SURFACE_OFFSET_Y … #define mmDCP2_GRPH_SURFACE_OFFSET_Y … #define mmDCP3_GRPH_SURFACE_OFFSET_Y … #define mmDCP4_GRPH_SURFACE_OFFSET_Y … #define mmDCP5_GRPH_SURFACE_OFFSET_Y … #define mmGRPH_X_START … #define mmDCP0_GRPH_X_START … #define mmDCP1_GRPH_X_START … #define mmDCP2_GRPH_X_START … #define mmDCP3_GRPH_X_START … #define mmDCP4_GRPH_X_START … #define mmDCP5_GRPH_X_START … #define mmGRPH_Y_START … #define mmDCP0_GRPH_Y_START … #define mmDCP1_GRPH_Y_START … #define mmDCP2_GRPH_Y_START … #define mmDCP3_GRPH_Y_START … #define mmDCP4_GRPH_Y_START … #define mmDCP5_GRPH_Y_START … #define mmGRPH_X_END … #define mmDCP0_GRPH_X_END … #define mmDCP1_GRPH_X_END … #define mmDCP2_GRPH_X_END … #define mmDCP3_GRPH_X_END … #define mmDCP4_GRPH_X_END … #define mmDCP5_GRPH_X_END … #define mmGRPH_Y_END … #define mmDCP0_GRPH_Y_END … #define mmDCP1_GRPH_Y_END … #define mmDCP2_GRPH_Y_END … #define mmDCP3_GRPH_Y_END … #define mmDCP4_GRPH_Y_END … #define mmDCP5_GRPH_Y_END … #define mmINPUT_GAMMA_CONTROL … #define mmDCP0_INPUT_GAMMA_CONTROL … #define mmDCP1_INPUT_GAMMA_CONTROL … #define mmDCP2_INPUT_GAMMA_CONTROL … #define mmDCP3_INPUT_GAMMA_CONTROL … #define mmDCP4_INPUT_GAMMA_CONTROL … #define mmDCP5_INPUT_GAMMA_CONTROL … #define mmGRPH_UPDATE … #define mmDCP0_GRPH_UPDATE … #define mmDCP1_GRPH_UPDATE … #define mmDCP2_GRPH_UPDATE … #define mmDCP3_GRPH_UPDATE … #define mmDCP4_GRPH_UPDATE … #define mmDCP5_GRPH_UPDATE … #define mmGRPH_FLIP_CONTROL … #define mmDCP0_GRPH_FLIP_CONTROL … #define mmDCP1_GRPH_FLIP_CONTROL … #define mmDCP2_GRPH_FLIP_CONTROL … #define mmDCP3_GRPH_FLIP_CONTROL … #define mmDCP4_GRPH_FLIP_CONTROL … #define mmDCP5_GRPH_FLIP_CONTROL … #define mmGRPH_SURFACE_ADDRESS_INUSE … #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE … #define mmGRPH_DFQ_CONTROL … #define mmDCP0_GRPH_DFQ_CONTROL … #define mmDCP1_GRPH_DFQ_CONTROL … #define mmDCP2_GRPH_DFQ_CONTROL … #define mmDCP3_GRPH_DFQ_CONTROL … #define mmDCP4_GRPH_DFQ_CONTROL … #define mmDCP5_GRPH_DFQ_CONTROL … #define mmGRPH_DFQ_STATUS … #define mmDCP0_GRPH_DFQ_STATUS … #define mmDCP1_GRPH_DFQ_STATUS … #define mmDCP2_GRPH_DFQ_STATUS … #define mmDCP3_GRPH_DFQ_STATUS … #define mmDCP4_GRPH_DFQ_STATUS … #define mmDCP5_GRPH_DFQ_STATUS … #define mmGRPH_INTERRUPT_STATUS … #define mmDCP0_GRPH_INTERRUPT_STATUS … #define mmDCP1_GRPH_INTERRUPT_STATUS … #define mmDCP2_GRPH_INTERRUPT_STATUS … #define mmDCP3_GRPH_INTERRUPT_STATUS … #define mmDCP4_GRPH_INTERRUPT_STATUS … #define mmDCP5_GRPH_INTERRUPT_STATUS … #define mmGRPH_INTERRUPT_CONTROL … #define mmDCP0_GRPH_INTERRUPT_CONTROL … #define mmDCP1_GRPH_INTERRUPT_CONTROL … #define mmDCP2_GRPH_INTERRUPT_CONTROL … #define mmDCP3_GRPH_INTERRUPT_CONTROL … #define mmDCP4_GRPH_INTERRUPT_CONTROL … #define mmDCP5_GRPH_INTERRUPT_CONTROL … #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmGRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmGRPH_COMPRESS_PITCH … #define mmDCP0_GRPH_COMPRESS_PITCH … #define mmDCP1_GRPH_COMPRESS_PITCH … #define mmDCP2_GRPH_COMPRESS_PITCH … #define mmDCP3_GRPH_COMPRESS_PITCH … #define mmDCP4_GRPH_COMPRESS_PITCH … #define mmDCP5_GRPH_COMPRESS_PITCH … #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmPRESCALE_GRPH_CONTROL … #define mmDCP0_PRESCALE_GRPH_CONTROL … #define mmDCP1_PRESCALE_GRPH_CONTROL … #define mmDCP2_PRESCALE_GRPH_CONTROL … #define mmDCP3_PRESCALE_GRPH_CONTROL … #define mmDCP4_PRESCALE_GRPH_CONTROL … #define mmDCP5_PRESCALE_GRPH_CONTROL … #define mmPRESCALE_VALUES_GRPH_R … #define mmDCP0_PRESCALE_VALUES_GRPH_R … #define mmDCP1_PRESCALE_VALUES_GRPH_R … #define mmDCP2_PRESCALE_VALUES_GRPH_R … #define mmDCP3_PRESCALE_VALUES_GRPH_R … #define mmDCP4_PRESCALE_VALUES_GRPH_R … #define mmDCP5_PRESCALE_VALUES_GRPH_R … #define mmPRESCALE_VALUES_GRPH_G … #define mmDCP0_PRESCALE_VALUES_GRPH_G … #define mmDCP1_PRESCALE_VALUES_GRPH_G … #define mmDCP2_PRESCALE_VALUES_GRPH_G … #define mmDCP3_PRESCALE_VALUES_GRPH_G … #define mmDCP4_PRESCALE_VALUES_GRPH_G … #define mmDCP5_PRESCALE_VALUES_GRPH_G … #define mmPRESCALE_VALUES_GRPH_B … #define mmDCP0_PRESCALE_VALUES_GRPH_B … #define mmDCP1_PRESCALE_VALUES_GRPH_B … #define mmDCP2_PRESCALE_VALUES_GRPH_B … #define mmDCP3_PRESCALE_VALUES_GRPH_B … #define mmDCP4_PRESCALE_VALUES_GRPH_B … #define mmDCP5_PRESCALE_VALUES_GRPH_B … #define mmINPUT_CSC_CONTROL … #define mmDCP0_INPUT_CSC_CONTROL … #define mmDCP1_INPUT_CSC_CONTROL … #define mmDCP2_INPUT_CSC_CONTROL … #define mmDCP3_INPUT_CSC_CONTROL … #define mmDCP4_INPUT_CSC_CONTROL … #define mmDCP5_INPUT_CSC_CONTROL … #define mmINPUT_CSC_C11_C12 … #define mmDCP0_INPUT_CSC_C11_C12 … #define mmDCP1_INPUT_CSC_C11_C12 … #define mmDCP2_INPUT_CSC_C11_C12 … #define mmDCP3_INPUT_CSC_C11_C12 … #define mmDCP4_INPUT_CSC_C11_C12 … #define mmDCP5_INPUT_CSC_C11_C12 … #define mmINPUT_CSC_C13_C14 … #define mmDCP0_INPUT_CSC_C13_C14 … #define mmDCP1_INPUT_CSC_C13_C14 … #define mmDCP2_INPUT_CSC_C13_C14 … #define mmDCP3_INPUT_CSC_C13_C14 … #define mmDCP4_INPUT_CSC_C13_C14 … #define mmDCP5_INPUT_CSC_C13_C14 … #define mmINPUT_CSC_C21_C22 … #define mmDCP0_INPUT_CSC_C21_C22 … #define mmDCP1_INPUT_CSC_C21_C22 … #define mmDCP2_INPUT_CSC_C21_C22 … #define mmDCP3_INPUT_CSC_C21_C22 … #define mmDCP4_INPUT_CSC_C21_C22 … #define mmDCP5_INPUT_CSC_C21_C22 … #define mmINPUT_CSC_C23_C24 … #define mmDCP0_INPUT_CSC_C23_C24 … #define mmDCP1_INPUT_CSC_C23_C24 … #define mmDCP2_INPUT_CSC_C23_C24 … #define mmDCP3_INPUT_CSC_C23_C24 … #define mmDCP4_INPUT_CSC_C23_C24 … #define mmDCP5_INPUT_CSC_C23_C24 … #define mmINPUT_CSC_C31_C32 … #define mmDCP0_INPUT_CSC_C31_C32 … #define mmDCP1_INPUT_CSC_C31_C32 … #define mmDCP2_INPUT_CSC_C31_C32 … #define mmDCP3_INPUT_CSC_C31_C32 … #define mmDCP4_INPUT_CSC_C31_C32 … #define mmDCP5_INPUT_CSC_C31_C32 … #define mmINPUT_CSC_C33_C34 … #define mmDCP0_INPUT_CSC_C33_C34 … #define mmDCP1_INPUT_CSC_C33_C34 … #define mmDCP2_INPUT_CSC_C33_C34 … #define mmDCP3_INPUT_CSC_C33_C34 … #define mmDCP4_INPUT_CSC_C33_C34 … #define mmDCP5_INPUT_CSC_C33_C34 … #define mmOUTPUT_CSC_CONTROL … #define mmDCP0_OUTPUT_CSC_CONTROL … #define mmDCP1_OUTPUT_CSC_CONTROL … #define mmDCP2_OUTPUT_CSC_CONTROL … #define mmDCP3_OUTPUT_CSC_CONTROL … #define mmDCP4_OUTPUT_CSC_CONTROL … #define mmDCP5_OUTPUT_CSC_CONTROL … #define mmOUTPUT_CSC_C11_C12 … #define mmDCP0_OUTPUT_CSC_C11_C12 … #define mmDCP1_OUTPUT_CSC_C11_C12 … #define mmDCP2_OUTPUT_CSC_C11_C12 … #define mmDCP3_OUTPUT_CSC_C11_C12 … #define mmDCP4_OUTPUT_CSC_C11_C12 … #define mmDCP5_OUTPUT_CSC_C11_C12 … #define mmOUTPUT_CSC_C13_C14 … #define mmDCP0_OUTPUT_CSC_C13_C14 … #define mmDCP1_OUTPUT_CSC_C13_C14 … #define mmDCP2_OUTPUT_CSC_C13_C14 … #define mmDCP3_OUTPUT_CSC_C13_C14 … #define mmDCP4_OUTPUT_CSC_C13_C14 … #define mmDCP5_OUTPUT_CSC_C13_C14 … #define mmOUTPUT_CSC_C21_C22 … #define mmDCP0_OUTPUT_CSC_C21_C22 … #define mmDCP1_OUTPUT_CSC_C21_C22 … #define mmDCP2_OUTPUT_CSC_C21_C22 … #define mmDCP3_OUTPUT_CSC_C21_C22 … #define mmDCP4_OUTPUT_CSC_C21_C22 … #define mmDCP5_OUTPUT_CSC_C21_C22 … #define mmOUTPUT_CSC_C23_C24 … #define mmDCP0_OUTPUT_CSC_C23_C24 … #define mmDCP1_OUTPUT_CSC_C23_C24 … #define mmDCP2_OUTPUT_CSC_C23_C24 … #define mmDCP3_OUTPUT_CSC_C23_C24 … #define mmDCP4_OUTPUT_CSC_C23_C24 … #define mmDCP5_OUTPUT_CSC_C23_C24 … #define mmOUTPUT_CSC_C31_C32 … #define mmDCP0_OUTPUT_CSC_C31_C32 … #define mmDCP1_OUTPUT_CSC_C31_C32 … #define mmDCP2_OUTPUT_CSC_C31_C32 … #define mmDCP3_OUTPUT_CSC_C31_C32 … #define mmDCP4_OUTPUT_CSC_C31_C32 … #define mmDCP5_OUTPUT_CSC_C31_C32 … #define mmOUTPUT_CSC_C33_C34 … #define mmDCP0_OUTPUT_CSC_C33_C34 … #define mmDCP1_OUTPUT_CSC_C33_C34 … #define mmDCP2_OUTPUT_CSC_C33_C34 … #define mmDCP3_OUTPUT_CSC_C33_C34 … #define mmDCP4_OUTPUT_CSC_C33_C34 … #define mmDCP5_OUTPUT_CSC_C33_C34 … #define mmCOMM_MATRIXA_TRANS_C11_C12 … #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 … #define mmCOMM_MATRIXA_TRANS_C13_C14 … #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 … #define mmCOMM_MATRIXA_TRANS_C21_C22 … #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 … #define mmCOMM_MATRIXA_TRANS_C23_C24 … #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 … #define mmCOMM_MATRIXA_TRANS_C31_C32 … #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 … #define mmCOMM_MATRIXA_TRANS_C33_C34 … #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 … #define mmCOMM_MATRIXB_TRANS_C11_C12 … #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 … #define mmCOMM_MATRIXB_TRANS_C13_C14 … #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 … #define mmCOMM_MATRIXB_TRANS_C21_C22 … #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 … #define mmCOMM_MATRIXB_TRANS_C23_C24 … #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 … #define mmCOMM_MATRIXB_TRANS_C31_C32 … #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 … #define mmCOMM_MATRIXB_TRANS_C33_C34 … #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 … #define mmDENORM_CONTROL … #define mmDCP0_DENORM_CONTROL … #define mmDCP1_DENORM_CONTROL … #define mmDCP2_DENORM_CONTROL … #define mmDCP3_DENORM_CONTROL … #define mmDCP4_DENORM_CONTROL … #define mmDCP5_DENORM_CONTROL … #define mmOUT_ROUND_CONTROL … #define mmDCP0_OUT_ROUND_CONTROL … #define mmDCP1_OUT_ROUND_CONTROL … #define mmDCP2_OUT_ROUND_CONTROL … #define mmDCP3_OUT_ROUND_CONTROL … #define mmDCP4_OUT_ROUND_CONTROL … #define mmDCP5_OUT_ROUND_CONTROL … #define mmOUT_CLAMP_CONTROL_R_CR … #define mmDCP0_OUT_CLAMP_CONTROL_R_CR … #define mmDCP1_OUT_CLAMP_CONTROL_R_CR … #define mmDCP2_OUT_CLAMP_CONTROL_R_CR … #define mmDCP3_OUT_CLAMP_CONTROL_R_CR … #define mmDCP4_OUT_CLAMP_CONTROL_R_CR … #define mmDCP5_OUT_CLAMP_CONTROL_R_CR … #define mmOUT_CLAMP_CONTROL_G_Y … #define mmDCP0_OUT_CLAMP_CONTROL_G_Y … #define mmDCP1_OUT_CLAMP_CONTROL_G_Y … #define mmDCP2_OUT_CLAMP_CONTROL_G_Y … #define mmDCP3_OUT_CLAMP_CONTROL_G_Y … #define mmDCP4_OUT_CLAMP_CONTROL_G_Y … #define mmDCP5_OUT_CLAMP_CONTROL_G_Y … #define mmOUT_CLAMP_CONTROL_B_CB … #define mmDCP0_OUT_CLAMP_CONTROL_B_CB … #define mmDCP1_OUT_CLAMP_CONTROL_B_CB … #define mmDCP2_OUT_CLAMP_CONTROL_B_CB … #define mmDCP3_OUT_CLAMP_CONTROL_B_CB … #define mmDCP4_OUT_CLAMP_CONTROL_B_CB … #define mmDCP5_OUT_CLAMP_CONTROL_B_CB … #define mmKEY_CONTROL … #define mmDCP0_KEY_CONTROL … #define mmDCP1_KEY_CONTROL … #define mmDCP2_KEY_CONTROL … #define mmDCP3_KEY_CONTROL … #define mmDCP4_KEY_CONTROL … #define mmDCP5_KEY_CONTROL … #define mmKEY_RANGE_ALPHA … #define mmDCP0_KEY_RANGE_ALPHA … #define mmDCP1_KEY_RANGE_ALPHA … #define mmDCP2_KEY_RANGE_ALPHA … #define mmDCP3_KEY_RANGE_ALPHA … #define mmDCP4_KEY_RANGE_ALPHA … #define mmDCP5_KEY_RANGE_ALPHA … #define mmKEY_RANGE_RED … #define mmDCP0_KEY_RANGE_RED … #define mmDCP1_KEY_RANGE_RED … #define mmDCP2_KEY_RANGE_RED … #define mmDCP3_KEY_RANGE_RED … #define mmDCP4_KEY_RANGE_RED … #define mmDCP5_KEY_RANGE_RED … #define mmKEY_RANGE_GREEN … #define mmDCP0_KEY_RANGE_GREEN … #define mmDCP1_KEY_RANGE_GREEN … #define mmDCP2_KEY_RANGE_GREEN … #define mmDCP3_KEY_RANGE_GREEN … #define mmDCP4_KEY_RANGE_GREEN … #define mmDCP5_KEY_RANGE_GREEN … #define mmKEY_RANGE_BLUE … #define mmDCP0_KEY_RANGE_BLUE … #define mmDCP1_KEY_RANGE_BLUE … #define mmDCP2_KEY_RANGE_BLUE … #define mmDCP3_KEY_RANGE_BLUE … #define mmDCP4_KEY_RANGE_BLUE … #define mmDCP5_KEY_RANGE_BLUE … #define mmDEGAMMA_CONTROL … #define mmDCP0_DEGAMMA_CONTROL … #define mmDCP1_DEGAMMA_CONTROL … #define mmDCP2_DEGAMMA_CONTROL … #define mmDCP3_DEGAMMA_CONTROL … #define mmDCP4_DEGAMMA_CONTROL … #define mmDCP5_DEGAMMA_CONTROL … #define mmGAMUT_REMAP_CONTROL … #define mmDCP0_GAMUT_REMAP_CONTROL … #define mmDCP1_GAMUT_REMAP_CONTROL … #define mmDCP2_GAMUT_REMAP_CONTROL … #define mmDCP3_GAMUT_REMAP_CONTROL … #define mmDCP4_GAMUT_REMAP_CONTROL … #define mmDCP5_GAMUT_REMAP_CONTROL … #define mmGAMUT_REMAP_C11_C12 … #define mmDCP0_GAMUT_REMAP_C11_C12 … #define mmDCP1_GAMUT_REMAP_C11_C12 … #define mmDCP2_GAMUT_REMAP_C11_C12 … #define mmDCP3_GAMUT_REMAP_C11_C12 … #define mmDCP4_GAMUT_REMAP_C11_C12 … #define mmDCP5_GAMUT_REMAP_C11_C12 … #define mmGAMUT_REMAP_C13_C14 … #define mmDCP0_GAMUT_REMAP_C13_C14 … #define mmDCP1_GAMUT_REMAP_C13_C14 … #define mmDCP2_GAMUT_REMAP_C13_C14 … #define mmDCP3_GAMUT_REMAP_C13_C14 … #define mmDCP4_GAMUT_REMAP_C13_C14 … #define mmDCP5_GAMUT_REMAP_C13_C14 … #define mmGAMUT_REMAP_C21_C22 … #define mmDCP0_GAMUT_REMAP_C21_C22 … #define mmDCP1_GAMUT_REMAP_C21_C22 … #define mmDCP2_GAMUT_REMAP_C21_C22 … #define mmDCP3_GAMUT_REMAP_C21_C22 … #define mmDCP4_GAMUT_REMAP_C21_C22 … #define mmDCP5_GAMUT_REMAP_C21_C22 … #define mmGAMUT_REMAP_C23_C24 … #define mmDCP0_GAMUT_REMAP_C23_C24 … #define mmDCP1_GAMUT_REMAP_C23_C24 … #define mmDCP2_GAMUT_REMAP_C23_C24 … #define mmDCP3_GAMUT_REMAP_C23_C24 … #define mmDCP4_GAMUT_REMAP_C23_C24 … #define mmDCP5_GAMUT_REMAP_C23_C24 … #define mmGAMUT_REMAP_C31_C32 … #define mmDCP0_GAMUT_REMAP_C31_C32 … #define mmDCP1_GAMUT_REMAP_C31_C32 … #define mmDCP2_GAMUT_REMAP_C31_C32 … #define mmDCP3_GAMUT_REMAP_C31_C32 … #define mmDCP4_GAMUT_REMAP_C31_C32 … #define mmDCP5_GAMUT_REMAP_C31_C32 … #define mmGAMUT_REMAP_C33_C34 … #define mmDCP0_GAMUT_REMAP_C33_C34 … #define mmDCP1_GAMUT_REMAP_C33_C34 … #define mmDCP2_GAMUT_REMAP_C33_C34 … #define mmDCP3_GAMUT_REMAP_C33_C34 … #define mmDCP4_GAMUT_REMAP_C33_C34 … #define mmDCP5_GAMUT_REMAP_C33_C34 … #define mmDCP_SPATIAL_DITHER_CNTL … #define mmDCP0_DCP_SPATIAL_DITHER_CNTL … #define mmDCP1_DCP_SPATIAL_DITHER_CNTL … #define mmDCP2_DCP_SPATIAL_DITHER_CNTL … #define mmDCP3_DCP_SPATIAL_DITHER_CNTL … #define mmDCP4_DCP_SPATIAL_DITHER_CNTL … #define mmDCP5_DCP_SPATIAL_DITHER_CNTL … #define mmDCP_FP_CONVERTED_FIELD … #define mmDCP0_DCP_FP_CONVERTED_FIELD … #define mmDCP1_DCP_FP_CONVERTED_FIELD … #define mmDCP2_DCP_FP_CONVERTED_FIELD … #define mmDCP3_DCP_FP_CONVERTED_FIELD … #define mmDCP4_DCP_FP_CONVERTED_FIELD … #define mmDCP5_DCP_FP_CONVERTED_FIELD … #define mmCUR_CONTROL … #define mmDCP0_CUR_CONTROL … #define mmDCP1_CUR_CONTROL … #define mmDCP2_CUR_CONTROL … #define mmDCP3_CUR_CONTROL … #define mmDCP4_CUR_CONTROL … #define mmDCP5_CUR_CONTROL … #define mmCUR_SURFACE_ADDRESS … #define mmDCP0_CUR_SURFACE_ADDRESS … #define mmDCP1_CUR_SURFACE_ADDRESS … #define mmDCP2_CUR_SURFACE_ADDRESS … #define mmDCP3_CUR_SURFACE_ADDRESS … #define mmDCP4_CUR_SURFACE_ADDRESS … #define mmDCP5_CUR_SURFACE_ADDRESS … #define mmCUR_SIZE … #define mmDCP0_CUR_SIZE … #define mmDCP1_CUR_SIZE … #define mmDCP2_CUR_SIZE … #define mmDCP3_CUR_SIZE … #define mmDCP4_CUR_SIZE … #define mmDCP5_CUR_SIZE … #define mmCUR_SURFACE_ADDRESS_HIGH … #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH … #define mmCUR_POSITION … #define mmDCP0_CUR_POSITION … #define mmDCP1_CUR_POSITION … #define mmDCP2_CUR_POSITION … #define mmDCP3_CUR_POSITION … #define mmDCP4_CUR_POSITION … #define mmDCP5_CUR_POSITION … #define mmCUR_HOT_SPOT … #define mmDCP0_CUR_HOT_SPOT … #define mmDCP1_CUR_HOT_SPOT … #define mmDCP2_CUR_HOT_SPOT … #define mmDCP3_CUR_HOT_SPOT … #define mmDCP4_CUR_HOT_SPOT … #define mmDCP5_CUR_HOT_SPOT … #define mmCUR_COLOR1 … #define mmDCP0_CUR_COLOR1 … #define mmDCP1_CUR_COLOR1 … #define mmDCP2_CUR_COLOR1 … #define mmDCP3_CUR_COLOR1 … #define mmDCP4_CUR_COLOR1 … #define mmDCP5_CUR_COLOR1 … #define mmCUR_COLOR2 … #define mmDCP0_CUR_COLOR2 … #define mmDCP1_CUR_COLOR2 … #define mmDCP2_CUR_COLOR2 … #define mmDCP3_CUR_COLOR2 … #define mmDCP4_CUR_COLOR2 … #define mmDCP5_CUR_COLOR2 … #define mmCUR_UPDATE … #define mmDCP0_CUR_UPDATE … #define mmDCP1_CUR_UPDATE … #define mmDCP2_CUR_UPDATE … #define mmDCP3_CUR_UPDATE … #define mmDCP4_CUR_UPDATE … #define mmDCP5_CUR_UPDATE … #define mmCUR_REQUEST_FILTER_CNTL … #define mmDCP0_CUR_REQUEST_FILTER_CNTL … #define mmDCP1_CUR_REQUEST_FILTER_CNTL … #define mmDCP2_CUR_REQUEST_FILTER_CNTL … #define mmDCP3_CUR_REQUEST_FILTER_CNTL … #define mmDCP4_CUR_REQUEST_FILTER_CNTL … #define mmDCP5_CUR_REQUEST_FILTER_CNTL … #define mmCUR_STEREO_CONTROL … #define mmDCP0_CUR_STEREO_CONTROL … #define mmDCP1_CUR_STEREO_CONTROL … #define mmDCP2_CUR_STEREO_CONTROL … #define mmDCP3_CUR_STEREO_CONTROL … #define mmDCP4_CUR_STEREO_CONTROL … #define mmDCP5_CUR_STEREO_CONTROL … #define mmDC_LUT_RW_MODE … #define mmDCP0_DC_LUT_RW_MODE … #define mmDCP1_DC_LUT_RW_MODE … #define mmDCP2_DC_LUT_RW_MODE … #define mmDCP3_DC_LUT_RW_MODE … #define mmDCP4_DC_LUT_RW_MODE … #define mmDCP5_DC_LUT_RW_MODE … #define mmDC_LUT_RW_INDEX … #define mmDCP0_DC_LUT_RW_INDEX … #define mmDCP1_DC_LUT_RW_INDEX … #define mmDCP2_DC_LUT_RW_INDEX … #define mmDCP3_DC_LUT_RW_INDEX … #define mmDCP4_DC_LUT_RW_INDEX … #define mmDCP5_DC_LUT_RW_INDEX … #define mmDC_LUT_SEQ_COLOR … #define mmDCP0_DC_LUT_SEQ_COLOR … #define mmDCP1_DC_LUT_SEQ_COLOR … #define mmDCP2_DC_LUT_SEQ_COLOR … #define mmDCP3_DC_LUT_SEQ_COLOR … #define mmDCP4_DC_LUT_SEQ_COLOR … #define mmDCP5_DC_LUT_SEQ_COLOR … #define mmDC_LUT_PWL_DATA … #define mmDCP0_DC_LUT_PWL_DATA … #define mmDCP1_DC_LUT_PWL_DATA … #define mmDCP2_DC_LUT_PWL_DATA … #define mmDCP3_DC_LUT_PWL_DATA … #define mmDCP4_DC_LUT_PWL_DATA … #define mmDCP5_DC_LUT_PWL_DATA … #define mmDC_LUT_30_COLOR … #define mmDCP0_DC_LUT_30_COLOR … #define mmDCP1_DC_LUT_30_COLOR … #define mmDCP2_DC_LUT_30_COLOR … #define mmDCP3_DC_LUT_30_COLOR … #define mmDCP4_DC_LUT_30_COLOR … #define mmDCP5_DC_LUT_30_COLOR … #define mmDC_LUT_VGA_ACCESS_ENABLE … #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE … #define mmDC_LUT_WRITE_EN_MASK … #define mmDCP0_DC_LUT_WRITE_EN_MASK … #define mmDCP1_DC_LUT_WRITE_EN_MASK … #define mmDCP2_DC_LUT_WRITE_EN_MASK … #define mmDCP3_DC_LUT_WRITE_EN_MASK … #define mmDCP4_DC_LUT_WRITE_EN_MASK … #define mmDCP5_DC_LUT_WRITE_EN_MASK … #define mmDC_LUT_AUTOFILL … #define mmDCP0_DC_LUT_AUTOFILL … #define mmDCP1_DC_LUT_AUTOFILL … #define mmDCP2_DC_LUT_AUTOFILL … #define mmDCP3_DC_LUT_AUTOFILL … #define mmDCP4_DC_LUT_AUTOFILL … #define mmDCP5_DC_LUT_AUTOFILL … #define mmDC_LUT_CONTROL … #define mmDCP0_DC_LUT_CONTROL … #define mmDCP1_DC_LUT_CONTROL … #define mmDCP2_DC_LUT_CONTROL … #define mmDCP3_DC_LUT_CONTROL … #define mmDCP4_DC_LUT_CONTROL … #define mmDCP5_DC_LUT_CONTROL … #define mmDC_LUT_BLACK_OFFSET_BLUE … #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE … #define mmDC_LUT_BLACK_OFFSET_GREEN … #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN … #define mmDC_LUT_BLACK_OFFSET_RED … #define mmDCP0_DC_LUT_BLACK_OFFSET_RED … #define mmDCP1_DC_LUT_BLACK_OFFSET_RED … #define mmDCP2_DC_LUT_BLACK_OFFSET_RED … #define mmDCP3_DC_LUT_BLACK_OFFSET_RED … #define mmDCP4_DC_LUT_BLACK_OFFSET_RED … #define mmDCP5_DC_LUT_BLACK_OFFSET_RED … #define mmDC_LUT_WHITE_OFFSET_BLUE … #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE … #define mmDC_LUT_WHITE_OFFSET_GREEN … #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN … #define mmDC_LUT_WHITE_OFFSET_RED … #define mmDCP0_DC_LUT_WHITE_OFFSET_RED … #define mmDCP1_DC_LUT_WHITE_OFFSET_RED … #define mmDCP2_DC_LUT_WHITE_OFFSET_RED … #define mmDCP3_DC_LUT_WHITE_OFFSET_RED … #define mmDCP4_DC_LUT_WHITE_OFFSET_RED … #define mmDCP5_DC_LUT_WHITE_OFFSET_RED … #define mmDCP_CRC_CONTROL … #define mmDCP0_DCP_CRC_CONTROL … #define mmDCP1_DCP_CRC_CONTROL … #define mmDCP2_DCP_CRC_CONTROL … #define mmDCP3_DCP_CRC_CONTROL … #define mmDCP4_DCP_CRC_CONTROL … #define mmDCP5_DCP_CRC_CONTROL … #define mmDCP_CRC_MASK … #define mmDCP0_DCP_CRC_MASK … #define mmDCP1_DCP_CRC_MASK … #define mmDCP2_DCP_CRC_MASK … #define mmDCP3_DCP_CRC_MASK … #define mmDCP4_DCP_CRC_MASK … #define mmDCP5_DCP_CRC_MASK … #define mmDCP_CRC_CURRENT … #define mmDCP0_DCP_CRC_CURRENT … #define mmDCP1_DCP_CRC_CURRENT … #define mmDCP2_DCP_CRC_CURRENT … #define mmDCP3_DCP_CRC_CURRENT … #define mmDCP4_DCP_CRC_CURRENT … #define mmDCP5_DCP_CRC_CURRENT … #define mmDVMM_PTE_CONTROL … #define mmDCP0_DVMM_PTE_CONTROL … #define mmDCP1_DVMM_PTE_CONTROL … #define mmDCP2_DVMM_PTE_CONTROL … #define mmDCP3_DVMM_PTE_CONTROL … #define mmDCP4_DVMM_PTE_CONTROL … #define mmDCP5_DVMM_PTE_CONTROL … #define mmDCP_CRC_LAST … #define mmDCP0_DCP_CRC_LAST … #define mmDCP1_DCP_CRC_LAST … #define mmDCP2_DCP_CRC_LAST … #define mmDCP3_DCP_CRC_LAST … #define mmDCP4_DCP_CRC_LAST … #define mmDCP5_DCP_CRC_LAST … #define mmDVMM_PTE_ARB_CONTROL … #define mmDCP0_DVMM_PTE_ARB_CONTROL … #define mmDCP1_DVMM_PTE_ARB_CONTROL … #define mmDCP2_DVMM_PTE_ARB_CONTROL … #define mmDCP3_DVMM_PTE_ARB_CONTROL … #define mmDCP4_DVMM_PTE_ARB_CONTROL … #define mmDCP5_DVMM_PTE_ARB_CONTROL … #define mmDCP_DEBUG … #define mmDCP0_DCP_DEBUG … #define mmDCP1_DCP_DEBUG … #define mmDCP2_DCP_DEBUG … #define mmDCP3_DCP_DEBUG … #define mmDCP4_DCP_DEBUG … #define mmDCP5_DCP_DEBUG … #define mmGRPH_FLIP_RATE_CNTL … #define mmDCP0_GRPH_FLIP_RATE_CNTL … #define mmDCP1_GRPH_FLIP_RATE_CNTL … #define mmDCP2_GRPH_FLIP_RATE_CNTL … #define mmDCP3_GRPH_FLIP_RATE_CNTL … #define mmDCP4_GRPH_FLIP_RATE_CNTL … #define mmDCP5_GRPH_FLIP_RATE_CNTL … #define mmDCP_GSL_CONTROL … #define mmDCP0_DCP_GSL_CONTROL … #define mmDCP1_DCP_GSL_CONTROL … #define mmDCP2_DCP_GSL_CONTROL … #define mmDCP3_DCP_GSL_CONTROL … #define mmDCP4_DCP_GSL_CONTROL … #define mmDCP5_DCP_GSL_CONTROL … #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP_DEBUG_SG … #define mmDCP0_DCP_DEBUG_SG … #define mmDCP1_DCP_DEBUG_SG … #define mmDCP2_DCP_DEBUG_SG … #define mmDCP3_DCP_DEBUG_SG … #define mmDCP4_DCP_DEBUG_SG … #define mmDCP5_DCP_DEBUG_SG … #define mmDCP_DEBUG_SG2 … #define mmDCP0_DCP_DEBUG_SG2 … #define mmDCP1_DCP_DEBUG_SG2 … #define mmDCP2_DCP_DEBUG_SG2 … #define mmDCP3_DCP_DEBUG_SG2 … #define mmDCP4_DCP_DEBUG_SG2 … #define mmDCP5_DCP_DEBUG_SG2 … #define mmDCP_DVMM_DEBUG … #define mmDCP0_DCP_DVMM_DEBUG … #define mmDCP1_DCP_DVMM_DEBUG … #define mmDCP2_DCP_DVMM_DEBUG … #define mmDCP3_DCP_DVMM_DEBUG … #define mmDCP4_DCP_DVMM_DEBUG … #define mmDCP5_DCP_DVMM_DEBUG … #define mmDCP_TEST_DEBUG_INDEX … #define mmDCP0_DCP_TEST_DEBUG_INDEX … #define mmDCP1_DCP_TEST_DEBUG_INDEX … #define mmDCP2_DCP_TEST_DEBUG_INDEX … #define mmDCP3_DCP_TEST_DEBUG_INDEX … #define mmDCP4_DCP_TEST_DEBUG_INDEX … #define mmDCP5_DCP_TEST_DEBUG_INDEX … #define mmDCP_TEST_DEBUG_DATA … #define mmDCP0_DCP_TEST_DEBUG_DATA … #define mmDCP1_DCP_TEST_DEBUG_DATA … #define mmDCP2_DCP_TEST_DEBUG_DATA … #define mmDCP3_DCP_TEST_DEBUG_DATA … #define mmDCP4_DCP_TEST_DEBUG_DATA … #define mmDCP5_DCP_TEST_DEBUG_DATA … #define mmGRPH_STEREOSYNC_FLIP … #define mmDCP0_GRPH_STEREOSYNC_FLIP … #define mmDCP1_GRPH_STEREOSYNC_FLIP … #define mmDCP2_GRPH_STEREOSYNC_FLIP … #define mmDCP3_GRPH_STEREOSYNC_FLIP … #define mmDCP4_GRPH_STEREOSYNC_FLIP … #define mmDCP5_GRPH_STEREOSYNC_FLIP … #define mmDCP_DEBUG2 … #define mmDCP0_DCP_DEBUG2 … #define mmDCP1_DCP_DEBUG2 … #define mmDCP2_DCP_DEBUG2 … #define mmDCP3_DCP_DEBUG2 … #define mmDCP4_DCP_DEBUG2 … #define mmDCP5_DCP_DEBUG2 … #define mmHW_ROTATION … #define mmDCP0_HW_ROTATION … #define mmDCP1_HW_ROTATION … #define mmDCP2_HW_ROTATION … #define mmDCP3_HW_ROTATION … #define mmDCP4_HW_ROTATION … #define mmDCP5_HW_ROTATION … #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmREGAMMA_CONTROL … #define mmDCP0_REGAMMA_CONTROL … #define mmDCP1_REGAMMA_CONTROL … #define mmDCP2_REGAMMA_CONTROL … #define mmDCP3_REGAMMA_CONTROL … #define mmDCP4_REGAMMA_CONTROL … #define mmDCP5_REGAMMA_CONTROL … #define mmREGAMMA_LUT_INDEX … #define mmDCP0_REGAMMA_LUT_INDEX … #define mmDCP1_REGAMMA_LUT_INDEX … #define mmDCP2_REGAMMA_LUT_INDEX … #define mmDCP3_REGAMMA_LUT_INDEX … #define mmDCP4_REGAMMA_LUT_INDEX … #define mmDCP5_REGAMMA_LUT_INDEX … #define mmREGAMMA_LUT_DATA … #define mmDCP0_REGAMMA_LUT_DATA … #define mmDCP1_REGAMMA_LUT_DATA … #define mmDCP2_REGAMMA_LUT_DATA … #define mmDCP3_REGAMMA_LUT_DATA … #define mmDCP4_REGAMMA_LUT_DATA … #define mmDCP5_REGAMMA_LUT_DATA … #define mmREGAMMA_LUT_WRITE_EN_MASK … #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK … #define mmREGAMMA_CNTLA_START_CNTL … #define mmDCP0_REGAMMA_CNTLA_START_CNTL … #define mmDCP1_REGAMMA_CNTLA_START_CNTL … #define mmDCP2_REGAMMA_CNTLA_START_CNTL … #define mmDCP3_REGAMMA_CNTLA_START_CNTL … #define mmDCP4_REGAMMA_CNTLA_START_CNTL … #define mmDCP5_REGAMMA_CNTLA_START_CNTL … #define mmREGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL … #define mmREGAMMA_CNTLA_END_CNTL1 … #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 … #define mmREGAMMA_CNTLA_END_CNTL2 … #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 … #define mmREGAMMA_CNTLA_REGION_0_1 … #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 … #define mmREGAMMA_CNTLA_REGION_2_3 … #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 … #define mmREGAMMA_CNTLA_REGION_4_5 … #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 … #define mmREGAMMA_CNTLA_REGION_6_7 … #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 … #define mmREGAMMA_CNTLA_REGION_8_9 … #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 … #define mmREGAMMA_CNTLA_REGION_10_11 … #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 … #define mmREGAMMA_CNTLA_REGION_12_13 … #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 … #define mmREGAMMA_CNTLA_REGION_14_15 … #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 … #define mmREGAMMA_CNTLB_START_CNTL … #define mmDCP0_REGAMMA_CNTLB_START_CNTL … #define mmDCP1_REGAMMA_CNTLB_START_CNTL … #define mmDCP2_REGAMMA_CNTLB_START_CNTL … #define mmDCP3_REGAMMA_CNTLB_START_CNTL … #define mmDCP4_REGAMMA_CNTLB_START_CNTL … #define mmDCP5_REGAMMA_CNTLB_START_CNTL … #define mmREGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL … #define mmREGAMMA_CNTLB_END_CNTL1 … #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 … #define mmREGAMMA_CNTLB_END_CNTL2 … #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 … #define mmREGAMMA_CNTLB_REGION_0_1 … #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 … #define mmREGAMMA_CNTLB_REGION_2_3 … #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 … #define mmREGAMMA_CNTLB_REGION_4_5 … #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 … #define mmREGAMMA_CNTLB_REGION_6_7 … #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 … #define mmREGAMMA_CNTLB_REGION_8_9 … #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 … #define mmREGAMMA_CNTLB_REGION_10_11 … #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 … #define mmREGAMMA_CNTLB_REGION_12_13 … #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 … #define mmREGAMMA_CNTLB_REGION_14_15 … #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 … #define mmALPHA_CONTROL … #define mmDCP0_ALPHA_CONTROL … #define mmDCP1_ALPHA_CONTROL … #define mmDCP2_ALPHA_CONTROL … #define mmDCP3_ALPHA_CONTROL … #define mmDCP4_ALPHA_CONTROL … #define mmDCP5_ALPHA_CONTROL … #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmGRPH_SURFACE_COUNTER_CONTROL … #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL … #define mmGRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDIG_FE_CNTL … #define mmDIG0_DIG_FE_CNTL … #define mmDIG1_DIG_FE_CNTL … #define mmDIG2_DIG_FE_CNTL … #define mmDIG3_DIG_FE_CNTL … #define mmDIG4_DIG_FE_CNTL … #define mmDIG5_DIG_FE_CNTL … #define mmDIG6_DIG_FE_CNTL … #define mmDIG7_DIG_FE_CNTL … #define mmDIG8_DIG_FE_CNTL … #define mmDIG_OUTPUT_CRC_CNTL … #define mmDIG0_DIG_OUTPUT_CRC_CNTL … #define mmDIG1_DIG_OUTPUT_CRC_CNTL … #define mmDIG2_DIG_OUTPUT_CRC_CNTL … #define mmDIG3_DIG_OUTPUT_CRC_CNTL … #define mmDIG4_DIG_OUTPUT_CRC_CNTL … #define mmDIG5_DIG_OUTPUT_CRC_CNTL … #define mmDIG6_DIG_OUTPUT_CRC_CNTL … #define mmDIG7_DIG_OUTPUT_CRC_CNTL … #define mmDIG8_DIG_OUTPUT_CRC_CNTL … #define mmDIG_OUTPUT_CRC_RESULT … #define mmDIG0_DIG_OUTPUT_CRC_RESULT … #define mmDIG1_DIG_OUTPUT_CRC_RESULT … #define mmDIG2_DIG_OUTPUT_CRC_RESULT … #define mmDIG3_DIG_OUTPUT_CRC_RESULT … #define mmDIG4_DIG_OUTPUT_CRC_RESULT … #define mmDIG5_DIG_OUTPUT_CRC_RESULT … #define mmDIG6_DIG_OUTPUT_CRC_RESULT … #define mmDIG7_DIG_OUTPUT_CRC_RESULT … #define mmDIG8_DIG_OUTPUT_CRC_RESULT … #define mmDIG_CLOCK_PATTERN … #define mmDIG0_DIG_CLOCK_PATTERN … #define mmDIG1_DIG_CLOCK_PATTERN … #define mmDIG2_DIG_CLOCK_PATTERN … #define mmDIG3_DIG_CLOCK_PATTERN … #define mmDIG4_DIG_CLOCK_PATTERN … #define mmDIG5_DIG_CLOCK_PATTERN … #define mmDIG6_DIG_CLOCK_PATTERN … #define mmDIG7_DIG_CLOCK_PATTERN … #define mmDIG8_DIG_CLOCK_PATTERN … #define mmDIG_TEST_PATTERN … #define mmDIG0_DIG_TEST_PATTERN … #define mmDIG1_DIG_TEST_PATTERN … #define mmDIG2_DIG_TEST_PATTERN … #define mmDIG3_DIG_TEST_PATTERN … #define mmDIG4_DIG_TEST_PATTERN … #define mmDIG5_DIG_TEST_PATTERN … #define mmDIG6_DIG_TEST_PATTERN … #define mmDIG7_DIG_TEST_PATTERN … #define mmDIG8_DIG_TEST_PATTERN … #define mmDIG_RANDOM_PATTERN_SEED … #define mmDIG0_DIG_RANDOM_PATTERN_SEED … #define mmDIG1_DIG_RANDOM_PATTERN_SEED … #define mmDIG2_DIG_RANDOM_PATTERN_SEED … #define mmDIG3_DIG_RANDOM_PATTERN_SEED … #define mmDIG4_DIG_RANDOM_PATTERN_SEED … #define mmDIG5_DIG_RANDOM_PATTERN_SEED … #define mmDIG6_DIG_RANDOM_PATTERN_SEED … #define mmDIG7_DIG_RANDOM_PATTERN_SEED … #define mmDIG8_DIG_RANDOM_PATTERN_SEED … #define mmDIG_FIFO_STATUS … #define mmDIG0_DIG_FIFO_STATUS … #define mmDIG1_DIG_FIFO_STATUS … #define mmDIG2_DIG_FIFO_STATUS … #define mmDIG3_DIG_FIFO_STATUS … #define mmDIG4_DIG_FIFO_STATUS … #define mmDIG5_DIG_FIFO_STATUS … #define mmDIG6_DIG_FIFO_STATUS … #define mmDIG7_DIG_FIFO_STATUS … #define mmDIG8_DIG_FIFO_STATUS … #define mmDIG_DISPCLK_SWITCH_CNTL … #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG7_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG8_DIG_DISPCLK_SWITCH_CNTL … #define mmDIG_DISPCLK_SWITCH_STATUS … #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG7_DIG_DISPCLK_SWITCH_STATUS … #define mmDIG8_DIG_DISPCLK_SWITCH_STATUS … #define mmHDMI_CONTROL … #define mmDIG0_HDMI_CONTROL … #define mmDIG1_HDMI_CONTROL … #define mmDIG2_HDMI_CONTROL … #define mmDIG3_HDMI_CONTROL … #define mmDIG4_HDMI_CONTROL … #define mmDIG5_HDMI_CONTROL … #define mmDIG6_HDMI_CONTROL … #define mmDIG7_HDMI_CONTROL … #define mmDIG8_HDMI_CONTROL … #define mmHDMI_STATUS … #define mmDIG0_HDMI_STATUS … #define mmDIG1_HDMI_STATUS … #define mmDIG2_HDMI_STATUS … #define mmDIG3_HDMI_STATUS … #define mmDIG4_HDMI_STATUS … #define mmDIG5_HDMI_STATUS … #define mmDIG6_HDMI_STATUS … #define mmDIG7_HDMI_STATUS … #define mmDIG8_HDMI_STATUS … #define mmHDMI_AUDIO_PACKET_CONTROL … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG7_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG8_HDMI_AUDIO_PACKET_CONTROL … #define mmHDMI_ACR_PACKET_CONTROL … #define mmDIG0_HDMI_ACR_PACKET_CONTROL … #define mmDIG1_HDMI_ACR_PACKET_CONTROL … #define mmDIG2_HDMI_ACR_PACKET_CONTROL … #define mmDIG3_HDMI_ACR_PACKET_CONTROL … #define mmDIG4_HDMI_ACR_PACKET_CONTROL … #define mmDIG5_HDMI_ACR_PACKET_CONTROL … #define mmDIG6_HDMI_ACR_PACKET_CONTROL … #define mmDIG7_HDMI_ACR_PACKET_CONTROL … #define mmDIG8_HDMI_ACR_PACKET_CONTROL … #define mmHDMI_VBI_PACKET_CONTROL … #define mmDIG0_HDMI_VBI_PACKET_CONTROL … #define mmDIG1_HDMI_VBI_PACKET_CONTROL … #define mmDIG2_HDMI_VBI_PACKET_CONTROL … #define mmDIG3_HDMI_VBI_PACKET_CONTROL … #define mmDIG4_HDMI_VBI_PACKET_CONTROL … #define mmDIG5_HDMI_VBI_PACKET_CONTROL … #define mmDIG6_HDMI_VBI_PACKET_CONTROL … #define mmDIG7_HDMI_VBI_PACKET_CONTROL … #define mmDIG8_HDMI_VBI_PACKET_CONTROL … #define mmHDMI_INFOFRAME_CONTROL0 … #define mmDIG0_HDMI_INFOFRAME_CONTROL0 … #define mmDIG1_HDMI_INFOFRAME_CONTROL0 … #define mmDIG2_HDMI_INFOFRAME_CONTROL0 … #define mmDIG3_HDMI_INFOFRAME_CONTROL0 … #define mmDIG4_HDMI_INFOFRAME_CONTROL0 … #define mmDIG5_HDMI_INFOFRAME_CONTROL0 … #define mmDIG6_HDMI_INFOFRAME_CONTROL0 … #define mmDIG7_HDMI_INFOFRAME_CONTROL0 … #define mmDIG8_HDMI_INFOFRAME_CONTROL0 … #define mmHDMI_INFOFRAME_CONTROL1 … #define mmDIG0_HDMI_INFOFRAME_CONTROL1 … #define mmDIG1_HDMI_INFOFRAME_CONTROL1 … #define mmDIG2_HDMI_INFOFRAME_CONTROL1 … #define mmDIG3_HDMI_INFOFRAME_CONTROL1 … #define mmDIG4_HDMI_INFOFRAME_CONTROL1 … #define mmDIG5_HDMI_INFOFRAME_CONTROL1 … #define mmDIG6_HDMI_INFOFRAME_CONTROL1 … #define mmDIG7_HDMI_INFOFRAME_CONTROL1 … #define mmDIG8_HDMI_INFOFRAME_CONTROL1 … #define mmHDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 … #define mmAFMT_INTERRUPT_STATUS … #define mmDIG0_AFMT_INTERRUPT_STATUS … #define mmDIG1_AFMT_INTERRUPT_STATUS … #define mmDIG2_AFMT_INTERRUPT_STATUS … #define mmDIG3_AFMT_INTERRUPT_STATUS … #define mmDIG4_AFMT_INTERRUPT_STATUS … #define mmDIG5_AFMT_INTERRUPT_STATUS … #define mmDIG6_AFMT_INTERRUPT_STATUS … #define mmDIG7_AFMT_INTERRUPT_STATUS … #define mmDIG8_AFMT_INTERRUPT_STATUS … #define mmHDMI_GC … #define mmDIG0_HDMI_GC … #define mmDIG1_HDMI_GC … #define mmDIG2_HDMI_GC … #define mmDIG3_HDMI_GC … #define mmDIG4_HDMI_GC … #define mmDIG5_HDMI_GC … #define mmDIG6_HDMI_GC … #define mmDIG7_HDMI_GC … #define mmDIG8_HDMI_GC … #define mmAFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 … #define mmAFMT_ISRC1_0 … #define mmDIG0_AFMT_ISRC1_0 … #define mmDIG1_AFMT_ISRC1_0 … #define mmDIG2_AFMT_ISRC1_0 … #define mmDIG3_AFMT_ISRC1_0 … #define mmDIG4_AFMT_ISRC1_0 … #define mmDIG5_AFMT_ISRC1_0 … #define mmDIG6_AFMT_ISRC1_0 … #define mmDIG7_AFMT_ISRC1_0 … #define mmDIG8_AFMT_ISRC1_0 … #define mmAFMT_ISRC1_1 … #define mmDIG0_AFMT_ISRC1_1 … #define mmDIG1_AFMT_ISRC1_1 … #define mmDIG2_AFMT_ISRC1_1 … #define mmDIG3_AFMT_ISRC1_1 … #define mmDIG4_AFMT_ISRC1_1 … #define mmDIG5_AFMT_ISRC1_1 … #define mmDIG6_AFMT_ISRC1_1 … #define mmDIG7_AFMT_ISRC1_1 … #define mmDIG8_AFMT_ISRC1_1 … #define mmAFMT_ISRC1_2 … #define mmDIG0_AFMT_ISRC1_2 … #define mmDIG1_AFMT_ISRC1_2 … #define mmDIG2_AFMT_ISRC1_2 … #define mmDIG3_AFMT_ISRC1_2 … #define mmDIG4_AFMT_ISRC1_2 … #define mmDIG5_AFMT_ISRC1_2 … #define mmDIG6_AFMT_ISRC1_2 … #define mmDIG7_AFMT_ISRC1_2 … #define mmDIG8_AFMT_ISRC1_2 … #define mmAFMT_ISRC1_3 … #define mmDIG0_AFMT_ISRC1_3 … #define mmDIG1_AFMT_ISRC1_3 … #define mmDIG2_AFMT_ISRC1_3 … #define mmDIG3_AFMT_ISRC1_3 … #define mmDIG4_AFMT_ISRC1_3 … #define mmDIG5_AFMT_ISRC1_3 … #define mmDIG6_AFMT_ISRC1_3 … #define mmDIG7_AFMT_ISRC1_3 … #define mmDIG8_AFMT_ISRC1_3 … #define mmAFMT_ISRC1_4 … #define mmDIG0_AFMT_ISRC1_4 … #define mmDIG1_AFMT_ISRC1_4 … #define mmDIG2_AFMT_ISRC1_4 … #define mmDIG3_AFMT_ISRC1_4 … #define mmDIG4_AFMT_ISRC1_4 … #define mmDIG5_AFMT_ISRC1_4 … #define mmDIG6_AFMT_ISRC1_4 … #define mmDIG7_AFMT_ISRC1_4 … #define mmDIG8_AFMT_ISRC1_4 … #define mmAFMT_ISRC2_0 … #define mmDIG0_AFMT_ISRC2_0 … #define mmDIG1_AFMT_ISRC2_0 … #define mmDIG2_AFMT_ISRC2_0 … #define mmDIG3_AFMT_ISRC2_0 … #define mmDIG4_AFMT_ISRC2_0 … #define mmDIG5_AFMT_ISRC2_0 … #define mmDIG6_AFMT_ISRC2_0 … #define mmDIG7_AFMT_ISRC2_0 … #define mmDIG8_AFMT_ISRC2_0 … #define mmAFMT_ISRC2_1 … #define mmDIG0_AFMT_ISRC2_1 … #define mmDIG1_AFMT_ISRC2_1 … #define mmDIG2_AFMT_ISRC2_1 … #define mmDIG3_AFMT_ISRC2_1 … #define mmDIG4_AFMT_ISRC2_1 … #define mmDIG5_AFMT_ISRC2_1 … #define mmDIG6_AFMT_ISRC2_1 … #define mmDIG7_AFMT_ISRC2_1 … #define mmDIG8_AFMT_ISRC2_1 … #define mmAFMT_ISRC2_2 … #define mmDIG0_AFMT_ISRC2_2 … #define mmDIG1_AFMT_ISRC2_2 … #define mmDIG2_AFMT_ISRC2_2 … #define mmDIG3_AFMT_ISRC2_2 … #define mmDIG4_AFMT_ISRC2_2 … #define mmDIG5_AFMT_ISRC2_2 … #define mmDIG6_AFMT_ISRC2_2 … #define mmDIG7_AFMT_ISRC2_2 … #define mmDIG8_AFMT_ISRC2_2 … #define mmAFMT_ISRC2_3 … #define mmDIG0_AFMT_ISRC2_3 … #define mmDIG1_AFMT_ISRC2_3 … #define mmDIG2_AFMT_ISRC2_3 … #define mmDIG3_AFMT_ISRC2_3 … #define mmDIG4_AFMT_ISRC2_3 … #define mmDIG5_AFMT_ISRC2_3 … #define mmDIG6_AFMT_ISRC2_3 … #define mmDIG7_AFMT_ISRC2_3 … #define mmDIG8_AFMT_ISRC2_3 … #define mmAFMT_AVI_INFO0 … #define mmDIG0_AFMT_AVI_INFO0 … #define mmDIG1_AFMT_AVI_INFO0 … #define mmDIG2_AFMT_AVI_INFO0 … #define mmDIG3_AFMT_AVI_INFO0 … #define mmDIG4_AFMT_AVI_INFO0 … #define mmDIG5_AFMT_AVI_INFO0 … #define mmDIG6_AFMT_AVI_INFO0 … #define mmDIG7_AFMT_AVI_INFO0 … #define mmDIG8_AFMT_AVI_INFO0 … #define mmAFMT_AVI_INFO1 … #define mmDIG0_AFMT_AVI_INFO1 … #define mmDIG1_AFMT_AVI_INFO1 … #define mmDIG2_AFMT_AVI_INFO1 … #define mmDIG3_AFMT_AVI_INFO1 … #define mmDIG4_AFMT_AVI_INFO1 … #define mmDIG5_AFMT_AVI_INFO1 … #define mmDIG6_AFMT_AVI_INFO1 … #define mmDIG7_AFMT_AVI_INFO1 … #define mmDIG8_AFMT_AVI_INFO1 … #define mmAFMT_AVI_INFO2 … #define mmDIG0_AFMT_AVI_INFO2 … #define mmDIG1_AFMT_AVI_INFO2 … #define mmDIG2_AFMT_AVI_INFO2 … #define mmDIG3_AFMT_AVI_INFO2 … #define mmDIG4_AFMT_AVI_INFO2 … #define mmDIG5_AFMT_AVI_INFO2 … #define mmDIG6_AFMT_AVI_INFO2 … #define mmDIG7_AFMT_AVI_INFO2 … #define mmDIG8_AFMT_AVI_INFO2 … #define mmAFMT_AVI_INFO3 … #define mmDIG0_AFMT_AVI_INFO3 … #define mmDIG1_AFMT_AVI_INFO3 … #define mmDIG2_AFMT_AVI_INFO3 … #define mmDIG3_AFMT_AVI_INFO3 … #define mmDIG4_AFMT_AVI_INFO3 … #define mmDIG5_AFMT_AVI_INFO3 … #define mmDIG6_AFMT_AVI_INFO3 … #define mmDIG7_AFMT_AVI_INFO3 … #define mmDIG8_AFMT_AVI_INFO3 … #define mmAFMT_MPEG_INFO0 … #define mmDIG0_AFMT_MPEG_INFO0 … #define mmDIG1_AFMT_MPEG_INFO0 … #define mmDIG2_AFMT_MPEG_INFO0 … #define mmDIG3_AFMT_MPEG_INFO0 … #define mmDIG4_AFMT_MPEG_INFO0 … #define mmDIG5_AFMT_MPEG_INFO0 … #define mmDIG6_AFMT_MPEG_INFO0 … #define mmDIG7_AFMT_MPEG_INFO0 … #define mmDIG8_AFMT_MPEG_INFO0 … #define mmAFMT_MPEG_INFO1 … #define mmDIG0_AFMT_MPEG_INFO1 … #define mmDIG1_AFMT_MPEG_INFO1 … #define mmDIG2_AFMT_MPEG_INFO1 … #define mmDIG3_AFMT_MPEG_INFO1 … #define mmDIG4_AFMT_MPEG_INFO1 … #define mmDIG5_AFMT_MPEG_INFO1 … #define mmDIG6_AFMT_MPEG_INFO1 … #define mmDIG7_AFMT_MPEG_INFO1 … #define mmDIG8_AFMT_MPEG_INFO1 … #define mmAFMT_GENERIC_HDR … #define mmDIG0_AFMT_GENERIC_HDR … #define mmDIG1_AFMT_GENERIC_HDR … #define mmDIG2_AFMT_GENERIC_HDR … #define mmDIG3_AFMT_GENERIC_HDR … #define mmDIG4_AFMT_GENERIC_HDR … #define mmDIG5_AFMT_GENERIC_HDR … #define mmDIG6_AFMT_GENERIC_HDR … #define mmDIG7_AFMT_GENERIC_HDR … #define mmDIG8_AFMT_GENERIC_HDR … #define mmAFMT_GENERIC_0 … #define mmDIG0_AFMT_GENERIC_0 … #define mmDIG1_AFMT_GENERIC_0 … #define mmDIG2_AFMT_GENERIC_0 … #define mmDIG3_AFMT_GENERIC_0 … #define mmDIG4_AFMT_GENERIC_0 … #define mmDIG5_AFMT_GENERIC_0 … #define mmDIG6_AFMT_GENERIC_0 … #define mmDIG7_AFMT_GENERIC_0 … #define mmDIG8_AFMT_GENERIC_0 … #define mmAFMT_GENERIC_1 … #define mmDIG0_AFMT_GENERIC_1 … #define mmDIG1_AFMT_GENERIC_1 … #define mmDIG2_AFMT_GENERIC_1 … #define mmDIG3_AFMT_GENERIC_1 … #define mmDIG4_AFMT_GENERIC_1 … #define mmDIG5_AFMT_GENERIC_1 … #define mmDIG6_AFMT_GENERIC_1 … #define mmDIG7_AFMT_GENERIC_1 … #define mmDIG8_AFMT_GENERIC_1 … #define mmAFMT_GENERIC_2 … #define mmDIG0_AFMT_GENERIC_2 … #define mmDIG1_AFMT_GENERIC_2 … #define mmDIG2_AFMT_GENERIC_2 … #define mmDIG3_AFMT_GENERIC_2 … #define mmDIG4_AFMT_GENERIC_2 … #define mmDIG5_AFMT_GENERIC_2 … #define mmDIG6_AFMT_GENERIC_2 … #define mmDIG7_AFMT_GENERIC_2 … #define mmDIG8_AFMT_GENERIC_2 … #define mmAFMT_GENERIC_3 … #define mmDIG0_AFMT_GENERIC_3 … #define mmDIG1_AFMT_GENERIC_3 … #define mmDIG2_AFMT_GENERIC_3 … #define mmDIG3_AFMT_GENERIC_3 … #define mmDIG4_AFMT_GENERIC_3 … #define mmDIG5_AFMT_GENERIC_3 … #define mmDIG6_AFMT_GENERIC_3 … #define mmDIG7_AFMT_GENERIC_3 … #define mmDIG8_AFMT_GENERIC_3 … #define mmAFMT_GENERIC_4 … #define mmDIG0_AFMT_GENERIC_4 … #define mmDIG1_AFMT_GENERIC_4 … #define mmDIG2_AFMT_GENERIC_4 … #define mmDIG3_AFMT_GENERIC_4 … #define mmDIG4_AFMT_GENERIC_4 … #define mmDIG5_AFMT_GENERIC_4 … #define mmDIG6_AFMT_GENERIC_4 … #define mmDIG7_AFMT_GENERIC_4 … #define mmDIG8_AFMT_GENERIC_4 … #define mmAFMT_GENERIC_5 … #define mmDIG0_AFMT_GENERIC_5 … #define mmDIG1_AFMT_GENERIC_5 … #define mmDIG2_AFMT_GENERIC_5 … #define mmDIG3_AFMT_GENERIC_5 … #define mmDIG4_AFMT_GENERIC_5 … #define mmDIG5_AFMT_GENERIC_5 … #define mmDIG6_AFMT_GENERIC_5 … #define mmDIG7_AFMT_GENERIC_5 … #define mmDIG8_AFMT_GENERIC_5 … #define mmAFMT_GENERIC_6 … #define mmDIG0_AFMT_GENERIC_6 … #define mmDIG1_AFMT_GENERIC_6 … #define mmDIG2_AFMT_GENERIC_6 … #define mmDIG3_AFMT_GENERIC_6 … #define mmDIG4_AFMT_GENERIC_6 … #define mmDIG5_AFMT_GENERIC_6 … #define mmDIG6_AFMT_GENERIC_6 … #define mmDIG7_AFMT_GENERIC_6 … #define mmDIG8_AFMT_GENERIC_6 … #define mmAFMT_GENERIC_7 … #define mmDIG0_AFMT_GENERIC_7 … #define mmDIG1_AFMT_GENERIC_7 … #define mmDIG2_AFMT_GENERIC_7 … #define mmDIG3_AFMT_GENERIC_7 … #define mmDIG4_AFMT_GENERIC_7 … #define mmDIG5_AFMT_GENERIC_7 … #define mmDIG6_AFMT_GENERIC_7 … #define mmDIG7_AFMT_GENERIC_7 … #define mmDIG8_AFMT_GENERIC_7 … #define mmHDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 … #define mmHDMI_ACR_32_0 … #define mmDIG0_HDMI_ACR_32_0 … #define mmDIG1_HDMI_ACR_32_0 … #define mmDIG2_HDMI_ACR_32_0 … #define mmDIG3_HDMI_ACR_32_0 … #define mmDIG4_HDMI_ACR_32_0 … #define mmDIG5_HDMI_ACR_32_0 … #define mmDIG6_HDMI_ACR_32_0 … #define mmDIG7_HDMI_ACR_32_0 … #define mmDIG8_HDMI_ACR_32_0 … #define mmHDMI_ACR_32_1 … #define mmDIG0_HDMI_ACR_32_1 … #define mmDIG1_HDMI_ACR_32_1 … #define mmDIG2_HDMI_ACR_32_1 … #define mmDIG3_HDMI_ACR_32_1 … #define mmDIG4_HDMI_ACR_32_1 … #define mmDIG5_HDMI_ACR_32_1 … #define mmDIG6_HDMI_ACR_32_1 … #define mmDIG7_HDMI_ACR_32_1 … #define mmDIG8_HDMI_ACR_32_1 … #define mmHDMI_ACR_44_0 … #define mmDIG0_HDMI_ACR_44_0 … #define mmDIG1_HDMI_ACR_44_0 … #define mmDIG2_HDMI_ACR_44_0 … #define mmDIG3_HDMI_ACR_44_0 … #define mmDIG4_HDMI_ACR_44_0 … #define mmDIG5_HDMI_ACR_44_0 … #define mmDIG6_HDMI_ACR_44_0 … #define mmDIG7_HDMI_ACR_44_0 … #define mmDIG8_HDMI_ACR_44_0 … #define mmHDMI_ACR_44_1 … #define mmDIG0_HDMI_ACR_44_1 … #define mmDIG1_HDMI_ACR_44_1 … #define mmDIG2_HDMI_ACR_44_1 … #define mmDIG3_HDMI_ACR_44_1 … #define mmDIG4_HDMI_ACR_44_1 … #define mmDIG5_HDMI_ACR_44_1 … #define mmDIG6_HDMI_ACR_44_1 … #define mmDIG7_HDMI_ACR_44_1 … #define mmDIG8_HDMI_ACR_44_1 … #define mmHDMI_ACR_48_0 … #define mmDIG0_HDMI_ACR_48_0 … #define mmDIG1_HDMI_ACR_48_0 … #define mmDIG2_HDMI_ACR_48_0 … #define mmDIG3_HDMI_ACR_48_0 … #define mmDIG4_HDMI_ACR_48_0 … #define mmDIG5_HDMI_ACR_48_0 … #define mmDIG6_HDMI_ACR_48_0 … #define mmDIG7_HDMI_ACR_48_0 … #define mmDIG8_HDMI_ACR_48_0 … #define mmHDMI_ACR_48_1 … #define mmDIG0_HDMI_ACR_48_1 … #define mmDIG1_HDMI_ACR_48_1 … #define mmDIG2_HDMI_ACR_48_1 … #define mmDIG3_HDMI_ACR_48_1 … #define mmDIG4_HDMI_ACR_48_1 … #define mmDIG5_HDMI_ACR_48_1 … #define mmDIG6_HDMI_ACR_48_1 … #define mmDIG7_HDMI_ACR_48_1 … #define mmDIG8_HDMI_ACR_48_1 … #define mmHDMI_ACR_STATUS_0 … #define mmDIG0_HDMI_ACR_STATUS_0 … #define mmDIG1_HDMI_ACR_STATUS_0 … #define mmDIG2_HDMI_ACR_STATUS_0 … #define mmDIG3_HDMI_ACR_STATUS_0 … #define mmDIG4_HDMI_ACR_STATUS_0 … #define mmDIG5_HDMI_ACR_STATUS_0 … #define mmDIG6_HDMI_ACR_STATUS_0 … #define mmDIG7_HDMI_ACR_STATUS_0 … #define mmDIG8_HDMI_ACR_STATUS_0 … #define mmHDMI_ACR_STATUS_1 … #define mmDIG0_HDMI_ACR_STATUS_1 … #define mmDIG1_HDMI_ACR_STATUS_1 … #define mmDIG2_HDMI_ACR_STATUS_1 … #define mmDIG3_HDMI_ACR_STATUS_1 … #define mmDIG4_HDMI_ACR_STATUS_1 … #define mmDIG5_HDMI_ACR_STATUS_1 … #define mmDIG6_HDMI_ACR_STATUS_1 … #define mmDIG7_HDMI_ACR_STATUS_1 … #define mmDIG8_HDMI_ACR_STATUS_1 … #define mmAFMT_AUDIO_INFO0 … #define mmDIG0_AFMT_AUDIO_INFO0 … #define mmDIG1_AFMT_AUDIO_INFO0 … #define mmDIG2_AFMT_AUDIO_INFO0 … #define mmDIG3_AFMT_AUDIO_INFO0 … #define mmDIG4_AFMT_AUDIO_INFO0 … #define mmDIG5_AFMT_AUDIO_INFO0 … #define mmDIG6_AFMT_AUDIO_INFO0 … #define mmDIG7_AFMT_AUDIO_INFO0 … #define mmDIG8_AFMT_AUDIO_INFO0 … #define mmAFMT_AUDIO_INFO1 … #define mmDIG0_AFMT_AUDIO_INFO1 … #define mmDIG1_AFMT_AUDIO_INFO1 … #define mmDIG2_AFMT_AUDIO_INFO1 … #define mmDIG3_AFMT_AUDIO_INFO1 … #define mmDIG4_AFMT_AUDIO_INFO1 … #define mmDIG5_AFMT_AUDIO_INFO1 … #define mmDIG6_AFMT_AUDIO_INFO1 … #define mmDIG7_AFMT_AUDIO_INFO1 … #define mmDIG8_AFMT_AUDIO_INFO1 … #define mmAFMT_60958_0 … #define mmDIG0_AFMT_60958_0 … #define mmDIG1_AFMT_60958_0 … #define mmDIG2_AFMT_60958_0 … #define mmDIG3_AFMT_60958_0 … #define mmDIG4_AFMT_60958_0 … #define mmDIG5_AFMT_60958_0 … #define mmDIG6_AFMT_60958_0 … #define mmDIG7_AFMT_60958_0 … #define mmDIG8_AFMT_60958_0 … #define mmAFMT_60958_1 … #define mmDIG0_AFMT_60958_1 … #define mmDIG1_AFMT_60958_1 … #define mmDIG2_AFMT_60958_1 … #define mmDIG3_AFMT_60958_1 … #define mmDIG4_AFMT_60958_1 … #define mmDIG5_AFMT_60958_1 … #define mmDIG6_AFMT_60958_1 … #define mmDIG7_AFMT_60958_1 … #define mmDIG8_AFMT_60958_1 … #define mmAFMT_AUDIO_CRC_CONTROL … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL … #define mmDIG2_AFMT_AUDIO_CRC_CONTROL … #define mmDIG3_AFMT_AUDIO_CRC_CONTROL … #define mmDIG4_AFMT_AUDIO_CRC_CONTROL … #define mmDIG5_AFMT_AUDIO_CRC_CONTROL … #define mmDIG6_AFMT_AUDIO_CRC_CONTROL … #define mmDIG7_AFMT_AUDIO_CRC_CONTROL … #define mmDIG8_AFMT_AUDIO_CRC_CONTROL … #define mmAFMT_RAMP_CONTROL0 … #define mmDIG0_AFMT_RAMP_CONTROL0 … #define mmDIG1_AFMT_RAMP_CONTROL0 … #define mmDIG2_AFMT_RAMP_CONTROL0 … #define mmDIG3_AFMT_RAMP_CONTROL0 … #define mmDIG4_AFMT_RAMP_CONTROL0 … #define mmDIG5_AFMT_RAMP_CONTROL0 … #define mmDIG6_AFMT_RAMP_CONTROL0 … #define mmDIG7_AFMT_RAMP_CONTROL0 … #define mmDIG8_AFMT_RAMP_CONTROL0 … #define mmAFMT_RAMP_CONTROL1 … #define mmDIG0_AFMT_RAMP_CONTROL1 … #define mmDIG1_AFMT_RAMP_CONTROL1 … #define mmDIG2_AFMT_RAMP_CONTROL1 … #define mmDIG3_AFMT_RAMP_CONTROL1 … #define mmDIG4_AFMT_RAMP_CONTROL1 … #define mmDIG5_AFMT_RAMP_CONTROL1 … #define mmDIG6_AFMT_RAMP_CONTROL1 … #define mmDIG7_AFMT_RAMP_CONTROL1 … #define mmDIG8_AFMT_RAMP_CONTROL1 … #define mmAFMT_RAMP_CONTROL2 … #define mmDIG0_AFMT_RAMP_CONTROL2 … #define mmDIG1_AFMT_RAMP_CONTROL2 … #define mmDIG2_AFMT_RAMP_CONTROL2 … #define mmDIG3_AFMT_RAMP_CONTROL2 … #define mmDIG4_AFMT_RAMP_CONTROL2 … #define mmDIG5_AFMT_RAMP_CONTROL2 … #define mmDIG6_AFMT_RAMP_CONTROL2 … #define mmDIG7_AFMT_RAMP_CONTROL2 … #define mmDIG8_AFMT_RAMP_CONTROL2 … #define mmAFMT_RAMP_CONTROL3 … #define mmDIG0_AFMT_RAMP_CONTROL3 … #define mmDIG1_AFMT_RAMP_CONTROL3 … #define mmDIG2_AFMT_RAMP_CONTROL3 … #define mmDIG3_AFMT_RAMP_CONTROL3 … #define mmDIG4_AFMT_RAMP_CONTROL3 … #define mmDIG5_AFMT_RAMP_CONTROL3 … #define mmDIG6_AFMT_RAMP_CONTROL3 … #define mmDIG7_AFMT_RAMP_CONTROL3 … #define mmDIG8_AFMT_RAMP_CONTROL3 … #define mmAFMT_60958_2 … #define mmDIG0_AFMT_60958_2 … #define mmDIG1_AFMT_60958_2 … #define mmDIG2_AFMT_60958_2 … #define mmDIG3_AFMT_60958_2 … #define mmDIG4_AFMT_60958_2 … #define mmDIG5_AFMT_60958_2 … #define mmDIG6_AFMT_60958_2 … #define mmDIG7_AFMT_60958_2 … #define mmDIG8_AFMT_60958_2 … #define mmAFMT_AUDIO_CRC_RESULT … #define mmDIG0_AFMT_AUDIO_CRC_RESULT … #define mmDIG1_AFMT_AUDIO_CRC_RESULT … #define mmDIG2_AFMT_AUDIO_CRC_RESULT … #define mmDIG3_AFMT_AUDIO_CRC_RESULT … #define mmDIG4_AFMT_AUDIO_CRC_RESULT … #define mmDIG5_AFMT_AUDIO_CRC_RESULT … #define mmDIG6_AFMT_AUDIO_CRC_RESULT … #define mmDIG7_AFMT_AUDIO_CRC_RESULT … #define mmDIG8_AFMT_AUDIO_CRC_RESULT … #define mmAFMT_STATUS … #define mmDIG0_AFMT_STATUS … #define mmDIG1_AFMT_STATUS … #define mmDIG2_AFMT_STATUS … #define mmDIG3_AFMT_STATUS … #define mmDIG4_AFMT_STATUS … #define mmDIG5_AFMT_STATUS … #define mmDIG6_AFMT_STATUS … #define mmDIG7_AFMT_STATUS … #define mmDIG8_AFMT_STATUS … #define mmAFMT_AUDIO_PACKET_CONTROL … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL … #define mmAFMT_VBI_PACKET_CONTROL … #define mmDIG0_AFMT_VBI_PACKET_CONTROL … #define mmDIG1_AFMT_VBI_PACKET_CONTROL … #define mmDIG2_AFMT_VBI_PACKET_CONTROL … #define mmDIG3_AFMT_VBI_PACKET_CONTROL … #define mmDIG4_AFMT_VBI_PACKET_CONTROL … #define mmDIG5_AFMT_VBI_PACKET_CONTROL … #define mmDIG6_AFMT_VBI_PACKET_CONTROL … #define mmDIG7_AFMT_VBI_PACKET_CONTROL … #define mmDIG8_AFMT_VBI_PACKET_CONTROL … #define mmAFMT_INFOFRAME_CONTROL0 … #define mmDIG0_AFMT_INFOFRAME_CONTROL0 … #define mmDIG1_AFMT_INFOFRAME_CONTROL0 … #define mmDIG2_AFMT_INFOFRAME_CONTROL0 … #define mmDIG3_AFMT_INFOFRAME_CONTROL0 … #define mmDIG4_AFMT_INFOFRAME_CONTROL0 … #define mmDIG5_AFMT_INFOFRAME_CONTROL0 … #define mmDIG6_AFMT_INFOFRAME_CONTROL0 … #define mmDIG7_AFMT_INFOFRAME_CONTROL0 … #define mmDIG8_AFMT_INFOFRAME_CONTROL0 … #define mmAFMT_AUDIO_SRC_CONTROL … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL … #define mmDIG2_AFMT_AUDIO_SRC_CONTROL … #define mmDIG3_AFMT_AUDIO_SRC_CONTROL … #define mmDIG4_AFMT_AUDIO_SRC_CONTROL … #define mmDIG5_AFMT_AUDIO_SRC_CONTROL … #define mmDIG6_AFMT_AUDIO_SRC_CONTROL … #define mmDIG7_AFMT_AUDIO_SRC_CONTROL … #define mmDIG8_AFMT_AUDIO_SRC_CONTROL … #define mmAFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL … #define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL … #define mmAFMT_CNTL … #define mmDIG0_AFMT_CNTL … #define mmDIG1_AFMT_CNTL … #define mmDIG2_AFMT_CNTL … #define mmDIG3_AFMT_CNTL … #define mmDIG4_AFMT_CNTL … #define mmDIG5_AFMT_CNTL … #define mmDIG6_AFMT_CNTL … #define mmDIG7_AFMT_CNTL … #define mmDIG8_AFMT_CNTL … #define mmDIG_BE_CNTL … #define mmDIG0_DIG_BE_CNTL … #define mmDIG1_DIG_BE_CNTL … #define mmDIG2_DIG_BE_CNTL … #define mmDIG3_DIG_BE_CNTL … #define mmDIG4_DIG_BE_CNTL … #define mmDIG5_DIG_BE_CNTL … #define mmDIG6_DIG_BE_CNTL … #define mmDIG7_DIG_BE_CNTL … #define mmDIG8_DIG_BE_CNTL … #define mmDIG_BE_EN_CNTL … #define mmDIG0_DIG_BE_EN_CNTL … #define mmDIG1_DIG_BE_EN_CNTL … #define mmDIG2_DIG_BE_EN_CNTL … #define mmDIG3_DIG_BE_EN_CNTL … #define mmDIG4_DIG_BE_EN_CNTL … #define mmDIG5_DIG_BE_EN_CNTL … #define mmDIG6_DIG_BE_EN_CNTL … #define mmDIG7_DIG_BE_EN_CNTL … #define mmDIG8_DIG_BE_EN_CNTL … #define mmTMDS_CNTL … #define mmDIG0_TMDS_CNTL … #define mmDIG1_TMDS_CNTL … #define mmDIG2_TMDS_CNTL … #define mmDIG3_TMDS_CNTL … #define mmDIG4_TMDS_CNTL … #define mmDIG5_TMDS_CNTL … #define mmDIG6_TMDS_CNTL … #define mmDIG7_TMDS_CNTL … #define mmDIG8_TMDS_CNTL … #define mmTMDS_CONTROL_CHAR … #define mmDIG0_TMDS_CONTROL_CHAR … #define mmDIG1_TMDS_CONTROL_CHAR … #define mmDIG2_TMDS_CONTROL_CHAR … #define mmDIG3_TMDS_CONTROL_CHAR … #define mmDIG4_TMDS_CONTROL_CHAR … #define mmDIG5_TMDS_CONTROL_CHAR … #define mmDIG6_TMDS_CONTROL_CHAR … #define mmDIG7_TMDS_CONTROL_CHAR … #define mmDIG8_TMDS_CONTROL_CHAR … #define mmTMDS_CONTROL0_FEEDBACK … #define mmDIG0_TMDS_CONTROL0_FEEDBACK … #define mmDIG1_TMDS_CONTROL0_FEEDBACK … #define mmDIG2_TMDS_CONTROL0_FEEDBACK … #define mmDIG3_TMDS_CONTROL0_FEEDBACK … #define mmDIG4_TMDS_CONTROL0_FEEDBACK … #define mmDIG5_TMDS_CONTROL0_FEEDBACK … #define mmDIG6_TMDS_CONTROL0_FEEDBACK … #define mmDIG7_TMDS_CONTROL0_FEEDBACK … #define mmDIG8_TMDS_CONTROL0_FEEDBACK … #define mmTMDS_STEREOSYNC_CTL_SEL … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG7_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG8_TMDS_STEREOSYNC_CTL_SEL … #define mmTMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmTMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmTMDS_DEBUG … #define mmDIG0_TMDS_DEBUG … #define mmDIG1_TMDS_DEBUG … #define mmDIG2_TMDS_DEBUG … #define mmDIG3_TMDS_DEBUG … #define mmDIG4_TMDS_DEBUG … #define mmDIG5_TMDS_DEBUG … #define mmDIG6_TMDS_DEBUG … #define mmDIG7_TMDS_DEBUG … #define mmDIG8_TMDS_DEBUG … #define mmTMDS_CTL_BITS … #define mmDIG0_TMDS_CTL_BITS … #define mmDIG1_TMDS_CTL_BITS … #define mmDIG2_TMDS_CTL_BITS … #define mmDIG3_TMDS_CTL_BITS … #define mmDIG4_TMDS_CTL_BITS … #define mmDIG5_TMDS_CTL_BITS … #define mmDIG6_TMDS_CTL_BITS … #define mmDIG7_TMDS_CTL_BITS … #define mmDIG8_TMDS_CTL_BITS … #define mmTMDS_DCBALANCER_CONTROL … #define mmDIG0_TMDS_DCBALANCER_CONTROL … #define mmDIG1_TMDS_DCBALANCER_CONTROL … #define mmDIG2_TMDS_DCBALANCER_CONTROL … #define mmDIG3_TMDS_DCBALANCER_CONTROL … #define mmDIG4_TMDS_DCBALANCER_CONTROL … #define mmDIG5_TMDS_DCBALANCER_CONTROL … #define mmDIG6_TMDS_DCBALANCER_CONTROL … #define mmDIG7_TMDS_DCBALANCER_CONTROL … #define mmDIG8_TMDS_DCBALANCER_CONTROL … #define mmTMDS_CTL0_1_GEN_CNTL … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL … #define mmDIG2_TMDS_CTL0_1_GEN_CNTL … #define mmDIG3_TMDS_CTL0_1_GEN_CNTL … #define mmDIG4_TMDS_CTL0_1_GEN_CNTL … #define mmDIG5_TMDS_CTL0_1_GEN_CNTL … #define mmDIG6_TMDS_CTL0_1_GEN_CNTL … #define mmDIG7_TMDS_CTL0_1_GEN_CNTL … #define mmDIG8_TMDS_CTL0_1_GEN_CNTL … #define mmTMDS_CTL2_3_GEN_CNTL … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL … #define mmDIG2_TMDS_CTL2_3_GEN_CNTL … #define mmDIG3_TMDS_CTL2_3_GEN_CNTL … #define mmDIG4_TMDS_CTL2_3_GEN_CNTL … #define mmDIG5_TMDS_CTL2_3_GEN_CNTL … #define mmDIG6_TMDS_CTL2_3_GEN_CNTL … #define mmDIG7_TMDS_CTL2_3_GEN_CNTL … #define mmDIG8_TMDS_CTL2_3_GEN_CNTL … #define mmDIG_VERSION … #define mmDIG0_DIG_VERSION … #define mmDIG1_DIG_VERSION … #define mmDIG2_DIG_VERSION … #define mmDIG3_DIG_VERSION … #define mmDIG4_DIG_VERSION … #define mmDIG5_DIG_VERSION … #define mmDIG6_DIG_VERSION … #define mmDIG7_DIG_VERSION … #define mmDIG8_DIG_VERSION … #define mmDIG_LANE_ENABLE … #define mmDIG0_DIG_LANE_ENABLE … #define mmDIG1_DIG_LANE_ENABLE … #define mmDIG2_DIG_LANE_ENABLE … #define mmDIG3_DIG_LANE_ENABLE … #define mmDIG4_DIG_LANE_ENABLE … #define mmDIG5_DIG_LANE_ENABLE … #define mmDIG6_DIG_LANE_ENABLE … #define mmDIG7_DIG_LANE_ENABLE … #define mmDIG8_DIG_LANE_ENABLE … #define mmDIG_TEST_DEBUG_INDEX … #define mmDIG0_DIG_TEST_DEBUG_INDEX … #define mmDIG1_DIG_TEST_DEBUG_INDEX … #define mmDIG2_DIG_TEST_DEBUG_INDEX … #define mmDIG3_DIG_TEST_DEBUG_INDEX … #define mmDIG4_DIG_TEST_DEBUG_INDEX … #define mmDIG5_DIG_TEST_DEBUG_INDEX … #define mmDIG6_DIG_TEST_DEBUG_INDEX … #define mmDIG7_DIG_TEST_DEBUG_INDEX … #define mmDIG8_DIG_TEST_DEBUG_INDEX … #define mmDIG_TEST_DEBUG_DATA … #define mmDIG0_DIG_TEST_DEBUG_DATA … #define mmDIG1_DIG_TEST_DEBUG_DATA … #define mmDIG2_DIG_TEST_DEBUG_DATA … #define mmDIG3_DIG_TEST_DEBUG_DATA … #define mmDIG4_DIG_TEST_DEBUG_DATA … #define mmDIG5_DIG_TEST_DEBUG_DATA … #define mmDIG6_DIG_TEST_DEBUG_DATA … #define mmDIG7_DIG_TEST_DEBUG_DATA … #define mmDIG8_DIG_TEST_DEBUG_DATA … #define mmDIG_FE_TEST_DEBUG_INDEX … #define mmDIG0_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG1_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG2_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG3_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG4_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG5_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG6_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG7_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG8_DIG_FE_TEST_DEBUG_INDEX … #define mmDIG_FE_TEST_DEBUG_DATA … #define mmDIG0_DIG_FE_TEST_DEBUG_DATA … #define mmDIG1_DIG_FE_TEST_DEBUG_DATA … #define mmDIG2_DIG_FE_TEST_DEBUG_DATA … #define mmDIG3_DIG_FE_TEST_DEBUG_DATA … #define mmDIG4_DIG_FE_TEST_DEBUG_DATA … #define mmDIG5_DIG_FE_TEST_DEBUG_DATA … #define mmDIG6_DIG_FE_TEST_DEBUG_DATA … #define mmDIG7_DIG_FE_TEST_DEBUG_DATA … #define mmDIG8_DIG_FE_TEST_DEBUG_DATA … #define mmDMCU_CTRL … #define mmDMCU_STATUS … #define mmDMCU_PC_START_ADDR … #define mmDMCU_FW_START_ADDR … #define mmDMCU_FW_END_ADDR … #define mmDMCU_FW_ISR_START_ADDR … #define mmDMCU_FW_CS_HI … #define mmDMCU_FW_CS_LO … #define mmDMCU_RAM_ACCESS_CTRL … #define mmDMCU_ERAM_WR_CTRL … #define mmDMCU_ERAM_WR_DATA … #define mmDMCU_ERAM_RD_CTRL … #define mmDMCU_ERAM_RD_DATA … #define mmDMCU_IRAM_WR_CTRL … #define mmDMCU_IRAM_WR_DATA … #define mmDMCU_IRAM_RD_CTRL … #define mmDMCU_IRAM_RD_DATA … #define mmDMCU_EVENT_TRIGGER … #define mmDMCU_UC_INTERNAL_INT_STATUS … #define mmDMCU_SS_INTERRUPT_CNTL_STATUS … #define mmDMCU_INTERRUPT_STATUS … #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 … #define mmDC_DMCU_SCRATCH … #define mmDMCU_INT_CNT … #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS … #define mmDMCU_UC_CLK_GATING_CNTL … #define mmMASTER_COMM_DATA_REG1 … #define mmMASTER_COMM_DATA_REG2 … #define mmMASTER_COMM_DATA_REG3 … #define mmMASTER_COMM_CMD_REG … #define mmMASTER_COMM_CNTL_REG … #define mmSLAVE_COMM_DATA_REG1 … #define mmSLAVE_COMM_DATA_REG2 … #define mmSLAVE_COMM_DATA_REG3 … #define mmSLAVE_COMM_CMD_REG … #define mmSLAVE_COMM_CNTL_REG … #define mmDMCU_TEST_DEBUG_INDEX … #define mmDMCU_TEST_DEBUG_DATA … #define mmDMCU_PERFMON_INTERRUPT_STATUS1 … #define mmDMCU_PERFMON_INTERRUPT_STATUS2 … #define mmDMCU_PERFMON_INTERRUPT_STATUS3 … #define mmDMCU_PERFMON_INTERRUPT_STATUS4 … #define mmDMCU_PERFMON_INTERRUPT_STATUS5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 … #define mmDMCU_DPRX_INTERRUPT_STATUS1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDP_LINK_CNTL … #define mmDP0_DP_LINK_CNTL … #define mmDP1_DP_LINK_CNTL … #define mmDP2_DP_LINK_CNTL … #define mmDP3_DP_LINK_CNTL … #define mmDP4_DP_LINK_CNTL … #define mmDP5_DP_LINK_CNTL … #define mmDP6_DP_LINK_CNTL … #define mmDP7_DP_LINK_CNTL … #define mmDP8_DP_LINK_CNTL … #define mmDP_PIXEL_FORMAT … #define mmDP0_DP_PIXEL_FORMAT … #define mmDP1_DP_PIXEL_FORMAT … #define mmDP2_DP_PIXEL_FORMAT … #define mmDP3_DP_PIXEL_FORMAT … #define mmDP4_DP_PIXEL_FORMAT … #define mmDP5_DP_PIXEL_FORMAT … #define mmDP6_DP_PIXEL_FORMAT … #define mmDP7_DP_PIXEL_FORMAT … #define mmDP8_DP_PIXEL_FORMAT … #define mmDP_MSA_COLORIMETRY … #define mmDP0_DP_MSA_COLORIMETRY … #define mmDP1_DP_MSA_COLORIMETRY … #define mmDP2_DP_MSA_COLORIMETRY … #define mmDP3_DP_MSA_COLORIMETRY … #define mmDP4_DP_MSA_COLORIMETRY … #define mmDP5_DP_MSA_COLORIMETRY … #define mmDP6_DP_MSA_COLORIMETRY … #define mmDP7_DP_MSA_COLORIMETRY … #define mmDP8_DP_MSA_COLORIMETRY … #define mmDP_CONFIG … #define mmDP0_DP_CONFIG … #define mmDP1_DP_CONFIG … #define mmDP2_DP_CONFIG … #define mmDP3_DP_CONFIG … #define mmDP4_DP_CONFIG … #define mmDP5_DP_CONFIG … #define mmDP6_DP_CONFIG … #define mmDP7_DP_CONFIG … #define mmDP8_DP_CONFIG … #define mmDP_VID_STREAM_CNTL … #define mmDP0_DP_VID_STREAM_CNTL … #define mmDP1_DP_VID_STREAM_CNTL … #define mmDP2_DP_VID_STREAM_CNTL … #define mmDP3_DP_VID_STREAM_CNTL … #define mmDP4_DP_VID_STREAM_CNTL … #define mmDP5_DP_VID_STREAM_CNTL … #define mmDP6_DP_VID_STREAM_CNTL … #define mmDP7_DP_VID_STREAM_CNTL … #define mmDP8_DP_VID_STREAM_CNTL … #define mmDP_STEER_FIFO … #define mmDP0_DP_STEER_FIFO … #define mmDP1_DP_STEER_FIFO … #define mmDP2_DP_STEER_FIFO … #define mmDP3_DP_STEER_FIFO … #define mmDP4_DP_STEER_FIFO … #define mmDP5_DP_STEER_FIFO … #define mmDP6_DP_STEER_FIFO … #define mmDP7_DP_STEER_FIFO … #define mmDP8_DP_STEER_FIFO … #define mmDP_MSA_MISC … #define mmDP0_DP_MSA_MISC … #define mmDP1_DP_MSA_MISC … #define mmDP2_DP_MSA_MISC … #define mmDP3_DP_MSA_MISC … #define mmDP4_DP_MSA_MISC … #define mmDP5_DP_MSA_MISC … #define mmDP6_DP_MSA_MISC … #define mmDP7_DP_MSA_MISC … #define mmDP8_DP_MSA_MISC … #define mmDP_VID_TIMING … #define mmDP0_DP_VID_TIMING … #define mmDP1_DP_VID_TIMING … #define mmDP2_DP_VID_TIMING … #define mmDP3_DP_VID_TIMING … #define mmDP4_DP_VID_TIMING … #define mmDP5_DP_VID_TIMING … #define mmDP6_DP_VID_TIMING … #define mmDP7_DP_VID_TIMING … #define mmDP8_DP_VID_TIMING … #define mmDP_VID_N … #define mmDP0_DP_VID_N … #define mmDP1_DP_VID_N … #define mmDP2_DP_VID_N … #define mmDP3_DP_VID_N … #define mmDP4_DP_VID_N … #define mmDP5_DP_VID_N … #define mmDP6_DP_VID_N … #define mmDP7_DP_VID_N … #define mmDP8_DP_VID_N … #define mmDP_VID_M … #define mmDP0_DP_VID_M … #define mmDP1_DP_VID_M … #define mmDP2_DP_VID_M … #define mmDP3_DP_VID_M … #define mmDP4_DP_VID_M … #define mmDP5_DP_VID_M … #define mmDP6_DP_VID_M … #define mmDP7_DP_VID_M … #define mmDP8_DP_VID_M … #define mmDP_LINK_FRAMING_CNTL … #define mmDP0_DP_LINK_FRAMING_CNTL … #define mmDP1_DP_LINK_FRAMING_CNTL … #define mmDP2_DP_LINK_FRAMING_CNTL … #define mmDP3_DP_LINK_FRAMING_CNTL … #define mmDP4_DP_LINK_FRAMING_CNTL … #define mmDP5_DP_LINK_FRAMING_CNTL … #define mmDP6_DP_LINK_FRAMING_CNTL … #define mmDP7_DP_LINK_FRAMING_CNTL … #define mmDP8_DP_LINK_FRAMING_CNTL … #define mmDP_HBR2_EYE_PATTERN … #define mmDP0_DP_HBR2_EYE_PATTERN … #define mmDP1_DP_HBR2_EYE_PATTERN … #define mmDP2_DP_HBR2_EYE_PATTERN … #define mmDP3_DP_HBR2_EYE_PATTERN … #define mmDP4_DP_HBR2_EYE_PATTERN … #define mmDP5_DP_HBR2_EYE_PATTERN … #define mmDP6_DP_HBR2_EYE_PATTERN … #define mmDP7_DP_HBR2_EYE_PATTERN … #define mmDP8_DP_HBR2_EYE_PATTERN … #define mmDP_VID_MSA_VBID … #define mmDP0_DP_VID_MSA_VBID … #define mmDP1_DP_VID_MSA_VBID … #define mmDP2_DP_VID_MSA_VBID … #define mmDP3_DP_VID_MSA_VBID … #define mmDP4_DP_VID_MSA_VBID … #define mmDP5_DP_VID_MSA_VBID … #define mmDP6_DP_VID_MSA_VBID … #define mmDP7_DP_VID_MSA_VBID … #define mmDP8_DP_VID_MSA_VBID … #define mmDP_VID_INTERRUPT_CNTL … #define mmDP0_DP_VID_INTERRUPT_CNTL … #define mmDP1_DP_VID_INTERRUPT_CNTL … #define mmDP2_DP_VID_INTERRUPT_CNTL … #define mmDP3_DP_VID_INTERRUPT_CNTL … #define mmDP4_DP_VID_INTERRUPT_CNTL … #define mmDP5_DP_VID_INTERRUPT_CNTL … #define mmDP6_DP_VID_INTERRUPT_CNTL … #define mmDP7_DP_VID_INTERRUPT_CNTL … #define mmDP8_DP_VID_INTERRUPT_CNTL … #define mmDP_DPHY_CNTL … #define mmDP0_DP_DPHY_CNTL … #define mmDP1_DP_DPHY_CNTL … #define mmDP2_DP_DPHY_CNTL … #define mmDP3_DP_DPHY_CNTL … #define mmDP4_DP_DPHY_CNTL … #define mmDP5_DP_DPHY_CNTL … #define mmDP6_DP_DPHY_CNTL … #define mmDP7_DP_DPHY_CNTL … #define mmDP8_DP_DPHY_CNTL … #define mmDP_DPHY_TRAINING_PATTERN_SEL … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP_DPHY_SYM0 … #define mmDP0_DP_DPHY_SYM0 … #define mmDP1_DP_DPHY_SYM0 … #define mmDP2_DP_DPHY_SYM0 … #define mmDP3_DP_DPHY_SYM0 … #define mmDP4_DP_DPHY_SYM0 … #define mmDP5_DP_DPHY_SYM0 … #define mmDP6_DP_DPHY_SYM0 … #define mmDP7_DP_DPHY_SYM0 … #define mmDP8_DP_DPHY_SYM0 … #define mmDP_DPHY_SYM1 … #define mmDP0_DP_DPHY_SYM1 … #define mmDP1_DP_DPHY_SYM1 … #define mmDP2_DP_DPHY_SYM1 … #define mmDP3_DP_DPHY_SYM1 … #define mmDP4_DP_DPHY_SYM1 … #define mmDP5_DP_DPHY_SYM1 … #define mmDP6_DP_DPHY_SYM1 … #define mmDP7_DP_DPHY_SYM1 … #define mmDP8_DP_DPHY_SYM1 … #define mmDP_DPHY_SYM2 … #define mmDP0_DP_DPHY_SYM2 … #define mmDP1_DP_DPHY_SYM2 … #define mmDP2_DP_DPHY_SYM2 … #define mmDP3_DP_DPHY_SYM2 … #define mmDP4_DP_DPHY_SYM2 … #define mmDP5_DP_DPHY_SYM2 … #define mmDP6_DP_DPHY_SYM2 … #define mmDP7_DP_DPHY_SYM2 … #define mmDP8_DP_DPHY_SYM2 … #define mmDP_DPHY_8B10B_CNTL … #define mmDP0_DP_DPHY_8B10B_CNTL … #define mmDP1_DP_DPHY_8B10B_CNTL … #define mmDP2_DP_DPHY_8B10B_CNTL … #define mmDP3_DP_DPHY_8B10B_CNTL … #define mmDP4_DP_DPHY_8B10B_CNTL … #define mmDP5_DP_DPHY_8B10B_CNTL … #define mmDP6_DP_DPHY_8B10B_CNTL … #define mmDP7_DP_DPHY_8B10B_CNTL … #define mmDP8_DP_DPHY_8B10B_CNTL … #define mmDP_DPHY_PRBS_CNTL … #define mmDP0_DP_DPHY_PRBS_CNTL … #define mmDP1_DP_DPHY_PRBS_CNTL … #define mmDP2_DP_DPHY_PRBS_CNTL … #define mmDP3_DP_DPHY_PRBS_CNTL … #define mmDP4_DP_DPHY_PRBS_CNTL … #define mmDP5_DP_DPHY_PRBS_CNTL … #define mmDP6_DP_DPHY_PRBS_CNTL … #define mmDP7_DP_DPHY_PRBS_CNTL … #define mmDP8_DP_DPHY_PRBS_CNTL … #define mmDP_DPHY_SCRAM_CNTL … #define mmDP0_DP_DPHY_SCRAM_CNTL … #define mmDP1_DP_DPHY_SCRAM_CNTL … #define mmDP2_DP_DPHY_SCRAM_CNTL … #define mmDP3_DP_DPHY_SCRAM_CNTL … #define mmDP4_DP_DPHY_SCRAM_CNTL … #define mmDP5_DP_DPHY_SCRAM_CNTL … #define mmDP6_DP_DPHY_SCRAM_CNTL … #define mmDP8_DP_DPHY_SCRAM_CNTL … #define mmDP_DPHY_BS_SR_SWAP_CNTL … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP_DPHY_CRC_EN … #define mmDP0_DP_DPHY_CRC_EN … #define mmDP1_DP_DPHY_CRC_EN … #define mmDP2_DP_DPHY_CRC_EN … #define mmDP3_DP_DPHY_CRC_EN … #define mmDP4_DP_DPHY_CRC_EN … #define mmDP5_DP_DPHY_CRC_EN … #define mmDP6_DP_DPHY_CRC_EN … #define mmDP7_DP_DPHY_CRC_EN … #define mmDP8_DP_DPHY_CRC_EN … #define mmDP_DPHY_CRC_CNTL … #define mmDP0_DP_DPHY_CRC_CNTL … #define mmDP1_DP_DPHY_CRC_CNTL … #define mmDP2_DP_DPHY_CRC_CNTL … #define mmDP3_DP_DPHY_CRC_CNTL … #define mmDP4_DP_DPHY_CRC_CNTL … #define mmDP5_DP_DPHY_CRC_CNTL … #define mmDP6_DP_DPHY_CRC_CNTL … #define mmDP7_DP_DPHY_CRC_CNTL … #define mmDP8_DP_DPHY_CRC_CNTL … #define mmDP_DPHY_CRC_RESULT … #define mmDP0_DP_DPHY_CRC_RESULT … #define mmDP1_DP_DPHY_CRC_RESULT … #define mmDP2_DP_DPHY_CRC_RESULT … #define mmDP3_DP_DPHY_CRC_RESULT … #define mmDP4_DP_DPHY_CRC_RESULT … #define mmDP5_DP_DPHY_CRC_RESULT … #define mmDP6_DP_DPHY_CRC_RESULT … #define mmDP7_DP_DPHY_CRC_RESULT … #define mmDP8_DP_DPHY_CRC_RESULT … #define mmDP_DPHY_CRC_MST_CNTL … #define mmDP0_DP_DPHY_CRC_MST_CNTL … #define mmDP1_DP_DPHY_CRC_MST_CNTL … #define mmDP2_DP_DPHY_CRC_MST_CNTL … #define mmDP3_DP_DPHY_CRC_MST_CNTL … #define mmDP4_DP_DPHY_CRC_MST_CNTL … #define mmDP5_DP_DPHY_CRC_MST_CNTL … #define mmDP6_DP_DPHY_CRC_MST_CNTL … #define mmDP7_DP_DPHY_CRC_MST_CNTL … #define mmDP8_DP_DPHY_CRC_MST_CNTL … #define mmDP_DPHY_CRC_MST_STATUS … #define mmDP0_DP_DPHY_CRC_MST_STATUS … #define mmDP1_DP_DPHY_CRC_MST_STATUS … #define mmDP2_DP_DPHY_CRC_MST_STATUS … #define mmDP3_DP_DPHY_CRC_MST_STATUS … #define mmDP4_DP_DPHY_CRC_MST_STATUS … #define mmDP5_DP_DPHY_CRC_MST_STATUS … #define mmDP6_DP_DPHY_CRC_MST_STATUS … #define mmDP7_DP_DPHY_CRC_MST_STATUS … #define mmDP8_DP_DPHY_CRC_MST_STATUS … #define mmDP_DPHY_FAST_TRAINING … #define mmDP0_DP_DPHY_FAST_TRAINING … #define mmDP1_DP_DPHY_FAST_TRAINING … #define mmDP2_DP_DPHY_FAST_TRAINING … #define mmDP3_DP_DPHY_FAST_TRAINING … #define mmDP4_DP_DPHY_FAST_TRAINING … #define mmDP5_DP_DPHY_FAST_TRAINING … #define mmDP6_DP_DPHY_FAST_TRAINING … #define mmDP7_DP_DPHY_FAST_TRAINING … #define mmDP8_DP_DPHY_FAST_TRAINING … #define mmDP_DPHY_FAST_TRAINING_STATUS … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP7_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP8_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP_MSA_V_TIMING_OVERRIDE1 … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP_MSA_V_TIMING_OVERRIDE2 … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP_SEC_CNTL … #define mmDP0_DP_SEC_CNTL … #define mmDP1_DP_SEC_CNTL … #define mmDP2_DP_SEC_CNTL … #define mmDP3_DP_SEC_CNTL … #define mmDP4_DP_SEC_CNTL … #define mmDP5_DP_SEC_CNTL … #define mmDP6_DP_SEC_CNTL … #define mmDP7_DP_SEC_CNTL … #define mmDP8_DP_SEC_CNTL … #define mmDP_SEC_CNTL1 … #define mmDP0_DP_SEC_CNTL1 … #define mmDP1_DP_SEC_CNTL1 … #define mmDP2_DP_SEC_CNTL1 … #define mmDP3_DP_SEC_CNTL1 … #define mmDP4_DP_SEC_CNTL1 … #define mmDP5_DP_SEC_CNTL1 … #define mmDP6_DP_SEC_CNTL1 … #define mmDP7_DP_SEC_CNTL1 … #define mmDP8_DP_SEC_CNTL1 … #define mmDP_SEC_FRAMING1 … #define mmDP0_DP_SEC_FRAMING1 … #define mmDP1_DP_SEC_FRAMING1 … #define mmDP2_DP_SEC_FRAMING1 … #define mmDP3_DP_SEC_FRAMING1 … #define mmDP4_DP_SEC_FRAMING1 … #define mmDP5_DP_SEC_FRAMING1 … #define mmDP6_DP_SEC_FRAMING1 … #define mmDP7_DP_SEC_FRAMING1 … #define mmDP8_DP_SEC_FRAMING1 … #define mmDP_SEC_FRAMING2 … #define mmDP0_DP_SEC_FRAMING2 … #define mmDP1_DP_SEC_FRAMING2 … #define mmDP2_DP_SEC_FRAMING2 … #define mmDP3_DP_SEC_FRAMING2 … #define mmDP4_DP_SEC_FRAMING2 … #define mmDP5_DP_SEC_FRAMING2 … #define mmDP6_DP_SEC_FRAMING2 … #define mmDP7_DP_SEC_FRAMING2 … #define mmDP8_DP_SEC_FRAMING2 … #define mmDP_SEC_FRAMING3 … #define mmDP0_DP_SEC_FRAMING3 … #define mmDP1_DP_SEC_FRAMING3 … #define mmDP2_DP_SEC_FRAMING3 … #define mmDP3_DP_SEC_FRAMING3 … #define mmDP4_DP_SEC_FRAMING3 … #define mmDP5_DP_SEC_FRAMING3 … #define mmDP6_DP_SEC_FRAMING3 … #define mmDP7_DP_SEC_FRAMING3 … #define mmDP8_DP_SEC_FRAMING3 … #define mmDP_SEC_FRAMING4 … #define mmDP0_DP_SEC_FRAMING4 … #define mmDP1_DP_SEC_FRAMING4 … #define mmDP2_DP_SEC_FRAMING4 … #define mmDP3_DP_SEC_FRAMING4 … #define mmDP4_DP_SEC_FRAMING4 … #define mmDP5_DP_SEC_FRAMING4 … #define mmDP6_DP_SEC_FRAMING4 … #define mmDP7_DP_SEC_FRAMING4 … #define mmDP8_DP_SEC_FRAMING4 … #define mmDP_SEC_AUD_N … #define mmDP0_DP_SEC_AUD_N … #define mmDP1_DP_SEC_AUD_N … #define mmDP2_DP_SEC_AUD_N … #define mmDP3_DP_SEC_AUD_N … #define mmDP4_DP_SEC_AUD_N … #define mmDP5_DP_SEC_AUD_N … #define mmDP6_DP_SEC_AUD_N … #define mmDP7_DP_SEC_AUD_N … #define mmDP8_DP_SEC_AUD_N … #define mmDP_SEC_AUD_N_READBACK … #define mmDP0_DP_SEC_AUD_N_READBACK … #define mmDP1_DP_SEC_AUD_N_READBACK … #define mmDP2_DP_SEC_AUD_N_READBACK … #define mmDP3_DP_SEC_AUD_N_READBACK … #define mmDP4_DP_SEC_AUD_N_READBACK … #define mmDP5_DP_SEC_AUD_N_READBACK … #define mmDP6_DP_SEC_AUD_N_READBACK … #define mmDP7_DP_SEC_AUD_N_READBACK … #define mmDP8_DP_SEC_AUD_N_READBACK … #define mmDP_SEC_AUD_M … #define mmDP0_DP_SEC_AUD_M … #define mmDP1_DP_SEC_AUD_M … #define mmDP2_DP_SEC_AUD_M … #define mmDP3_DP_SEC_AUD_M … #define mmDP4_DP_SEC_AUD_M … #define mmDP5_DP_SEC_AUD_M … #define mmDP6_DP_SEC_AUD_M … #define mmDP7_DP_SEC_AUD_M … #define mmDP8_DP_SEC_AUD_M … #define mmDP_SEC_AUD_M_READBACK … #define mmDP0_DP_SEC_AUD_M_READBACK … #define mmDP1_DP_SEC_AUD_M_READBACK … #define mmDP2_DP_SEC_AUD_M_READBACK … #define mmDP3_DP_SEC_AUD_M_READBACK … #define mmDP4_DP_SEC_AUD_M_READBACK … #define mmDP5_DP_SEC_AUD_M_READBACK … #define mmDP6_DP_SEC_AUD_M_READBACK … #define mmDP7_DP_SEC_AUD_M_READBACK … #define mmDP8_DP_SEC_AUD_M_READBACK … #define mmDP_SEC_TIMESTAMP … #define mmDP0_DP_SEC_TIMESTAMP … #define mmDP1_DP_SEC_TIMESTAMP … #define mmDP2_DP_SEC_TIMESTAMP … #define mmDP3_DP_SEC_TIMESTAMP … #define mmDP4_DP_SEC_TIMESTAMP … #define mmDP5_DP_SEC_TIMESTAMP … #define mmDP6_DP_SEC_TIMESTAMP … #define mmDP7_DP_SEC_TIMESTAMP … #define mmDP8_DP_SEC_TIMESTAMP … #define mmDP_SEC_PACKET_CNTL … #define mmDP0_DP_SEC_PACKET_CNTL … #define mmDP1_DP_SEC_PACKET_CNTL … #define mmDP2_DP_SEC_PACKET_CNTL … #define mmDP3_DP_SEC_PACKET_CNTL … #define mmDP4_DP_SEC_PACKET_CNTL … #define mmDP5_DP_SEC_PACKET_CNTL … #define mmDP6_DP_SEC_PACKET_CNTL … #define mmDP7_DP_SEC_PACKET_CNTL … #define mmDP8_DP_SEC_PACKET_CNTL … #define mmDP_MSE_RATE_CNTL … #define mmDP0_DP_MSE_RATE_CNTL … #define mmDP1_DP_MSE_RATE_CNTL … #define mmDP2_DP_MSE_RATE_CNTL … #define mmDP3_DP_MSE_RATE_CNTL … #define mmDP4_DP_MSE_RATE_CNTL … #define mmDP5_DP_MSE_RATE_CNTL … #define mmDP6_DP_MSE_RATE_CNTL … #define mmDP7_DP_MSE_RATE_CNTL … #define mmDP8_DP_MSE_RATE_CNTL … #define mmDP_MSE_RATE_UPDATE … #define mmDP0_DP_MSE_RATE_UPDATE … #define mmDP1_DP_MSE_RATE_UPDATE … #define mmDP2_DP_MSE_RATE_UPDATE … #define mmDP3_DP_MSE_RATE_UPDATE … #define mmDP4_DP_MSE_RATE_UPDATE … #define mmDP5_DP_MSE_RATE_UPDATE … #define mmDP6_DP_MSE_RATE_UPDATE … #define mmDP7_DP_MSE_RATE_UPDATE … #define mmDP8_DP_MSE_RATE_UPDATE … #define mmDP_MSE_SAT0 … #define mmDP0_DP_MSE_SAT0 … #define mmDP1_DP_MSE_SAT0 … #define mmDP2_DP_MSE_SAT0 … #define mmDP3_DP_MSE_SAT0 … #define mmDP4_DP_MSE_SAT0 … #define mmDP5_DP_MSE_SAT0 … #define mmDP6_DP_MSE_SAT0 … #define mmDP7_DP_MSE_SAT0 … #define mmDP8_DP_MSE_SAT0 … #define mmDP_MSE_SAT1 … #define mmDP0_DP_MSE_SAT1 … #define mmDP1_DP_MSE_SAT1 … #define mmDP2_DP_MSE_SAT1 … #define mmDP3_DP_MSE_SAT1 … #define mmDP4_DP_MSE_SAT1 … #define mmDP5_DP_MSE_SAT1 … #define mmDP6_DP_MSE_SAT1 … #define mmDP7_DP_MSE_SAT1 … #define mmDP8_DP_MSE_SAT1 … #define mmDP_MSE_SAT2 … #define mmDP0_DP_MSE_SAT2 … #define mmDP1_DP_MSE_SAT2 … #define mmDP2_DP_MSE_SAT2 … #define mmDP3_DP_MSE_SAT2 … #define mmDP4_DP_MSE_SAT2 … #define mmDP5_DP_MSE_SAT2 … #define mmDP6_DP_MSE_SAT2 … #define mmDP7_DP_MSE_SAT2 … #define mmDP8_DP_MSE_SAT2 … #define mmDP_MSE_SAT_UPDATE … #define mmDP0_DP_MSE_SAT_UPDATE … #define mmDP1_DP_MSE_SAT_UPDATE … #define mmDP2_DP_MSE_SAT_UPDATE … #define mmDP3_DP_MSE_SAT_UPDATE … #define mmDP4_DP_MSE_SAT_UPDATE … #define mmDP5_DP_MSE_SAT_UPDATE … #define mmDP6_DP_MSE_SAT_UPDATE … #define mmDP7_DP_MSE_SAT_UPDATE … #define mmDP8_DP_MSE_SAT_UPDATE … #define mmDP_MSE_LINK_TIMING … #define mmDP0_DP_MSE_LINK_TIMING … #define mmDP1_DP_MSE_LINK_TIMING … #define mmDP2_DP_MSE_LINK_TIMING … #define mmDP3_DP_MSE_LINK_TIMING … #define mmDP4_DP_MSE_LINK_TIMING … #define mmDP5_DP_MSE_LINK_TIMING … #define mmDP6_DP_MSE_LINK_TIMING … #define mmDP7_DP_MSE_LINK_TIMING … #define mmDP8_DP_MSE_LINK_TIMING … #define mmDP_MSE_MISC_CNTL … #define mmDP0_DP_MSE_MISC_CNTL … #define mmDP1_DP_MSE_MISC_CNTL … #define mmDP2_DP_MSE_MISC_CNTL … #define mmDP3_DP_MSE_MISC_CNTL … #define mmDP4_DP_MSE_MISC_CNTL … #define mmDP5_DP_MSE_MISC_CNTL … #define mmDP6_DP_MSE_MISC_CNTL … #define mmDP7_DP_MSE_MISC_CNTL … #define mmDP8_DP_MSE_MISC_CNTL … #define mmDP_TEST_DEBUG_INDEX … #define mmDP0_DP_TEST_DEBUG_INDEX … #define mmDP1_DP_TEST_DEBUG_INDEX … #define mmDP2_DP_TEST_DEBUG_INDEX … #define mmDP3_DP_TEST_DEBUG_INDEX … #define mmDP4_DP_TEST_DEBUG_INDEX … #define mmDP5_DP_TEST_DEBUG_INDEX … #define mmDP6_DP_TEST_DEBUG_INDEX … #define mmDP7_DP_TEST_DEBUG_INDEX … #define mmDP8_DP_TEST_DEBUG_INDEX … #define mmDP_TEST_DEBUG_DATA … #define mmDP0_DP_TEST_DEBUG_DATA … #define mmDP1_DP_TEST_DEBUG_DATA … #define mmDP2_DP_TEST_DEBUG_DATA … #define mmDP3_DP_TEST_DEBUG_DATA … #define mmDP4_DP_TEST_DEBUG_DATA … #define mmDP5_DP_TEST_DEBUG_DATA … #define mmDP6_DP_TEST_DEBUG_DATA … #define mmDP7_DP_TEST_DEBUG_DATA … #define mmDP8_DP_TEST_DEBUG_DATA … #define mmDP_FE_TEST_DEBUG_INDEX … #define mmDP0_DP_FE_TEST_DEBUG_INDEX … #define mmDP1_DP_FE_TEST_DEBUG_INDEX … #define mmDP2_DP_FE_TEST_DEBUG_INDEX … #define mmDP3_DP_FE_TEST_DEBUG_INDEX … #define mmDP4_DP_FE_TEST_DEBUG_INDEX … #define mmDP5_DP_FE_TEST_DEBUG_INDEX … #define mmDP6_DP_FE_TEST_DEBUG_INDEX … #define mmDP7_DP_FE_TEST_DEBUG_INDEX … #define mmDP8_DP_FE_TEST_DEBUG_INDEX … #define mmDP_FE_TEST_DEBUG_DATA … #define mmDP0_DP_FE_TEST_DEBUG_DATA … #define mmDP1_DP_FE_TEST_DEBUG_DATA … #define mmDP2_DP_FE_TEST_DEBUG_DATA … #define mmDP3_DP_FE_TEST_DEBUG_DATA … #define mmDP4_DP_FE_TEST_DEBUG_DATA … #define mmDP5_DP_FE_TEST_DEBUG_DATA … #define mmDP6_DP_FE_TEST_DEBUG_DATA … #define mmDP7_DP_FE_TEST_DEBUG_DATA … #define mmDP8_DP_FE_TEST_DEBUG_DATA … #define mmAUX_CONTROL … #define mmDP_AUX0_AUX_CONTROL … #define mmDP_AUX1_AUX_CONTROL … #define mmDP_AUX2_AUX_CONTROL … #define mmDP_AUX3_AUX_CONTROL … #define mmDP_AUX4_AUX_CONTROL … #define mmDP_AUX5_AUX_CONTROL … #define mmAUX_SW_CONTROL … #define mmDP_AUX0_AUX_SW_CONTROL … #define mmDP_AUX1_AUX_SW_CONTROL … #define mmDP_AUX2_AUX_SW_CONTROL … #define mmDP_AUX3_AUX_SW_CONTROL … #define mmDP_AUX4_AUX_SW_CONTROL … #define mmDP_AUX5_AUX_SW_CONTROL … #define mmAUX_ARB_CONTROL … #define mmDP_AUX0_AUX_ARB_CONTROL … #define mmDP_AUX1_AUX_ARB_CONTROL … #define mmDP_AUX2_AUX_ARB_CONTROL … #define mmDP_AUX3_AUX_ARB_CONTROL … #define mmDP_AUX4_AUX_ARB_CONTROL … #define mmDP_AUX5_AUX_ARB_CONTROL … #define mmAUX_INTERRUPT_CONTROL … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL … #define mmDP_AUX2_AUX_INTERRUPT_CONTROL … #define mmDP_AUX3_AUX_INTERRUPT_CONTROL … #define mmDP_AUX4_AUX_INTERRUPT_CONTROL … #define mmDP_AUX5_AUX_INTERRUPT_CONTROL … #define mmAUX_SW_STATUS … #define mmDP_AUX0_AUX_SW_STATUS … #define mmDP_AUX1_AUX_SW_STATUS … #define mmDP_AUX2_AUX_SW_STATUS … #define mmDP_AUX3_AUX_SW_STATUS … #define mmDP_AUX4_AUX_SW_STATUS … #define mmDP_AUX5_AUX_SW_STATUS … #define mmAUX_LS_STATUS … #define mmDP_AUX0_AUX_LS_STATUS … #define mmDP_AUX1_AUX_LS_STATUS … #define mmDP_AUX2_AUX_LS_STATUS … #define mmDP_AUX3_AUX_LS_STATUS … #define mmDP_AUX4_AUX_LS_STATUS … #define mmDP_AUX5_AUX_LS_STATUS … #define mmAUX_SW_DATA … #define mmDP_AUX0_AUX_SW_DATA … #define mmDP_AUX1_AUX_SW_DATA … #define mmDP_AUX2_AUX_SW_DATA … #define mmDP_AUX3_AUX_SW_DATA … #define mmDP_AUX4_AUX_SW_DATA … #define mmDP_AUX5_AUX_SW_DATA … #define mmAUX_LS_DATA … #define mmDP_AUX0_AUX_LS_DATA … #define mmDP_AUX1_AUX_LS_DATA … #define mmDP_AUX2_AUX_LS_DATA … #define mmDP_AUX3_AUX_LS_DATA … #define mmDP_AUX4_AUX_LS_DATA … #define mmDP_AUX5_AUX_LS_DATA … #define mmAUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL … #define mmAUX_DPHY_TX_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_CONTROL … #define mmAUX_DPHY_RX_CONTROL0 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 … #define mmAUX_DPHY_RX_CONTROL1 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 … #define mmAUX_DPHY_TX_STATUS … #define mmDP_AUX0_AUX_DPHY_TX_STATUS … #define mmDP_AUX1_AUX_DPHY_TX_STATUS … #define mmDP_AUX2_AUX_DPHY_TX_STATUS … #define mmDP_AUX3_AUX_DPHY_TX_STATUS … #define mmDP_AUX4_AUX_DPHY_TX_STATUS … #define mmDP_AUX5_AUX_DPHY_TX_STATUS … #define mmAUX_DPHY_RX_STATUS … #define mmDP_AUX0_AUX_DPHY_RX_STATUS … #define mmDP_AUX1_AUX_DPHY_RX_STATUS … #define mmDP_AUX2_AUX_DPHY_RX_STATUS … #define mmDP_AUX3_AUX_DPHY_RX_STATUS … #define mmDP_AUX4_AUX_DPHY_RX_STATUS … #define mmDP_AUX5_AUX_DPHY_RX_STATUS … #define mmAUX_GTC_SYNC_CONTROL … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL … #define mmAUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL … #define mmAUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmAUX_GTC_SYNC_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_STATUS … #define mmAUX_GTC_SYNC_DATA … #define mmDP_AUX0_AUX_GTC_SYNC_DATA … #define mmDP_AUX1_AUX_GTC_SYNC_DATA … #define mmDP_AUX2_AUX_GTC_SYNC_DATA … #define mmDP_AUX3_AUX_GTC_SYNC_DATA … #define mmDP_AUX4_AUX_GTC_SYNC_DATA … #define mmDP_AUX5_AUX_GTC_SYNC_DATA … #define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE … #define mmAUX_TEST_DEBUG_INDEX … #define mmDP_AUX0_AUX_TEST_DEBUG_INDEX … #define mmDP_AUX1_AUX_TEST_DEBUG_INDEX … #define mmDP_AUX2_AUX_TEST_DEBUG_INDEX … #define mmDP_AUX3_AUX_TEST_DEBUG_INDEX … #define mmDP_AUX4_AUX_TEST_DEBUG_INDEX … #define mmDP_AUX5_AUX_TEST_DEBUG_INDEX … #define mmAUX_TEST_DEBUG_DATA … #define mmDP_AUX0_AUX_TEST_DEBUG_DATA … #define mmDP_AUX1_AUX_TEST_DEBUG_DATA … #define mmDP_AUX2_AUX_TEST_DEBUG_DATA … #define mmDP_AUX3_AUX_TEST_DEBUG_DATA … #define mmDP_AUX4_AUX_TEST_DEBUG_DATA … #define mmDP_AUX5_AUX_TEST_DEBUG_DATA … #define ixDP_AUX_DEBUG_A … #define ixDP_AUX_DEBUG_B … #define ixDP_AUX_DEBUG_C … #define ixDP_AUX_DEBUG_D … #define ixDP_AUX_DEBUG_E … #define ixDP_AUX_DEBUG_F … #define ixDP_AUX_DEBUG_G … #define ixDP_AUX_DEBUG_H … #define ixDP_AUX_DEBUG_I … #define ixDP_AUX_DEBUG_J … #define ixDP_AUX_DEBUG_K … #define ixDP_AUX_DEBUG_L … #define ixDP_AUX_DEBUG_M … #define ixDP_AUX_DEBUG_N … #define ixDP_AUX_DEBUG_O … #define ixDP_AUX_DEBUG_P … #define ixDP_AUX_DEBUG_Q … #define mmDVO_ENABLE … #define mmDVO_SOURCE_SELECT … #define mmDVO_OUTPUT … #define mmDVO_CONTROL … #define mmDVO_CRC_EN … #define mmDVO_CRC2_SIG_MASK … #define mmDVO_CRC2_SIG_RESULT … #define mmDVO_FIFO_ERROR_STATUS … #define mmDVO_TEST_DEBUG_INDEX … #define mmDVO_TEST_DEBUG_DATA … #define mmFBC_CNTL … #define mmFBC_IDLE_MASK … #define mmFBC_IDLE_FORCE_CLEAR_MASK … #define mmFBC_START_STOP_DELAY … #define mmFBC_COMP_CNTL … #define mmFBC_COMP_MODE … #define mmFBC_DEBUG0 … #define mmFBC_DEBUG1 … #define mmFBC_DEBUG2 … #define mmFBC_IND_LUT0 … #define mmFBC_IND_LUT1 … #define mmFBC_IND_LUT2 … #define mmFBC_IND_LUT3 … #define mmFBC_IND_LUT4 … #define mmFBC_IND_LUT5 … #define mmFBC_IND_LUT6 … #define mmFBC_IND_LUT7 … #define mmFBC_IND_LUT8 … #define mmFBC_IND_LUT9 … #define mmFBC_IND_LUT10 … #define mmFBC_IND_LUT11 … #define mmFBC_IND_LUT12 … #define mmFBC_IND_LUT13 … #define mmFBC_IND_LUT14 … #define mmFBC_IND_LUT15 … #define mmFBC_CSM_REGION_OFFSET_01 … #define mmFBC_CSM_REGION_OFFSET_23 … #define mmFBC_CLIENT_REGION_MASK … #define mmFBC_DEBUG_COMP … #define mmFBC_DEBUG_CSR … #define mmFBC_DEBUG_CSR_RDATA … #define mmFBC_DEBUG_CSR_WDATA … #define mmFBC_DEBUG_CSR_RDATA_HI … #define mmFBC_DEBUG_CSR_WDATA_HI … #define mmFBC_MISC … #define mmFBC_STATUS … #define mmFBC_TEST_DEBUG_INDEX … #define mmFBC_TEST_DEBUG_DATA … #define mmFMT_CLAMP_COMPONENT_R … #define mmFMT0_FMT_CLAMP_COMPONENT_R … #define mmFMT1_FMT_CLAMP_COMPONENT_R … #define mmFMT2_FMT_CLAMP_COMPONENT_R … #define mmFMT3_FMT_CLAMP_COMPONENT_R … #define mmFMT4_FMT_CLAMP_COMPONENT_R … #define mmFMT5_FMT_CLAMP_COMPONENT_R … #define mmFMT_CLAMP_COMPONENT_G … #define mmFMT0_FMT_CLAMP_COMPONENT_G … #define mmFMT1_FMT_CLAMP_COMPONENT_G … #define mmFMT2_FMT_CLAMP_COMPONENT_G … #define mmFMT3_FMT_CLAMP_COMPONENT_G … #define mmFMT4_FMT_CLAMP_COMPONENT_G … #define mmFMT5_FMT_CLAMP_COMPONENT_G … #define mmFMT_CLAMP_COMPONENT_B … #define mmFMT0_FMT_CLAMP_COMPONENT_B … #define mmFMT1_FMT_CLAMP_COMPONENT_B … #define mmFMT2_FMT_CLAMP_COMPONENT_B … #define mmFMT3_FMT_CLAMP_COMPONENT_B … #define mmFMT4_FMT_CLAMP_COMPONENT_B … #define mmFMT5_FMT_CLAMP_COMPONENT_B … #define mmFMT_DYNAMIC_EXP_CNTL … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL … #define mmFMT2_FMT_DYNAMIC_EXP_CNTL … #define mmFMT3_FMT_DYNAMIC_EXP_CNTL … #define mmFMT4_FMT_DYNAMIC_EXP_CNTL … #define mmFMT5_FMT_DYNAMIC_EXP_CNTL … #define mmFMT_CONTROL … #define mmFMT0_FMT_CONTROL … #define mmFMT1_FMT_CONTROL … #define mmFMT2_FMT_CONTROL … #define mmFMT3_FMT_CONTROL … #define mmFMT4_FMT_CONTROL … #define mmFMT5_FMT_CONTROL … #define mmFMT_BIT_DEPTH_CONTROL … #define mmFMT0_FMT_BIT_DEPTH_CONTROL … #define mmFMT1_FMT_BIT_DEPTH_CONTROL … #define mmFMT2_FMT_BIT_DEPTH_CONTROL … #define mmFMT3_FMT_BIT_DEPTH_CONTROL … #define mmFMT4_FMT_BIT_DEPTH_CONTROL … #define mmFMT5_FMT_BIT_DEPTH_CONTROL … #define mmFMT_DITHER_RAND_R_SEED … #define mmFMT0_FMT_DITHER_RAND_R_SEED … #define mmFMT1_FMT_DITHER_RAND_R_SEED … #define mmFMT2_FMT_DITHER_RAND_R_SEED … #define mmFMT3_FMT_DITHER_RAND_R_SEED … #define mmFMT4_FMT_DITHER_RAND_R_SEED … #define mmFMT5_FMT_DITHER_RAND_R_SEED … #define mmFMT_DITHER_RAND_G_SEED … #define mmFMT0_FMT_DITHER_RAND_G_SEED … #define mmFMT1_FMT_DITHER_RAND_G_SEED … #define mmFMT2_FMT_DITHER_RAND_G_SEED … #define mmFMT3_FMT_DITHER_RAND_G_SEED … #define mmFMT4_FMT_DITHER_RAND_G_SEED … #define mmFMT5_FMT_DITHER_RAND_G_SEED … #define mmFMT_DITHER_RAND_B_SEED … #define mmFMT0_FMT_DITHER_RAND_B_SEED … #define mmFMT1_FMT_DITHER_RAND_B_SEED … #define mmFMT2_FMT_DITHER_RAND_B_SEED … #define mmFMT3_FMT_DITHER_RAND_B_SEED … #define mmFMT4_FMT_DITHER_RAND_B_SEED … #define mmFMT5_FMT_DITHER_RAND_B_SEED … #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL … #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX … #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX … #define mmFMT_CLAMP_CNTL … #define mmFMT0_FMT_CLAMP_CNTL … #define mmFMT1_FMT_CLAMP_CNTL … #define mmFMT2_FMT_CLAMP_CNTL … #define mmFMT3_FMT_CLAMP_CNTL … #define mmFMT4_FMT_CLAMP_CNTL … #define mmFMT5_FMT_CLAMP_CNTL … #define mmFMT_CRC_CNTL … #define mmFMT0_FMT_CRC_CNTL … #define mmFMT1_FMT_CRC_CNTL … #define mmFMT2_FMT_CRC_CNTL … #define mmFMT3_FMT_CRC_CNTL … #define mmFMT4_FMT_CRC_CNTL … #define mmFMT5_FMT_CRC_CNTL … #define mmFMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT_CRC_SIG_RED_GREEN … #define mmFMT0_FMT_CRC_SIG_RED_GREEN … #define mmFMT1_FMT_CRC_SIG_RED_GREEN … #define mmFMT2_FMT_CRC_SIG_RED_GREEN … #define mmFMT3_FMT_CRC_SIG_RED_GREEN … #define mmFMT4_FMT_CRC_SIG_RED_GREEN … #define mmFMT5_FMT_CRC_SIG_RED_GREEN … #define mmFMT_CRC_SIG_BLUE_CONTROL … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT_DEBUG_CNTL … #define mmFMT0_FMT_DEBUG_CNTL … #define mmFMT1_FMT_DEBUG_CNTL … #define mmFMT2_FMT_DEBUG_CNTL … #define mmFMT3_FMT_DEBUG_CNTL … #define mmFMT4_FMT_DEBUG_CNTL … #define mmFMT5_FMT_DEBUG_CNTL … #define mmFMT_TEST_DEBUG_INDEX … #define mmFMT0_FMT_TEST_DEBUG_INDEX … #define mmFMT1_FMT_TEST_DEBUG_INDEX … #define mmFMT2_FMT_TEST_DEBUG_INDEX … #define mmFMT3_FMT_TEST_DEBUG_INDEX … #define mmFMT4_FMT_TEST_DEBUG_INDEX … #define mmFMT5_FMT_TEST_DEBUG_INDEX … #define mmFMT_TEST_DEBUG_DATA … #define mmFMT0_FMT_TEST_DEBUG_DATA … #define mmFMT1_FMT_TEST_DEBUG_DATA … #define mmFMT2_FMT_TEST_DEBUG_DATA … #define mmFMT3_FMT_TEST_DEBUG_DATA … #define mmFMT4_FMT_TEST_DEBUG_DATA … #define mmFMT5_FMT_TEST_DEBUG_DATA … #define ixFMT_DEBUG0 … #define ixFMT_DEBUG1 … #define ixFMT_DEBUG2 … #define ixFMT_DEBUG_ID … #define mmLB_DATA_FORMAT … #define mmLB0_LB_DATA_FORMAT … #define mmLB1_LB_DATA_FORMAT … #define mmLB2_LB_DATA_FORMAT … #define mmLB3_LB_DATA_FORMAT … #define mmLB4_LB_DATA_FORMAT … #define mmLB5_LB_DATA_FORMAT … #define mmLB_MEMORY_CTRL … #define mmLB0_LB_MEMORY_CTRL … #define mmLB1_LB_MEMORY_CTRL … #define mmLB2_LB_MEMORY_CTRL … #define mmLB3_LB_MEMORY_CTRL … #define mmLB4_LB_MEMORY_CTRL … #define mmLB5_LB_MEMORY_CTRL … #define mmLB_MEMORY_SIZE_STATUS … #define mmLB0_LB_MEMORY_SIZE_STATUS … #define mmLB1_LB_MEMORY_SIZE_STATUS … #define mmLB2_LB_MEMORY_SIZE_STATUS … #define mmLB3_LB_MEMORY_SIZE_STATUS … #define mmLB4_LB_MEMORY_SIZE_STATUS … #define mmLB5_LB_MEMORY_SIZE_STATUS … #define mmLB_DESKTOP_HEIGHT … #define mmLB0_LB_DESKTOP_HEIGHT … #define mmLB1_LB_DESKTOP_HEIGHT … #define mmLB2_LB_DESKTOP_HEIGHT … #define mmLB3_LB_DESKTOP_HEIGHT … #define mmLB4_LB_DESKTOP_HEIGHT … #define mmLB5_LB_DESKTOP_HEIGHT … #define mmLB_VLINE_START_END … #define mmLB0_LB_VLINE_START_END … #define mmLB1_LB_VLINE_START_END … #define mmLB2_LB_VLINE_START_END … #define mmLB3_LB_VLINE_START_END … #define mmLB4_LB_VLINE_START_END … #define mmLB5_LB_VLINE_START_END … #define mmLB_VLINE2_START_END … #define mmLB0_LB_VLINE2_START_END … #define mmLB1_LB_VLINE2_START_END … #define mmLB2_LB_VLINE2_START_END … #define mmLB3_LB_VLINE2_START_END … #define mmLB4_LB_VLINE2_START_END … #define mmLB5_LB_VLINE2_START_END … #define mmLB_V_COUNTER … #define mmLB0_LB_V_COUNTER … #define mmLB1_LB_V_COUNTER … #define mmLB2_LB_V_COUNTER … #define mmLB3_LB_V_COUNTER … #define mmLB4_LB_V_COUNTER … #define mmLB5_LB_V_COUNTER … #define mmLB_SNAPSHOT_V_COUNTER … #define mmLB0_LB_SNAPSHOT_V_COUNTER … #define mmLB1_LB_SNAPSHOT_V_COUNTER … #define mmLB2_LB_SNAPSHOT_V_COUNTER … #define mmLB3_LB_SNAPSHOT_V_COUNTER … #define mmLB4_LB_SNAPSHOT_V_COUNTER … #define mmLB5_LB_SNAPSHOT_V_COUNTER … #define mmLB_INTERRUPT_MASK … #define mmLB0_LB_INTERRUPT_MASK … #define mmLB1_LB_INTERRUPT_MASK … #define mmLB2_LB_INTERRUPT_MASK … #define mmLB3_LB_INTERRUPT_MASK … #define mmLB4_LB_INTERRUPT_MASK … #define mmLB5_LB_INTERRUPT_MASK … #define mmLB_VLINE_STATUS … #define mmLB0_LB_VLINE_STATUS … #define mmLB1_LB_VLINE_STATUS … #define mmLB2_LB_VLINE_STATUS … #define mmLB3_LB_VLINE_STATUS … #define mmLB4_LB_VLINE_STATUS … #define mmLB5_LB_VLINE_STATUS … #define mmLB_VLINE2_STATUS … #define mmLB0_LB_VLINE2_STATUS … #define mmLB1_LB_VLINE2_STATUS … #define mmLB2_LB_VLINE2_STATUS … #define mmLB3_LB_VLINE2_STATUS … #define mmLB4_LB_VLINE2_STATUS … #define mmLB5_LB_VLINE2_STATUS … #define mmLB_VBLANK_STATUS … #define mmLB0_LB_VBLANK_STATUS … #define mmLB1_LB_VBLANK_STATUS … #define mmLB2_LB_VBLANK_STATUS … #define mmLB3_LB_VBLANK_STATUS … #define mmLB4_LB_VBLANK_STATUS … #define mmLB5_LB_VBLANK_STATUS … #define mmLB_SYNC_RESET_SEL … #define mmLB0_LB_SYNC_RESET_SEL … #define mmLB1_LB_SYNC_RESET_SEL … #define mmLB2_LB_SYNC_RESET_SEL … #define mmLB3_LB_SYNC_RESET_SEL … #define mmLB4_LB_SYNC_RESET_SEL … #define mmLB5_LB_SYNC_RESET_SEL … #define mmLB_BLACK_KEYER_R_CR … #define mmLB0_LB_BLACK_KEYER_R_CR … #define mmLB1_LB_BLACK_KEYER_R_CR … #define mmLB2_LB_BLACK_KEYER_R_CR … #define mmLB3_LB_BLACK_KEYER_R_CR … #define mmLB4_LB_BLACK_KEYER_R_CR … #define mmLB5_LB_BLACK_KEYER_R_CR … #define mmLB_BLACK_KEYER_G_Y … #define mmLB0_LB_BLACK_KEYER_G_Y … #define mmLB1_LB_BLACK_KEYER_G_Y … #define mmLB2_LB_BLACK_KEYER_G_Y … #define mmLB3_LB_BLACK_KEYER_G_Y … #define mmLB4_LB_BLACK_KEYER_G_Y … #define mmLB5_LB_BLACK_KEYER_G_Y … #define mmLB_BLACK_KEYER_B_CB … #define mmLB0_LB_BLACK_KEYER_B_CB … #define mmLB1_LB_BLACK_KEYER_B_CB … #define mmLB2_LB_BLACK_KEYER_B_CB … #define mmLB3_LB_BLACK_KEYER_B_CB … #define mmLB4_LB_BLACK_KEYER_B_CB … #define mmLB5_LB_BLACK_KEYER_B_CB … #define mmLB_KEYER_COLOR_CTRL … #define mmLB0_LB_KEYER_COLOR_CTRL … #define mmLB1_LB_KEYER_COLOR_CTRL … #define mmLB2_LB_KEYER_COLOR_CTRL … #define mmLB3_LB_KEYER_COLOR_CTRL … #define mmLB4_LB_KEYER_COLOR_CTRL … #define mmLB5_LB_KEYER_COLOR_CTRL … #define mmLB_KEYER_COLOR_R_CR … #define mmLB0_LB_KEYER_COLOR_R_CR … #define mmLB1_LB_KEYER_COLOR_R_CR … #define mmLB2_LB_KEYER_COLOR_R_CR … #define mmLB3_LB_KEYER_COLOR_R_CR … #define mmLB4_LB_KEYER_COLOR_R_CR … #define mmLB5_LB_KEYER_COLOR_R_CR … #define mmLB_KEYER_COLOR_G_Y … #define mmLB0_LB_KEYER_COLOR_G_Y … #define mmLB1_LB_KEYER_COLOR_G_Y … #define mmLB2_LB_KEYER_COLOR_G_Y … #define mmLB3_LB_KEYER_COLOR_G_Y … #define mmLB4_LB_KEYER_COLOR_G_Y … #define mmLB5_LB_KEYER_COLOR_G_Y … #define mmLB_KEYER_COLOR_B_CB … #define mmLB0_LB_KEYER_COLOR_B_CB … #define mmLB1_LB_KEYER_COLOR_B_CB … #define mmLB2_LB_KEYER_COLOR_B_CB … #define mmLB3_LB_KEYER_COLOR_B_CB … #define mmLB4_LB_KEYER_COLOR_B_CB … #define mmLB5_LB_KEYER_COLOR_B_CB … #define mmLB_KEYER_COLOR_REP_R_CR … #define mmLB0_LB_KEYER_COLOR_REP_R_CR … #define mmLB1_LB_KEYER_COLOR_REP_R_CR … #define mmLB2_LB_KEYER_COLOR_REP_R_CR … #define mmLB3_LB_KEYER_COLOR_REP_R_CR … #define mmLB4_LB_KEYER_COLOR_REP_R_CR … #define mmLB5_LB_KEYER_COLOR_REP_R_CR … #define mmLB_KEYER_COLOR_REP_G_Y … #define mmLB0_LB_KEYER_COLOR_REP_G_Y … #define mmLB1_LB_KEYER_COLOR_REP_G_Y … #define mmLB2_LB_KEYER_COLOR_REP_G_Y … #define mmLB3_LB_KEYER_COLOR_REP_G_Y … #define mmLB4_LB_KEYER_COLOR_REP_G_Y … #define mmLB5_LB_KEYER_COLOR_REP_G_Y … #define mmLB_KEYER_COLOR_REP_B_CB … #define mmLB0_LB_KEYER_COLOR_REP_B_CB … #define mmLB1_LB_KEYER_COLOR_REP_B_CB … #define mmLB2_LB_KEYER_COLOR_REP_B_CB … #define mmLB3_LB_KEYER_COLOR_REP_B_CB … #define mmLB4_LB_KEYER_COLOR_REP_B_CB … #define mmLB5_LB_KEYER_COLOR_REP_B_CB … #define mmLB_BUFFER_LEVEL_STATUS … #define mmLB0_LB_BUFFER_LEVEL_STATUS … #define mmLB1_LB_BUFFER_LEVEL_STATUS … #define mmLB2_LB_BUFFER_LEVEL_STATUS … #define mmLB3_LB_BUFFER_LEVEL_STATUS … #define mmLB4_LB_BUFFER_LEVEL_STATUS … #define mmLB5_LB_BUFFER_LEVEL_STATUS … #define mmLB_BUFFER_URGENCY_CTRL … #define mmLB0_LB_BUFFER_URGENCY_CTRL … #define mmLB1_LB_BUFFER_URGENCY_CTRL … #define mmLB2_LB_BUFFER_URGENCY_CTRL … #define mmLB3_LB_BUFFER_URGENCY_CTRL … #define mmLB4_LB_BUFFER_URGENCY_CTRL … #define mmLB5_LB_BUFFER_URGENCY_CTRL … #define mmLB_BUFFER_URGENCY_STATUS … #define mmLB0_LB_BUFFER_URGENCY_STATUS … #define mmLB1_LB_BUFFER_URGENCY_STATUS … #define mmLB2_LB_BUFFER_URGENCY_STATUS … #define mmLB3_LB_BUFFER_URGENCY_STATUS … #define mmLB4_LB_BUFFER_URGENCY_STATUS … #define mmLB5_LB_BUFFER_URGENCY_STATUS … #define mmLB_BUFFER_STATUS … #define mmLB0_LB_BUFFER_STATUS … #define mmLB1_LB_BUFFER_STATUS … #define mmLB2_LB_BUFFER_STATUS … #define mmLB3_LB_BUFFER_STATUS … #define mmLB4_LB_BUFFER_STATUS … #define mmLB5_LB_BUFFER_STATUS … #define mmLB_NO_OUTSTANDING_REQ_STATUS … #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS … #define mmMVP_AFR_FLIP_MODE … #define mmLB0_MVP_AFR_FLIP_MODE … #define mmLB1_MVP_AFR_FLIP_MODE … #define mmLB2_MVP_AFR_FLIP_MODE … #define mmLB3_MVP_AFR_FLIP_MODE … #define mmLB4_MVP_AFR_FLIP_MODE … #define mmLB5_MVP_AFR_FLIP_MODE … #define mmMVP_AFR_FLIP_FIFO_CNTL … #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL … #define mmMVP_FLIP_LINE_NUM_INSERT … #define mmLB0_MVP_FLIP_LINE_NUM_INSERT … #define mmLB1_MVP_FLIP_LINE_NUM_INSERT … #define mmLB2_MVP_FLIP_LINE_NUM_INSERT … #define mmLB3_MVP_FLIP_LINE_NUM_INSERT … #define mmLB4_MVP_FLIP_LINE_NUM_INSERT … #define mmLB5_MVP_FLIP_LINE_NUM_INSERT … #define mmDC_MVP_LB_CONTROL … #define mmLB0_DC_MVP_LB_CONTROL … #define mmLB1_DC_MVP_LB_CONTROL … #define mmLB2_DC_MVP_LB_CONTROL … #define mmLB3_DC_MVP_LB_CONTROL … #define mmLB4_DC_MVP_LB_CONTROL … #define mmLB5_DC_MVP_LB_CONTROL … #define mmLB_DEBUG … #define mmLB0_LB_DEBUG … #define mmLB1_LB_DEBUG … #define mmLB2_LB_DEBUG … #define mmLB3_LB_DEBUG … #define mmLB4_LB_DEBUG … #define mmLB5_LB_DEBUG … #define mmLB_DEBUG2 … #define mmLB0_LB_DEBUG2 … #define mmLB1_LB_DEBUG2 … #define mmLB2_LB_DEBUG2 … #define mmLB3_LB_DEBUG2 … #define mmLB4_LB_DEBUG2 … #define mmLB5_LB_DEBUG2 … #define mmLB_DEBUG3 … #define mmLB0_LB_DEBUG3 … #define mmLB1_LB_DEBUG3 … #define mmLB2_LB_DEBUG3 … #define mmLB3_LB_DEBUG3 … #define mmLB4_LB_DEBUG3 … #define mmLB5_LB_DEBUG3 … #define mmLB_TEST_DEBUG_INDEX … #define mmLB0_LB_TEST_DEBUG_INDEX … #define mmLB1_LB_TEST_DEBUG_INDEX … #define mmLB2_LB_TEST_DEBUG_INDEX … #define mmLB3_LB_TEST_DEBUG_INDEX … #define mmLB4_LB_TEST_DEBUG_INDEX … #define mmLB5_LB_TEST_DEBUG_INDEX … #define mmLB_TEST_DEBUG_DATA … #define mmLB0_LB_TEST_DEBUG_DATA … #define mmLB1_LB_TEST_DEBUG_DATA … #define mmLB2_LB_TEST_DEBUG_DATA … #define mmLB3_LB_TEST_DEBUG_DATA … #define mmLB4_LB_TEST_DEBUG_DATA … #define mmLB5_LB_TEST_DEBUG_DATA … #define mmLBV_DATA_FORMAT … #define mmLBV_MEMORY_CTRL … #define mmLBV_MEMORY_SIZE_STATUS … #define mmLBV_DESKTOP_HEIGHT … #define mmLBV_VLINE_START_END … #define mmLBV_VLINE2_START_END … #define mmLBV_V_COUNTER … #define mmLBV_SNAPSHOT_V_COUNTER … #define mmLBV_V_COUNTER_CHROMA … #define mmLBV_SNAPSHOT_V_COUNTER_CHROMA … #define mmLBV_INTERRUPT_MASK … #define mmLBV_VLINE_STATUS … #define mmLBV_VLINE2_STATUS … #define mmLBV_VBLANK_STATUS … #define mmLBV_SYNC_RESET_SEL … #define mmLBV_BLACK_KEYER_R_CR … #define mmLBV_BLACK_KEYER_G_Y … #define mmLBV_BLACK_KEYER_B_CB … #define mmLBV_KEYER_COLOR_CTRL … #define mmLBV_KEYER_COLOR_R_CR … #define mmLBV_KEYER_COLOR_G_Y … #define mmLBV_KEYER_COLOR_B_CB … #define mmLBV_KEYER_COLOR_REP_R_CR … #define mmLBV_KEYER_COLOR_REP_G_Y … #define mmLBV_KEYER_COLOR_REP_B_CB … #define mmLBV_BUFFER_LEVEL_STATUS … #define mmLBV_BUFFER_URGENCY_CTRL … #define mmLBV_BUFFER_URGENCY_STATUS … #define mmLBV_BUFFER_STATUS … #define mmLBV_NO_OUTSTANDING_REQ_STATUS … #define mmLBV_DEBUG … #define mmLBV_DEBUG2 … #define mmLBV_DEBUG3 … #define mmLBV_TEST_DEBUG_INDEX … #define mmLBV_TEST_DEBUG_DATA … #define mmMVP_CONTROL1 … #define mmMVP_CONTROL2 … #define mmMVP_FIFO_CONTROL … #define mmMVP_FIFO_STATUS … #define mmMVP_SLAVE_STATUS … #define mmMVP_INBAND_CNTL_CAP … #define mmMVP_BLACK_KEYER … #define mmMVP_CRC_CNTL … #define mmMVP_CRC_RESULT_BLUE_GREEN … #define mmMVP_CRC_RESULT_RED … #define mmMVP_CONTROL3 … #define mmMVP_RECEIVE_CNT_CNTL1 … #define mmMVP_RECEIVE_CNT_CNTL2 … #define mmMVP_DEBUG … #define mmMVP_TEST_DEBUG_INDEX … #define mmMVP_TEST_DEBUG_DATA … #define ixMVP_DEBUG_12 … #define ixMVP_DEBUG_13 … #define ixMVP_DEBUG_14 … #define ixMVP_DEBUG_15 … #define ixMVP_DEBUG_16 … #define ixMVP_DEBUG_17 … #define mmSCL_COEF_RAM_SELECT … #define mmSCL0_SCL_COEF_RAM_SELECT … #define mmSCL1_SCL_COEF_RAM_SELECT … #define mmSCL2_SCL_COEF_RAM_SELECT … #define mmSCL3_SCL_COEF_RAM_SELECT … #define mmSCL4_SCL_COEF_RAM_SELECT … #define mmSCL5_SCL_COEF_RAM_SELECT … #define mmSCL_COEF_RAM_TAP_DATA … #define mmSCL0_SCL_COEF_RAM_TAP_DATA … #define mmSCL1_SCL_COEF_RAM_TAP_DATA … #define mmSCL2_SCL_COEF_RAM_TAP_DATA … #define mmSCL3_SCL_COEF_RAM_TAP_DATA … #define mmSCL4_SCL_COEF_RAM_TAP_DATA … #define mmSCL5_SCL_COEF_RAM_TAP_DATA … #define mmSCL_MODE … #define mmSCL0_SCL_MODE … #define mmSCL1_SCL_MODE … #define mmSCL2_SCL_MODE … #define mmSCL3_SCL_MODE … #define mmSCL4_SCL_MODE … #define mmSCL5_SCL_MODE … #define mmSCL_TAP_CONTROL … #define mmSCL0_SCL_TAP_CONTROL … #define mmSCL1_SCL_TAP_CONTROL … #define mmSCL2_SCL_TAP_CONTROL … #define mmSCL3_SCL_TAP_CONTROL … #define mmSCL4_SCL_TAP_CONTROL … #define mmSCL5_SCL_TAP_CONTROL … #define mmSCL_CONTROL … #define mmSCL0_SCL_CONTROL … #define mmSCL1_SCL_CONTROL … #define mmSCL2_SCL_CONTROL … #define mmSCL3_SCL_CONTROL … #define mmSCL4_SCL_CONTROL … #define mmSCL5_SCL_CONTROL … #define mmSCL_BYPASS_CONTROL … #define mmSCL0_SCL_BYPASS_CONTROL … #define mmSCL1_SCL_BYPASS_CONTROL … #define mmSCL2_SCL_BYPASS_CONTROL … #define mmSCL3_SCL_BYPASS_CONTROL … #define mmSCL4_SCL_BYPASS_CONTROL … #define mmSCL5_SCL_BYPASS_CONTROL … #define mmSCL_MANUAL_REPLICATE_CONTROL … #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL_AUTOMATIC_MODE_CONTROL … #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL_HORZ_FILTER_CONTROL … #define mmSCL0_SCL_HORZ_FILTER_CONTROL … #define mmSCL1_SCL_HORZ_FILTER_CONTROL … #define mmSCL2_SCL_HORZ_FILTER_CONTROL … #define mmSCL3_SCL_HORZ_FILTER_CONTROL … #define mmSCL4_SCL_HORZ_FILTER_CONTROL … #define mmSCL5_SCL_HORZ_FILTER_CONTROL … #define mmSCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL_HORZ_FILTER_INIT … #define mmSCL0_SCL_HORZ_FILTER_INIT … #define mmSCL1_SCL_HORZ_FILTER_INIT … #define mmSCL2_SCL_HORZ_FILTER_INIT … #define mmSCL3_SCL_HORZ_FILTER_INIT … #define mmSCL4_SCL_HORZ_FILTER_INIT … #define mmSCL5_SCL_HORZ_FILTER_INIT … #define mmSCL_VERT_FILTER_CONTROL … #define mmSCL0_SCL_VERT_FILTER_CONTROL … #define mmSCL1_SCL_VERT_FILTER_CONTROL … #define mmSCL2_SCL_VERT_FILTER_CONTROL … #define mmSCL3_SCL_VERT_FILTER_CONTROL … #define mmSCL4_SCL_VERT_FILTER_CONTROL … #define mmSCL5_SCL_VERT_FILTER_CONTROL … #define mmSCL_VERT_FILTER_SCALE_RATIO … #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL_VERT_FILTER_INIT … #define mmSCL0_SCL_VERT_FILTER_INIT … #define mmSCL1_SCL_VERT_FILTER_INIT … #define mmSCL2_SCL_VERT_FILTER_INIT … #define mmSCL3_SCL_VERT_FILTER_INIT … #define mmSCL4_SCL_VERT_FILTER_INIT … #define mmSCL5_SCL_VERT_FILTER_INIT … #define mmSCL_VERT_FILTER_INIT_BOT … #define mmSCL0_SCL_VERT_FILTER_INIT_BOT … #define mmSCL1_SCL_VERT_FILTER_INIT_BOT … #define mmSCL2_SCL_VERT_FILTER_INIT_BOT … #define mmSCL3_SCL_VERT_FILTER_INIT_BOT … #define mmSCL4_SCL_VERT_FILTER_INIT_BOT … #define mmSCL5_SCL_VERT_FILTER_INIT_BOT … #define mmSCL_ROUND_OFFSET … #define mmSCL0_SCL_ROUND_OFFSET … #define mmSCL1_SCL_ROUND_OFFSET … #define mmSCL2_SCL_ROUND_OFFSET … #define mmSCL3_SCL_ROUND_OFFSET … #define mmSCL4_SCL_ROUND_OFFSET … #define mmSCL5_SCL_ROUND_OFFSET … #define mmSCL_UPDATE … #define mmSCL0_SCL_UPDATE … #define mmSCL1_SCL_UPDATE … #define mmSCL2_SCL_UPDATE … #define mmSCL3_SCL_UPDATE … #define mmSCL4_SCL_UPDATE … #define mmSCL5_SCL_UPDATE … #define mmSCL_F_SHARP_CONTROL … #define mmSCL0_SCL_F_SHARP_CONTROL … #define mmSCL1_SCL_F_SHARP_CONTROL … #define mmSCL2_SCL_F_SHARP_CONTROL … #define mmSCL3_SCL_F_SHARP_CONTROL … #define mmSCL4_SCL_F_SHARP_CONTROL … #define mmSCL5_SCL_F_SHARP_CONTROL … #define mmSCL_ALU_CONTROL … #define mmSCL0_SCL_ALU_CONTROL … #define mmSCL1_SCL_ALU_CONTROL … #define mmSCL2_SCL_ALU_CONTROL … #define mmSCL3_SCL_ALU_CONTROL … #define mmSCL4_SCL_ALU_CONTROL … #define mmSCL5_SCL_ALU_CONTROL … #define mmSCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS … #define mmVIEWPORT_START_SECONDARY … #define mmSCL0_VIEWPORT_START_SECONDARY … #define mmSCL1_VIEWPORT_START_SECONDARY … #define mmSCL2_VIEWPORT_START_SECONDARY … #define mmSCL3_VIEWPORT_START_SECONDARY … #define mmSCL4_VIEWPORT_START_SECONDARY … #define mmSCL5_VIEWPORT_START_SECONDARY … #define mmVIEWPORT_START … #define mmSCL0_VIEWPORT_START … #define mmSCL1_VIEWPORT_START … #define mmSCL2_VIEWPORT_START … #define mmSCL3_VIEWPORT_START … #define mmSCL4_VIEWPORT_START … #define mmSCL5_VIEWPORT_START … #define mmVIEWPORT_SIZE … #define mmSCL0_VIEWPORT_SIZE … #define mmSCL1_VIEWPORT_SIZE … #define mmSCL2_VIEWPORT_SIZE … #define mmSCL3_VIEWPORT_SIZE … #define mmSCL4_VIEWPORT_SIZE … #define mmSCL5_VIEWPORT_SIZE … #define mmEXT_OVERSCAN_LEFT_RIGHT … #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT … #define mmEXT_OVERSCAN_TOP_BOTTOM … #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL_MODE_CHANGE_DET1 … #define mmSCL0_SCL_MODE_CHANGE_DET1 … #define mmSCL1_SCL_MODE_CHANGE_DET1 … #define mmSCL2_SCL_MODE_CHANGE_DET1 … #define mmSCL3_SCL_MODE_CHANGE_DET1 … #define mmSCL4_SCL_MODE_CHANGE_DET1 … #define mmSCL5_SCL_MODE_CHANGE_DET1 … #define mmSCL_MODE_CHANGE_DET2 … #define mmSCL0_SCL_MODE_CHANGE_DET2 … #define mmSCL1_SCL_MODE_CHANGE_DET2 … #define mmSCL2_SCL_MODE_CHANGE_DET2 … #define mmSCL3_SCL_MODE_CHANGE_DET2 … #define mmSCL4_SCL_MODE_CHANGE_DET2 … #define mmSCL5_SCL_MODE_CHANGE_DET2 … #define mmSCL_MODE_CHANGE_DET3 … #define mmSCL0_SCL_MODE_CHANGE_DET3 … #define mmSCL1_SCL_MODE_CHANGE_DET3 … #define mmSCL2_SCL_MODE_CHANGE_DET3 … #define mmSCL3_SCL_MODE_CHANGE_DET3 … #define mmSCL4_SCL_MODE_CHANGE_DET3 … #define mmSCL5_SCL_MODE_CHANGE_DET3 … #define mmSCL_MODE_CHANGE_MASK … #define mmSCL0_SCL_MODE_CHANGE_MASK … #define mmSCL1_SCL_MODE_CHANGE_MASK … #define mmSCL2_SCL_MODE_CHANGE_MASK … #define mmSCL3_SCL_MODE_CHANGE_MASK … #define mmSCL4_SCL_MODE_CHANGE_MASK … #define mmSCL5_SCL_MODE_CHANGE_MASK … #define mmSCL_DEBUG2 … #define mmSCL0_SCL_DEBUG2 … #define mmSCL1_SCL_DEBUG2 … #define mmSCL2_SCL_DEBUG2 … #define mmSCL3_SCL_DEBUG2 … #define mmSCL4_SCL_DEBUG2 … #define mmSCL5_SCL_DEBUG2 … #define mmSCL_DEBUG … #define mmSCL0_SCL_DEBUG … #define mmSCL1_SCL_DEBUG … #define mmSCL2_SCL_DEBUG … #define mmSCL3_SCL_DEBUG … #define mmSCL4_SCL_DEBUG … #define mmSCL5_SCL_DEBUG … #define mmSCL_TEST_DEBUG_INDEX … #define mmSCL0_SCL_TEST_DEBUG_INDEX … #define mmSCL1_SCL_TEST_DEBUG_INDEX … #define mmSCL2_SCL_TEST_DEBUG_INDEX … #define mmSCL3_SCL_TEST_DEBUG_INDEX … #define mmSCL4_SCL_TEST_DEBUG_INDEX … #define mmSCL5_SCL_TEST_DEBUG_INDEX … #define mmSCL_TEST_DEBUG_DATA … #define mmSCL0_SCL_TEST_DEBUG_DATA … #define mmSCL1_SCL_TEST_DEBUG_DATA … #define mmSCL2_SCL_TEST_DEBUG_DATA … #define mmSCL3_SCL_TEST_DEBUG_DATA … #define mmSCL4_SCL_TEST_DEBUG_DATA … #define mmSCL5_SCL_TEST_DEBUG_DATA … #define mmSCLV_COEF_RAM_SELECT … #define mmSCLV_COEF_RAM_TAP_DATA … #define mmSCLV_MODE … #define mmSCLV_TAP_CONTROL … #define mmSCLV_CONTROL … #define mmSCLV_MANUAL_REPLICATE_CONTROL … #define mmSCLV_AUTOMATIC_MODE_CONTROL … #define mmSCLV_HORZ_FILTER_CONTROL … #define mmSCLV_HORZ_FILTER_SCALE_RATIO … #define mmSCLV_HORZ_FILTER_INIT … #define mmSCLV_HORZ_FILTER_SCALE_RATIO_C … #define mmSCLV_HORZ_FILTER_INIT_C … #define mmSCLV_VERT_FILTER_CONTROL … #define mmSCLV_VERT_FILTER_SCALE_RATIO … #define mmSCLV_VERT_FILTER_INIT … #define mmSCLV_VERT_FILTER_INIT_BOT … #define mmSCLV_VERT_FILTER_SCALE_RATIO_C … #define mmSCLV_VERT_FILTER_INIT_C … #define mmSCLV_VERT_FILTER_INIT_BOT_C … #define mmSCLV_ROUND_OFFSET … #define mmSCLV_UPDATE … #define mmSCLV_ALU_CONTROL … #define mmSCLV_VIEWPORT_START … #define mmSCLV_VIEWPORT_START_SECONDARY … #define mmSCLV_VIEWPORT_SIZE … #define mmSCLV_VIEWPORT_START_C … #define mmSCLV_VIEWPORT_START_SECONDARY_C … #define mmSCLV_VIEWPORT_SIZE_C … #define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCLV_MODE_CHANGE_DET1 … #define mmSCLV_MODE_CHANGE_DET2 … #define mmSCLV_MODE_CHANGE_DET3 … #define mmSCLV_MODE_CHANGE_MASK … #define mmSCLV_HORZ_FILTER_INIT_BOT … #define mmSCLV_HORZ_FILTER_INIT_BOT_C … #define mmSCLV_DEBUG2 … #define mmSCLV_DEBUG … #define mmSCLV_TEST_DEBUG_INDEX … #define mmSCLV_TEST_DEBUG_DATA … #define mmCOL_MAN_UPDATE … #define mmCOL_MAN_INPUT_CSC_CONTROL … #define mmINPUT_CSC_C11_C12_A … #define mmINPUT_CSC_C13_C14_A … #define mmINPUT_CSC_C21_C22_A … #define mmINPUT_CSC_C23_C24_A … #define mmINPUT_CSC_C31_C32_A … #define mmINPUT_CSC_C33_C34_A … #define mmINPUT_CSC_C11_C12_B … #define mmINPUT_CSC_C13_C14_B … #define mmINPUT_CSC_C21_C22_B … #define mmINPUT_CSC_C23_C24_B … #define mmINPUT_CSC_C31_C32_B … #define mmINPUT_CSC_C33_C34_B … #define mmPRESCALE_CONTROL … #define mmPRESCALE_VALUES_R … #define mmPRESCALE_VALUES_G … #define mmPRESCALE_VALUES_B … #define mmCOL_MAN_OUTPUT_CSC_CONTROL … #define mmOUTPUT_CSC_C11_C12_A … #define mmOUTPUT_CSC_C13_C14_A … #define mmOUTPUT_CSC_C21_C22_A … #define mmOUTPUT_CSC_C23_C24_A … #define mmOUTPUT_CSC_C31_C32_A … #define mmOUTPUT_CSC_C33_C34_A … #define mmOUTPUT_CSC_C11_C12_B … #define mmOUTPUT_CSC_C13_C14_B … #define mmOUTPUT_CSC_C21_C22_B … #define mmOUTPUT_CSC_C23_C24_B … #define mmOUTPUT_CSC_C31_C32_B … #define mmOUTPUT_CSC_C33_C34_B … #define mmDENORM_CLAMP_CONTROL … #define mmDENORM_CLAMP_RANGE_R_CR … #define mmDENORM_CLAMP_RANGE_G_Y … #define mmDENORM_CLAMP_RANGE_B_CB … #define mmCOL_MAN_FP_CONVERTED_FIELD … #define mmGAMMA_CORR_CONTROL … #define mmGAMMA_CORR_LUT_INDEX … #define mmGAMMA_CORR_LUT_DATA … #define mmGAMMA_CORR_LUT_WRITE_EN_MASK … #define mmGAMMA_CORR_CNTLA_START_CNTL … #define mmGAMMA_CORR_CNTLA_SLOPE_CNTL … #define mmGAMMA_CORR_CNTLA_END_CNTL1 … #define mmGAMMA_CORR_CNTLA_END_CNTL2 … #define mmGAMMA_CORR_CNTLA_REGION_0_1 … #define mmGAMMA_CORR_CNTLA_REGION_2_3 … #define mmGAMMA_CORR_CNTLA_REGION_4_5 … #define mmGAMMA_CORR_CNTLA_REGION_6_7 … #define mmGAMMA_CORR_CNTLA_REGION_8_9 … #define mmGAMMA_CORR_CNTLA_REGION_10_11 … #define mmGAMMA_CORR_CNTLA_REGION_12_13 … #define mmGAMMA_CORR_CNTLA_REGION_14_15 … #define mmGAMMA_CORR_CNTLB_START_CNTL … #define mmGAMMA_CORR_CNTLB_SLOPE_CNTL … #define mmGAMMA_CORR_CNTLB_END_CNTL1 … #define mmGAMMA_CORR_CNTLB_END_CNTL2 … #define mmGAMMA_CORR_CNTLB_REGION_0_1 … #define mmGAMMA_CORR_CNTLB_REGION_2_3 … #define mmGAMMA_CORR_CNTLB_REGION_4_5 … #define mmGAMMA_CORR_CNTLB_REGION_6_7 … #define mmGAMMA_CORR_CNTLB_REGION_8_9 … #define mmGAMMA_CORR_CNTLB_REGION_10_11 … #define mmGAMMA_CORR_CNTLB_REGION_12_13 … #define mmGAMMA_CORR_CNTLB_REGION_14_15 … #define mmPACK_FIFO_ERROR … #define mmOUTPUT_FIFO_ERROR … #define mmINPUT_GAMMA_LUT_AUTOFILL … #define mmINPUT_GAMMA_LUT_RW_INDEX … #define mmINPUT_GAMMA_LUT_SEQ_COLOR … #define mmINPUT_GAMMA_LUT_PWL_DATA … #define mmINPUT_GAMMA_LUT_30_COLOR … #define mmCOL_MAN_INPUT_GAMMA_CONTROL1 … #define mmCOL_MAN_INPUT_GAMMA_CONTROL2 … #define mmINPUT_GAMMA_BW_OFFSETS_B … #define mmINPUT_GAMMA_BW_OFFSETS_G … #define mmINPUT_GAMMA_BW_OFFSETS_R … #define mmCOL_MAN_DEBUG_CONTROL … #define mmCOL_MAN_TEST_DEBUG_INDEX … #define mmCOL_MAN_TEST_DEBUG_DATA … #define mmUNP_GRPH_ENABLE … #define mmUNP_GRPH_CONTROL … #define mmUNP_GRPH_CONTROL_C … #define mmUNP_GRPH_CONTROL_EXP … #define mmUNP_GRPH_SWAP_CNTL … #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L … #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C … #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L … #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C … #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP_GRPH_PITCH_L … #define mmUNP_GRPH_PITCH_C … #define mmUNP_GRPH_SURFACE_OFFSET_X_L … #define mmUNP_GRPH_SURFACE_OFFSET_X_C … #define mmUNP_GRPH_SURFACE_OFFSET_Y_L … #define mmUNP_GRPH_SURFACE_OFFSET_Y_C … #define mmUNP_GRPH_X_START_L … #define mmUNP_GRPH_X_START_C … #define mmUNP_GRPH_Y_START_L … #define mmUNP_GRPH_Y_START_C … #define mmUNP_GRPH_X_END_L … #define mmUNP_GRPH_X_END_C … #define mmUNP_GRPH_Y_END_L … #define mmUNP_GRPH_Y_END_C … #define mmUNP_GRPH_UPDATE … #define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L … #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C … #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L … #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C … #define mmUNP_DVMM_PTE_CONTROL … #define mmUNP_DVMM_PTE_CONTROL_C … #define mmUNP_DVMM_PTE_ARB_CONTROL … #define mmUNP_DVMM_PTE_ARB_CONTROL_C … #define mmUNP_GRPH_INTERRUPT_STATUS … #define mmUNP_GRPH_INTERRUPT_CONTROL … #define mmUNP_GRPH_STEREOSYNC_FLIP … #define mmUNP_FLIP_CONTROL … #define mmUNP_CRC_CONTROL … #define mmUNP_CRC_MASK … #define mmUNP_CRC_CURRENT … #define mmUNP_CRC_LAST … #define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmUNP_HW_ROTATION … #define mmUNP_DEBUG … #define mmUNP_DEBUG2 … #define mmUNP_DVMM_DEBUG … #define mmUNP_TEST_DEBUG_INDEX … #define mmUNP_TEST_DEBUG_DATA … #define mmGENMO_WT … #define mmGENMO_RD … #define mmGENENB … #define mmGENFC_WT … #define mmVGA0_GENFC_WT … #define mmVGA1_GENFC_WT … #define mmGENFC_RD … #define mmGENS0 … #define mmGENS1 … #define mmVGA0_GENS1 … #define mmVGA1_GENS1 … #define mmDAC_DATA … #define mmDAC_MASK … #define mmDAC_R_INDEX … #define mmDAC_W_INDEX … #define mmSEQ8_IDX … #define mmSEQ8_DATA … #define ixSEQ00 … #define ixSEQ01 … #define ixSEQ02 … #define ixSEQ03 … #define ixSEQ04 … #define mmCRTC8_IDX … #define mmVGA0_CRTC8_IDX … #define mmVGA1_CRTC8_IDX … #define mmCRTC8_DATA … #define mmVGA0_CRTC8_DATA … #define mmVGA1_CRTC8_DATA … #define ixCRT00 … #define ixCRT01 … #define ixCRT02 … #define ixCRT03 … #define ixCRT04 … #define ixCRT05 … #define ixCRT06 … #define ixCRT07 … #define ixCRT08 … #define ixCRT09 … #define ixCRT0A … #define ixCRT0B … #define ixCRT0C … #define ixCRT0D … #define ixCRT0E … #define ixCRT0F … #define ixCRT10 … #define ixCRT11 … #define ixCRT12 … #define ixCRT13 … #define ixCRT14 … #define ixCRT15 … #define ixCRT16 … #define ixCRT17 … #define ixCRT18 … #define ixCRT1E … #define ixCRT1F … #define ixCRT22 … #define mmGRPH8_IDX … #define mmGRPH8_DATA … #define ixGRA00 … #define ixGRA01 … #define ixGRA02 … #define ixGRA03 … #define ixGRA04 … #define ixGRA05 … #define ixGRA06 … #define ixGRA07 … #define ixGRA08 … #define mmATTRX … #define mmATTRDW … #define mmATTRDR … #define ixATTR00 … #define ixATTR01 … #define ixATTR02 … #define ixATTR03 … #define ixATTR04 … #define ixATTR05 … #define ixATTR06 … #define ixATTR07 … #define ixATTR08 … #define ixATTR09 … #define ixATTR0A … #define ixATTR0B … #define ixATTR0C … #define ixATTR0D … #define ixATTR0E … #define ixATTR0F … #define ixATTR10 … #define ixATTR11 … #define ixATTR12 … #define ixATTR13 … #define ixATTR14 … #define mmVGA_RENDER_CONTROL … #define mmVGA_SOURCE_SELECT … #define mmVGA_SEQUENCER_RESET_CONTROL … #define mmVGA_MODE_CONTROL … #define mmVGA_SURFACE_PITCH_SELECT … #define mmVGA_MEMORY_BASE_ADDRESS … #define mmVGA_MEMORY_BASE_ADDRESS_HIGH … #define mmVGA_DISPBUF1_SURFACE_ADDR … #define mmVGA_DISPBUF2_SURFACE_ADDR … #define mmVGA_HDP_CONTROL … #define mmVGA_CACHE_CONTROL … #define mmD1VGA_CONTROL … #define mmD2VGA_CONTROL … #define mmD3VGA_CONTROL … #define mmD4VGA_CONTROL … #define mmD5VGA_CONTROL … #define mmD6VGA_CONTROL … #define mmVGA_HW_DEBUG … #define mmVGA_STATUS … #define mmVGA_INTERRUPT_CONTROL … #define mmVGA_STATUS_CLEAR … #define mmVGA_INTERRUPT_STATUS … #define mmVGA_MAIN_CONTROL … #define mmVGA_TEST_CONTROL … #define mmVGA_DEBUG_READBACK_INDEX … #define mmVGA_DEBUG_READBACK_DATA … #define mmVGA_MEM_WRITE_PAGE_ADDR … #define mmVGA_MEM_READ_PAGE_ADDR … #define mmVGA_TEST_DEBUG_INDEX … #define mmVGA_TEST_DEBUG_DATA … #define ixVGADCC_DBG_DCCIF_C … #define mmBPHYC_DAC_MACRO_CNTL … #define mmBPHYC_DAC_AUTO_CALIB_CONTROL … #define mmPLL_REF_DIV … #define mmBPHYC_PLL0_PLL_REF_DIV … #define mmBPHYC_PLL1_PLL_REF_DIV … #define mmBPHYC_PLL2_PLL_REF_DIV … #define mmPLL_FB_DIV … #define mmBPHYC_PLL0_PLL_FB_DIV … #define mmBPHYC_PLL1_PLL_FB_DIV … #define mmBPHYC_PLL2_PLL_FB_DIV … #define mmPLL_POST_DIV … #define mmBPHYC_PLL0_PLL_POST_DIV … #define mmBPHYC_PLL1_PLL_POST_DIV … #define mmBPHYC_PLL2_PLL_POST_DIV … #define mmPLL_SS_AMOUNT_DSFRAC … #define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC … #define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC … #define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC … #define mmPLL_SS_CNTL … #define mmBPHYC_PLL0_PLL_SS_CNTL … #define mmBPHYC_PLL1_PLL_SS_CNTL … #define mmBPHYC_PLL2_PLL_SS_CNTL … #define mmPLL_DS_CNTL … #define mmBPHYC_PLL0_PLL_DS_CNTL … #define mmBPHYC_PLL1_PLL_DS_CNTL … #define mmBPHYC_PLL2_PLL_DS_CNTL … #define mmPLL_IDCLK_CNTL … #define mmBPHYC_PLL0_PLL_IDCLK_CNTL … #define mmBPHYC_PLL1_PLL_IDCLK_CNTL … #define mmBPHYC_PLL2_PLL_IDCLK_CNTL … #define mmPLL_CNTL … #define mmBPHYC_PLL0_PLL_CNTL … #define mmBPHYC_PLL1_PLL_CNTL … #define mmBPHYC_PLL2_PLL_CNTL … #define mmPLL_ANALOG … #define mmBPHYC_PLL0_PLL_ANALOG … #define mmBPHYC_PLL1_PLL_ANALOG … #define mmBPHYC_PLL2_PLL_ANALOG … #define mmPLL_VREG_CNTL … #define mmBPHYC_PLL0_PLL_VREG_CNTL … #define mmBPHYC_PLL1_PLL_VREG_CNTL … #define mmBPHYC_PLL2_PLL_VREG_CNTL … #define mmPLL_UNLOCK_DETECT_CNTL … #define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL … #define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL … #define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL … #define mmPLL_DEBUG_CNTL … #define mmBPHYC_PLL0_PLL_DEBUG_CNTL … #define mmBPHYC_PLL1_PLL_DEBUG_CNTL … #define mmBPHYC_PLL2_PLL_DEBUG_CNTL … #define mmPLL_UPDATE_LOCK … #define mmBPHYC_PLL0_PLL_UPDATE_LOCK … #define mmBPHYC_PLL1_PLL_UPDATE_LOCK … #define mmBPHYC_PLL2_PLL_UPDATE_LOCK … #define mmPLL_UPDATE_CNTL … #define mmBPHYC_PLL0_PLL_UPDATE_CNTL … #define mmBPHYC_PLL1_PLL_UPDATE_CNTL … #define mmBPHYC_PLL2_PLL_UPDATE_CNTL … #define mmPLL_XOR_LOCK … #define mmBPHYC_PLL0_PLL_XOR_LOCK … #define mmBPHYC_PLL1_PLL_XOR_LOCK … #define mmBPHYC_PLL2_PLL_XOR_LOCK … #define mmPLL_ANALOG_CNTL … #define mmBPHYC_PLL0_PLL_ANALOG_CNTL … #define mmBPHYC_PLL1_PLL_ANALOG_CNTL … #define mmBPHYC_PLL2_PLL_ANALOG_CNTL … #define mmVGA25_PPLL_REF_DIV … #define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV … #define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV … #define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV … #define mmVGA28_PPLL_REF_DIV … #define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV … #define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV … #define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV … #define mmVGA41_PPLL_REF_DIV … #define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV … #define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV … #define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV … #define mmVGA25_PPLL_FB_DIV … #define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV … #define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV … #define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV … #define mmVGA28_PPLL_FB_DIV … #define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV … #define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV … #define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV … #define mmVGA41_PPLL_FB_DIV … #define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV … #define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV … #define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV … #define mmVGA25_PPLL_POST_DIV … #define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV … #define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV … #define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV … #define mmVGA28_PPLL_POST_DIV … #define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV … #define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV … #define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV … #define mmVGA41_PPLL_POST_DIV … #define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV … #define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV … #define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV … #define mmVGA25_PPLL_ANALOG … #define mmBPHYC_PLL0_VGA25_PPLL_ANALOG … #define mmBPHYC_PLL1_VGA25_PPLL_ANALOG … #define mmBPHYC_PLL2_VGA25_PPLL_ANALOG … #define mmVGA28_PPLL_ANALOG … #define mmBPHYC_PLL0_VGA28_PPLL_ANALOG … #define mmBPHYC_PLL1_VGA28_PPLL_ANALOG … #define mmBPHYC_PLL2_VGA28_PPLL_ANALOG … #define mmVGA41_PPLL_ANALOG … #define mmBPHYC_PLL0_VGA41_PPLL_ANALOG … #define mmBPHYC_PLL1_VGA41_PPLL_ANALOG … #define mmBPHYC_PLL2_VGA41_PPLL_ANALOG … #define mmDISPPLL_BG_CNTL … #define mmBPHYC_PLL0_DISPPLL_BG_CNTL … #define mmBPHYC_PLL1_DISPPLL_BG_CNTL … #define mmBPHYC_PLL2_DISPPLL_BG_CNTL … #define mmPPLL_DIV_UPDATE_DEBUG … #define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG … #define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG … #define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG … #define mmPPLL_STATUS_DEBUG … #define mmBPHYC_PLL0_PPLL_STATUS_DEBUG … #define mmBPHYC_PLL1_PPLL_STATUS_DEBUG … #define mmBPHYC_PLL2_PPLL_STATUS_DEBUG … #define mmPPLL_DEBUG_MUX_CNTL … #define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL … #define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL … #define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL … #define mmPPLL_SPARE0 … #define mmBPHYC_PLL0_PPLL_SPARE0 … #define mmBPHYC_PLL1_PPLL_SPARE0 … #define mmBPHYC_PLL2_PPLL_SPARE0 … #define mmPPLL_SPARE1 … #define mmBPHYC_PLL0_PPLL_SPARE1 … #define mmBPHYC_PLL1_PPLL_SPARE1 … #define mmBPHYC_PLL2_PPLL_SPARE1 … #define mmUNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 … #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 … #define mmUNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 … #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 … #define mmUNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 … #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 … #define mmUNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 … #define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 … #define mmUNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL … #define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL … #define mmUNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV … #define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV … #define mmUNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 … #define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 … #define mmUNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 … #define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 … #define mmUNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE … #define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE … #define mmUNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL … #define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL … #define mmUNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION … #define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION … #define mmUNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT … #define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT … #define mmUNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL … #define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL … #define mmUNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 … #define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 … #define mmUNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 … #define mmUNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 … #define mmUNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 … #define mmUNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 … #define mmUNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 … #define mmUNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 … #define mmUNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 … #define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 … #define mmUNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL … #define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL … #define mmUNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED … #define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED … #define mmUNIPHY_DEBUG … #define mmBPHYC_UNIPHY0_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY1_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY2_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY3_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY4_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY5_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY6_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY7_UNIPHY_DEBUG … #define mmBPHYC_UNIPHY8_UNIPHY_DEBUG … #define mmDPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL … #define mmDPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL … #define mmDPG_PIPE_DPM_CONTROL … #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL … #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL … #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL … #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL … #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL … #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL … #define mmDPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL … #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDPG_REPEATER_PROGRAM … #define mmDMIF_PG0_DPG_REPEATER_PROGRAM … #define mmDMIF_PG1_DPG_REPEATER_PROGRAM … #define mmDMIF_PG2_DPG_REPEATER_PROGRAM … #define mmDMIF_PG3_DPG_REPEATER_PROGRAM … #define mmDMIF_PG4_DPG_REPEATER_PROGRAM … #define mmDMIF_PG5_DPG_REPEATER_PROGRAM … #define mmDPG_HW_DEBUG_A … #define mmDMIF_PG0_DPG_HW_DEBUG_A … #define mmDMIF_PG1_DPG_HW_DEBUG_A … #define mmDMIF_PG2_DPG_HW_DEBUG_A … #define mmDMIF_PG3_DPG_HW_DEBUG_A … #define mmDMIF_PG4_DPG_HW_DEBUG_A … #define mmDMIF_PG5_DPG_HW_DEBUG_A … #define mmDPG_HW_DEBUG_B … #define mmDMIF_PG0_DPG_HW_DEBUG_B … #define mmDMIF_PG1_DPG_HW_DEBUG_B … #define mmDMIF_PG2_DPG_HW_DEBUG_B … #define mmDMIF_PG3_DPG_HW_DEBUG_B … #define mmDMIF_PG4_DPG_HW_DEBUG_B … #define mmDMIF_PG5_DPG_HW_DEBUG_B … #define mmDPG_HW_DEBUG_11 … #define mmDMIF_PG0_DPG_HW_DEBUG_11 … #define mmDMIF_PG1_DPG_HW_DEBUG_11 … #define mmDMIF_PG2_DPG_HW_DEBUG_11 … #define mmDMIF_PG3_DPG_HW_DEBUG_11 … #define mmDMIF_PG4_DPG_HW_DEBUG_11 … #define mmDMIF_PG5_DPG_HW_DEBUG_11 … #define mmDPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL … #define mmDPG_TEST_DEBUG_INDEX … #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX … #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX … #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX … #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX … #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX … #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX … #define mmDPG_TEST_DEBUG_DATA … #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA … #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA … #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA … #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA … #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA … #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA … #define mmDPGV0_PIPE_ARBITRATION_CONTROL1 … #define mmDPGV1_PIPE_ARBITRATION_CONTROL1 … #define mmDPGV0_PIPE_ARBITRATION_CONTROL2 … #define mmDPGV1_PIPE_ARBITRATION_CONTROL2 … #define mmDPGV0_WATERMARK_MASK_CONTROL … #define mmDPGV1_WATERMARK_MASK_CONTROL … #define mmDPGV0_PIPE_URGENCY_CONTROL … #define mmDPGV1_PIPE_URGENCY_CONTROL … #define mmDPGV0_PIPE_DPM_CONTROL … #define mmDPGV1_PIPE_DPM_CONTROL … #define mmDPGV0_PIPE_STUTTER_CONTROL … #define mmDPGV1_PIPE_STUTTER_CONTROL … #define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDPGV0_REPEATER_PROGRAM … #define mmDPGV1_REPEATER_PROGRAM … #define mmDPGV0_HW_DEBUG_A … #define mmDPGV1_HW_DEBUG_A … #define mmDPGV0_HW_DEBUG_B … #define mmDPGV1_HW_DEBUG_B … #define mmDPGV0_HW_DEBUG_11 … #define mmDPGV1_HW_DEBUG_11 … #define mmDPGV0_CHK_PRE_PROC_CNTL … #define mmDPGV1_CHK_PRE_PROC_CNTL … #define mmDPGV_TEST_DEBUG_INDEX … #define mmDPGV_TEST_DEBUG_DATA … #define ixDPGV0_DEBUG00_DMIFARB … #define ixDPGV1_DEBUG00_DMIFARB … #define ixDPGV0_DEBUG01_DMIFARB … #define ixDPGV1_DEBUG01_DMIFARB … #define ixDPGV0_DEBUG02_DMIFARB … #define ixDPGV1_DEBUG02_DMIFARB … #define ixDPGV0_DEBUG03_DMIFARB … #define ixDPGV1_DEBUG03_DMIFARB … #define ixDPGV0_DEBUG04_DMIFARB … #define ixDPGV1_DEBUG04_DMIFARB … #define ixDPGV0_DEBUG00 … #define ixDPGV1_DEBUG00 … #define ixDPGV0_DEBUG01 … #define ixDPGV1_DEBUG01 … #define ixDPGV0_DEBUG02 … #define ixDPGV1_DEBUG02 … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY … #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmAZALIA_F0_CODEC_DEBUG … #define mmAZALIA_F0_GTC_GROUP_OFFSET0 … #define mmAZALIA_F0_GTC_GROUP_OFFSET1 … #define mmAZALIA_F0_GTC_GROUP_OFFSET2 … #define mmAZALIA_F0_GTC_GROUP_OFFSET3 … #define mmAZALIA_F0_GTC_GROUP_OFFSET4 … #define mmAZALIA_F0_GTC_GROUP_OFFSET5 … #define mmAZALIA_F0_GTC_GROUP_OFFSET6 … #define mmGLOBAL_CAPABILITIES … #define mmMINOR_VERSION … #define mmMAJOR_VERSION … #define mmOUTPUT_PAYLOAD_CAPABILITY … #define mmINPUT_PAYLOAD_CAPABILITY … #define mmGLOBAL_CONTROL … #define mmWAKE_ENABLE … #define mmSTATE_CHANGE_STATUS … #define mmGLOBAL_STATUS … #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY … #define mmINPUT_STREAM_PAYLOAD_CAPABILITY … #define mmINTERRUPT_CONTROL … #define mmINTERRUPT_STATUS … #define mmWALL_CLOCK_COUNTER … #define mmSTREAM_SYNCHRONIZATION … #define mmCORB_LOWER_BASE_ADDRESS … #define mmCORB_UPPER_BASE_ADDRESS … #define mmCORB_WRITE_POINTER … #define mmCORB_READ_POINTER … #define mmCORB_CONTROL … #define mmCORB_STATUS … #define mmCORB_SIZE … #define mmRIRB_LOWER_BASE_ADDRESS … #define mmRIRB_UPPER_BASE_ADDRESS … #define mmRIRB_WRITE_POINTER … #define mmRESPONSE_INTERRUPT_COUNT … #define mmRIRB_CONTROL … #define mmRIRB_STATUS … #define mmRIRB_SIZE … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE … #define mmIMMEDIATE_COMMAND_STATUS … #define mmDMA_POSITION_LOWER_BASE_ADDRESS … #define mmDMA_POSITION_UPPER_BASE_ADDRESS … #define mmWALL_CLOCK_COUNTER_ALIAS … #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 … #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA … #define ixAUDIO_DESCRIPTOR0 … #define ixAUDIO_DESCRIPTOR1 … #define ixAUDIO_DESCRIPTOR2 … #define ixAUDIO_DESCRIPTOR3 … #define ixAUDIO_DESCRIPTOR4 … #define ixAUDIO_DESCRIPTOR5 … #define ixAUDIO_DESCRIPTOR6 … #define ixAUDIO_DESCRIPTOR7 … #define ixAUDIO_DESCRIPTOR8 … #define ixAUDIO_DESCRIPTOR9 … #define ixAUDIO_DESCRIPTOR10 … #define ixAUDIO_DESCRIPTOR11 … #define ixAUDIO_DESCRIPTOR12 … #define ixAUDIO_DESCRIPTOR13 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC … #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 … #define ixSINK_DESCRIPTION0 … #define ixSINK_DESCRIPTION1 … #define ixSINK_DESCRIPTION2 … #define ixSINK_DESCRIPTION3 … #define ixSINK_DESCRIPTION4 … #define ixSINK_DESCRIPTION5 … #define ixSINK_DESCRIPTION6 … #define ixSINK_DESCRIPTION7 … #define ixSINK_DESCRIPTION8 … #define ixSINK_DESCRIPTION9 … #define ixSINK_DESCRIPTION10 … #define ixSINK_DESCRIPTION11 … #define ixSINK_DESCRIPTION12 … #define ixSINK_DESCRIPTION13 … #define ixSINK_DESCRIPTION14 … #define ixSINK_DESCRIPTION15 … #define ixSINK_DESCRIPTION16 … #define ixSINK_DESCRIPTION17 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define mmAZALIA_CONTROLLER_CLOCK_GATING … #define mmAZALIA_AUDIO_DTO … #define mmAZALIA_AUDIO_DTO_CONTROL … #define mmAZALIA_SCLK_CONTROL … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE … #define mmAZALIA_DATA_DMA_CONTROL … #define mmAZALIA_BDL_DMA_CONTROL … #define mmAZALIA_RIRB_AND_DP_CONTROL … #define mmAZALIA_CORB_DMA_CONTROL … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER … #define mmAZALIA_CYCLIC_BUFFER_SYNC … #define mmAZALIA_GLOBAL_CAPABILITIES … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_CONTROLLER_DEBUG … #define mmAZALIA_MEM_PWR_CTRL … #define mmAZALIA_MEM_PWR_STATUS … #define mmDCI_PG_DEBUG_CONFIG … #define mmAZALIA_INPUT_CRC0_CONTROL0 … #define mmAZALIA_INPUT_CRC0_CONTROL1 … #define mmAZALIA_INPUT_CRC0_CONTROL2 … #define mmAZALIA_INPUT_CRC0_CONTROL3 … #define mmAZALIA_INPUT_CRC0_RESULT … #define ixAZALIA_INPUT_CRC0_CHANNEL0 … #define ixAZALIA_INPUT_CRC0_CHANNEL1 … #define ixAZALIA_INPUT_CRC0_CHANNEL2 … #define ixAZALIA_INPUT_CRC0_CHANNEL3 … #define ixAZALIA_INPUT_CRC0_CHANNEL4 … #define ixAZALIA_INPUT_CRC0_CHANNEL5 … #define ixAZALIA_INPUT_CRC0_CHANNEL6 … #define ixAZALIA_INPUT_CRC0_CHANNEL7 … #define mmAZALIA_INPUT_CRC1_CONTROL0 … #define mmAZALIA_INPUT_CRC1_CONTROL1 … #define mmAZALIA_INPUT_CRC1_CONTROL2 … #define mmAZALIA_INPUT_CRC1_CONTROL3 … #define mmAZALIA_INPUT_CRC1_RESULT … #define ixAZALIA_INPUT_CRC1_CHANNEL0 … #define ixAZALIA_INPUT_CRC1_CHANNEL1 … #define ixAZALIA_INPUT_CRC1_CHANNEL2 … #define ixAZALIA_INPUT_CRC1_CHANNEL3 … #define ixAZALIA_INPUT_CRC1_CHANNEL4 … #define ixAZALIA_INPUT_CRC1_CHANNEL5 … #define ixAZALIA_INPUT_CRC1_CHANNEL6 … #define ixAZALIA_INPUT_CRC1_CHANNEL7 … #define mmAZALIA_CRC0_CONTROL0 … #define mmAZALIA_CRC0_CONTROL1 … #define mmAZALIA_CRC0_CONTROL2 … #define mmAZALIA_CRC0_CONTROL3 … #define mmAZALIA_CRC0_RESULT … #define ixAZALIA_CRC0_CHANNEL0 … #define ixAZALIA_CRC0_CHANNEL1 … #define ixAZALIA_CRC0_CHANNEL2 … #define ixAZALIA_CRC0_CHANNEL3 … #define ixAZALIA_CRC0_CHANNEL4 … #define ixAZALIA_CRC0_CHANNEL5 … #define ixAZALIA_CRC0_CHANNEL6 … #define ixAZALIA_CRC0_CHANNEL7 … #define mmAZALIA_CRC1_CONTROL0 … #define mmAZALIA_CRC1_CONTROL1 … #define mmAZALIA_CRC1_CONTROL2 … #define mmAZALIA_CRC1_CONTROL3 … #define mmAZALIA_CRC1_RESULT … #define ixAZALIA_CRC1_CHANNEL0 … #define ixAZALIA_CRC1_CHANNEL1 … #define ixAZALIA_CRC1_CHANNEL2 … #define ixAZALIA_CRC1_CHANNEL3 … #define ixAZALIA_CRC1_CHANNEL4 … #define ixAZALIA_CRC1_CHANNEL5 … #define ixAZALIA_CRC1_CHANNEL6 … #define ixAZALIA_CRC1_CHANNEL7 … #define mmAZ_TEST_DEBUG_INDEX … #define mmAZ_TEST_DEBUG_DATA … #define mmAZALIA_STREAM_INDEX … #define mmAZF0STREAM0_AZALIA_STREAM_INDEX … #define mmAZF0STREAM1_AZALIA_STREAM_INDEX … #define mmAZF0STREAM2_AZALIA_STREAM_INDEX … #define mmAZF0STREAM3_AZALIA_STREAM_INDEX … #define mmAZF0STREAM4_AZALIA_STREAM_INDEX … #define mmAZF0STREAM5_AZALIA_STREAM_INDEX … #define mmAZF0STREAM6_AZALIA_STREAM_INDEX … #define mmAZF0STREAM7_AZALIA_STREAM_INDEX … #define mmAZF0STREAM8_AZALIA_STREAM_INDEX … #define mmAZF0STREAM9_AZALIA_STREAM_INDEX … #define mmAZF0STREAM10_AZALIA_STREAM_INDEX … #define mmAZF0STREAM11_AZALIA_STREAM_INDEX … #define mmAZF0STREAM12_AZALIA_STREAM_INDEX … #define mmAZF0STREAM13_AZALIA_STREAM_INDEX … #define mmAZF0STREAM14_AZALIA_STREAM_INDEX … #define mmAZF0STREAM15_AZALIA_STREAM_INDEX … #define mmAZALIA_STREAM_DATA … #define mmAZF0STREAM0_AZALIA_STREAM_DATA … #define mmAZF0STREAM1_AZALIA_STREAM_DATA … #define mmAZF0STREAM2_AZALIA_STREAM_DATA … #define mmAZF0STREAM3_AZALIA_STREAM_DATA … #define mmAZF0STREAM4_AZALIA_STREAM_DATA … #define mmAZF0STREAM5_AZALIA_STREAM_DATA … #define mmAZF0STREAM6_AZALIA_STREAM_DATA … #define mmAZF0STREAM7_AZALIA_STREAM_DATA … #define mmAZF0STREAM8_AZALIA_STREAM_DATA … #define mmAZF0STREAM9_AZALIA_STREAM_DATA … #define mmAZF0STREAM10_AZALIA_STREAM_DATA … #define mmAZF0STREAM11_AZALIA_STREAM_DATA … #define mmAZF0STREAM12_AZALIA_STREAM_DATA … #define mmAZF0STREAM13_AZALIA_STREAM_DATA … #define mmAZF0STREAM14_AZALIA_STREAM_DATA … #define mmAZF0STREAM15_AZALIA_STREAM_DATA … #define ixAZALIA_FIFO_SIZE_CONTROL … #define ixAZALIA_LATENCY_COUNTER_CONTROL … #define ixAZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZALIA_CUMULATIVE_REQUEST_COUNT … #define ixAZALIA_STREAM_DEBUG … #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA … #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG … #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG … #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define mmBLND_CONTROL … #define mmBLND0_BLND_CONTROL … #define mmBLND1_BLND_CONTROL … #define mmBLND2_BLND_CONTROL … #define mmBLND3_BLND_CONTROL … #define mmBLND4_BLND_CONTROL … #define mmBLND5_BLND_CONTROL … #define mmBLND_SM_CONTROL2 … #define mmBLND0_BLND_SM_CONTROL2 … #define mmBLND1_BLND_SM_CONTROL2 … #define mmBLND2_BLND_SM_CONTROL2 … #define mmBLND3_BLND_SM_CONTROL2 … #define mmBLND4_BLND_SM_CONTROL2 … #define mmBLND5_BLND_SM_CONTROL2 … #define mmBLND_CONTROL2 … #define mmBLND0_BLND_CONTROL2 … #define mmBLND1_BLND_CONTROL2 … #define mmBLND2_BLND_CONTROL2 … #define mmBLND3_BLND_CONTROL2 … #define mmBLND4_BLND_CONTROL2 … #define mmBLND5_BLND_CONTROL2 … #define mmBLND_UPDATE … #define mmBLND0_BLND_UPDATE … #define mmBLND1_BLND_UPDATE … #define mmBLND2_BLND_UPDATE … #define mmBLND3_BLND_UPDATE … #define mmBLND4_BLND_UPDATE … #define mmBLND5_BLND_UPDATE … #define mmBLND_UNDERFLOW_INTERRUPT … #define mmBLND0_BLND_UNDERFLOW_INTERRUPT … #define mmBLND1_BLND_UNDERFLOW_INTERRUPT … #define mmBLND2_BLND_UNDERFLOW_INTERRUPT … #define mmBLND3_BLND_UNDERFLOW_INTERRUPT … #define mmBLND4_BLND_UNDERFLOW_INTERRUPT … #define mmBLND5_BLND_UNDERFLOW_INTERRUPT … #define mmBLND_V_UPDATE_LOCK … #define mmBLND0_BLND_V_UPDATE_LOCK … #define mmBLND1_BLND_V_UPDATE_LOCK … #define mmBLND2_BLND_V_UPDATE_LOCK … #define mmBLND3_BLND_V_UPDATE_LOCK … #define mmBLND4_BLND_V_UPDATE_LOCK … #define mmBLND5_BLND_V_UPDATE_LOCK … #define mmBLND_REG_UPDATE_STATUS … #define mmBLND0_BLND_REG_UPDATE_STATUS … #define mmBLND1_BLND_REG_UPDATE_STATUS … #define mmBLND2_BLND_REG_UPDATE_STATUS … #define mmBLND3_BLND_REG_UPDATE_STATUS … #define mmBLND4_BLND_REG_UPDATE_STATUS … #define mmBLND5_BLND_REG_UPDATE_STATUS … #define mmBLND_DEBUG … #define mmBLND0_BLND_DEBUG … #define mmBLND1_BLND_DEBUG … #define mmBLND2_BLND_DEBUG … #define mmBLND3_BLND_DEBUG … #define mmBLND4_BLND_DEBUG … #define mmBLND5_BLND_DEBUG … #define mmBLND_TEST_DEBUG_INDEX … #define mmBLND0_BLND_TEST_DEBUG_INDEX … #define mmBLND1_BLND_TEST_DEBUG_INDEX … #define mmBLND2_BLND_TEST_DEBUG_INDEX … #define mmBLND3_BLND_TEST_DEBUG_INDEX … #define mmBLND4_BLND_TEST_DEBUG_INDEX … #define mmBLND5_BLND_TEST_DEBUG_INDEX … #define mmBLND_TEST_DEBUG_DATA … #define mmBLND0_BLND_TEST_DEBUG_DATA … #define mmBLND1_BLND_TEST_DEBUG_DATA … #define mmBLND2_BLND_TEST_DEBUG_DATA … #define mmBLND3_BLND_TEST_DEBUG_DATA … #define mmBLND4_BLND_TEST_DEBUG_DATA … #define mmBLND5_BLND_TEST_DEBUG_DATA … #define mmWB_ENABLE … #define mmWB_EC_CONFIG … #define mmCNV_MODE … #define mmCNV_WINDOW_START … #define mmCNV_WINDOW_SIZE … #define mmCNV_UPDATE … #define mmCNV_SOURCE_SIZE … #define mmCNV_CSC_CONTROL … #define mmCNV_CSC_C11_C12 … #define mmCNV_CSC_C13_C14 … #define mmCNV_CSC_C21_C22 … #define mmCNV_CSC_C23_C24 … #define mmCNV_CSC_C31_C32 … #define mmCNV_CSC_C33_C34 … #define mmCNV_CSC_ROUND_OFFSET_R … #define mmCNV_CSC_ROUND_OFFSET_G … #define mmCNV_CSC_ROUND_OFFSET_B … #define mmCNV_CSC_CLAMP_R … #define mmCNV_CSC_CLAMP_G … #define mmCNV_CSC_CLAMP_B … #define mmCNV_TEST_CNTL … #define mmCNV_TEST_CRC_RED … #define mmCNV_TEST_CRC_GREEN … #define mmCNV_TEST_CRC_BLUE … #define mmWB_DEBUG_CTRL … #define mmWB_DBG_MODE … #define mmWB_HW_DEBUG … #define mmCNV_INPUT_SELECT … #define mmWB_SOFT_RESET … #define mmCNV_TEST_DEBUG_INDEX … #define mmCNV_TEST_DEBUG_DATA … #define mmDCFE_CLOCK_CONTROL … #define mmDCFE0_DCFE_CLOCK_CONTROL … #define mmDCFE1_DCFE_CLOCK_CONTROL … #define mmDCFE2_DCFE_CLOCK_CONTROL … #define mmDCFE3_DCFE_CLOCK_CONTROL … #define mmDCFE4_DCFE_CLOCK_CONTROL … #define mmDCFE5_DCFE_CLOCK_CONTROL … #define mmDCFE_SOFT_RESET … #define mmDCFE0_DCFE_SOFT_RESET … #define mmDCFE1_DCFE_SOFT_RESET … #define mmDCFE2_DCFE_SOFT_RESET … #define mmDCFE3_DCFE_SOFT_RESET … #define mmDCFE4_DCFE_SOFT_RESET … #define mmDCFE5_DCFE_SOFT_RESET … #define mmDCFE_DBG_CONFIG … #define mmDCFE0_DCFE_DBG_CONFIG … #define mmDCFE1_DCFE_DBG_CONFIG … #define mmDCFE2_DCFE_DBG_CONFIG … #define mmDCFE3_DCFE_DBG_CONFIG … #define mmDCFE4_DCFE_DBG_CONFIG … #define mmDCFE5_DCFE_DBG_CONFIG … #define mmDCFE_MEM_PWR_CTRL … #define mmDCFE0_DCFE_MEM_PWR_CTRL … #define mmDCFE1_DCFE_MEM_PWR_CTRL … #define mmDCFE2_DCFE_MEM_PWR_CTRL … #define mmDCFE3_DCFE_MEM_PWR_CTRL … #define mmDCFE4_DCFE_MEM_PWR_CTRL … #define mmDCFE5_DCFE_MEM_PWR_CTRL … #define mmDCFE_MEM_PWR_CTRL2 … #define mmDCFE0_DCFE_MEM_PWR_CTRL2 … #define mmDCFE1_DCFE_MEM_PWR_CTRL2 … #define mmDCFE2_DCFE_MEM_PWR_CTRL2 … #define mmDCFE3_DCFE_MEM_PWR_CTRL2 … #define mmDCFE4_DCFE_MEM_PWR_CTRL2 … #define mmDCFE5_DCFE_MEM_PWR_CTRL2 … #define mmDCFE_MEM_PWR_STATUS … #define mmDCFE0_DCFE_MEM_PWR_STATUS … #define mmDCFE1_DCFE_MEM_PWR_STATUS … #define mmDCFE2_DCFE_MEM_PWR_STATUS … #define mmDCFE3_DCFE_MEM_PWR_STATUS … #define mmDCFE4_DCFE_MEM_PWR_STATUS … #define mmDCFE5_DCFE_MEM_PWR_STATUS … #define mmDCFE_MISC … #define mmDCFE0_DCFE_MISC … #define mmDCFE1_DCFE_MISC … #define mmDCFE2_DCFE_MISC … #define mmDCFE3_DCFE_MISC … #define mmDCFE4_DCFE_MISC … #define mmDCFE5_DCFE_MISC … #define mmDCFEV_CLOCK_CONTROL … #define mmDCFEV_SOFT_RESET … #define mmDCFEV_DMIFV_CLOCK_CONTROL … #define mmDCFEV_DBG_CONFIG … #define mmDCFEV_DMIFV_MEM_PWR_CTRL … #define mmDCFEV_DMIFV_MEM_PWR_STATUS … #define mmDCFEV_MEM_PWR_CTRL … #define mmDCFEV_MEM_PWR_CTRL2 … #define mmDCFEV_MEM_PWR_STATUS … #define mmDCFEV_DMIFV_DEBUG … #define mmDCFEV_MISC … #define mmDC_HPD_INT_STATUS … #define mmHPD0_DC_HPD_INT_STATUS … #define mmHPD1_DC_HPD_INT_STATUS … #define mmHPD2_DC_HPD_INT_STATUS … #define mmHPD3_DC_HPD_INT_STATUS … #define mmHPD4_DC_HPD_INT_STATUS … #define mmHPD5_DC_HPD_INT_STATUS … #define mmDC_HPD_INT_CONTROL … #define mmHPD0_DC_HPD_INT_CONTROL … #define mmHPD1_DC_HPD_INT_CONTROL … #define mmHPD2_DC_HPD_INT_CONTROL … #define mmHPD3_DC_HPD_INT_CONTROL … #define mmHPD4_DC_HPD_INT_CONTROL … #define mmHPD5_DC_HPD_INT_CONTROL … #define mmDC_HPD_CONTROL … #define mmHPD0_DC_HPD_CONTROL … #define mmHPD1_DC_HPD_CONTROL … #define mmHPD2_DC_HPD_CONTROL … #define mmHPD3_DC_HPD_CONTROL … #define mmHPD4_DC_HPD_CONTROL … #define mmHPD5_DC_HPD_CONTROL … #define mmDC_HPD_FAST_TRAIN_CNTL … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL … #define mmDC_HPD_TOGGLE_FILT_CNTL … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL … #define mmDCO_SCRATCH0 … #define mmDCO_SCRATCH1 … #define mmDCO_SCRATCH2 … #define mmDCO_SCRATCH3 … #define mmDCO_SCRATCH4 … #define mmDCO_SCRATCH5 … #define mmDCO_SCRATCH6 … #define mmDCO_SCRATCH7 … #define mmDCE_VCE_CONTROL … #define mmDISP_INTERRUPT_STATUS … #define mmDISP_INTERRUPT_STATUS_CONTINUE … #define mmDISP_INTERRUPT_STATUS_CONTINUE2 … #define mmDISP_INTERRUPT_STATUS_CONTINUE3 … #define mmDISP_INTERRUPT_STATUS_CONTINUE4 … #define mmDISP_INTERRUPT_STATUS_CONTINUE5 … #define mmDISP_INTERRUPT_STATUS_CONTINUE6 … #define mmDISP_INTERRUPT_STATUS_CONTINUE7 … #define mmDISP_INTERRUPT_STATUS_CONTINUE8 … #define mmDISP_INTERRUPT_STATUS_CONTINUE9 … #define mmDISP_INTERRUPT_STATUS_CONTINUE10 … #define mmDCO_MEM_PWR_STATUS … #define mmDCO_MEM_PWR_STATUS1 … #define mmDCO_MEM_PWR_CTRL … #define mmDCO_MEM_PWR_CTRL2 … #define mmDCO_CLK_CNTL … #define mmDCO_CLK_CNTL2 … #define mmDCO_CLK_CNTL3 … #define mmDPDBG_CNTL … #define mmDPDBG_INTERRUPT … #define mmDCO_POWER_MANAGEMENT_CNTL … #define mmDCO_SOFT_RESET … #define mmDIG_SOFT_RESET … #define mmDIG_SOFT_RESET_2 … #define mmDCO_STEREOSYNC_SEL … #define mmDCO_TEST_DEBUG_INDEX … #define mmDCO_TEST_DEBUG_DATA … #define mmDC_I2C_CONTROL … #define mmDC_I2C_ARBITRATION … #define mmDC_I2C_INTERRUPT_CONTROL … #define mmDC_I2C_SW_STATUS … #define mmDC_I2C_DDC1_HW_STATUS … #define mmDC_I2C_DDC2_HW_STATUS … #define mmDC_I2C_DDC3_HW_STATUS … #define mmDC_I2C_DDC4_HW_STATUS … #define mmDC_I2C_DDC5_HW_STATUS … #define mmDC_I2C_DDC6_HW_STATUS … #define mmDC_I2C_DDC1_SPEED … #define mmDC_I2C_DDC1_SETUP … #define mmDC_I2C_DDC2_SPEED … #define mmDC_I2C_DDC2_SETUP … #define mmDC_I2C_DDC3_SPEED … #define mmDC_I2C_DDC3_SETUP … #define mmDC_I2C_DDC4_SPEED … #define mmDC_I2C_DDC4_SETUP … #define mmDC_I2C_DDC5_SPEED … #define mmDC_I2C_DDC5_SETUP … #define mmDC_I2C_DDC6_SPEED … #define mmDC_I2C_DDC6_SETUP … #define mmDC_I2C_TRANSACTION0 … #define mmDC_I2C_TRANSACTION1 … #define mmDC_I2C_TRANSACTION2 … #define mmDC_I2C_TRANSACTION3 … #define mmDC_I2C_DATA … #define mmDC_I2C_DDCVGA_HW_STATUS … #define mmDC_I2C_DDCVGA_SPEED … #define mmDC_I2C_DDCVGA_SETUP … #define mmDC_I2C_EDID_DETECT_CTRL … #define mmDC_I2C_READ_REQUEST_INTERRUPT … #define mmGENERIC_I2C_CONTROL … #define mmGENERIC_I2C_INTERRUPT_CONTROL … #define mmGENERIC_I2C_STATUS … #define mmGENERIC_I2C_SPEED … #define mmGENERIC_I2C_SETUP … #define mmGENERIC_I2C_TRANSACTION … #define mmGENERIC_I2C_DATA … #define mmGENERIC_I2C_PIN_SELECTION … #define mmGENERIC_I2C_PIN_DEBUG … #define mmBLNDV_CONTROL … #define mmBLNDV_SM_CONTROL2 … #define mmBLNDV_CONTROL2 … #define mmBLNDV_UPDATE … #define mmBLNDV_UNDERFLOW_INTERRUPT … #define mmBLNDV_V_UPDATE_LOCK … #define mmBLNDV_REG_UPDATE_STATUS … #define mmBLNDV_DEBUG … #define mmBLNDV_TEST_DEBUG_INDEX … #define mmBLNDV_TEST_DEBUG_DATA … #define mmCRTCV_H_BLANK_EARLY_NUM … #define mmCRTCV_H_TOTAL … #define mmCRTCV_H_BLANK_START_END … #define mmCRTCV_H_SYNC_A … #define mmCRTCV_H_SYNC_A_CNTL … #define mmCRTCV_H_SYNC_B … #define mmCRTCV_H_SYNC_B_CNTL … #define mmCRTCV_VBI_END … #define mmCRTCV_V_TOTAL … #define mmCRTCV_V_TOTAL_MIN … #define mmCRTCV_V_TOTAL_MAX … #define mmCRTCV_V_TOTAL_CONTROL … #define mmCRTCV_V_TOTAL_INT_STATUS … #define mmCRTCV_VSYNC_NOM_INT_STATUS … #define mmCRTCV_V_BLANK_START_END … #define mmCRTCV_V_SYNC_A … #define mmCRTCV_V_SYNC_A_CNTL … #define mmCRTCV_V_SYNC_B … #define mmCRTCV_V_SYNC_B_CNTL … #define mmCRTCV_DTMTEST_CNTL … #define mmCRTCV_DTMTEST_STATUS_POSITION … #define mmCRTCV_TRIGA_CNTL … #define mmCRTCV_TRIGA_MANUAL_TRIG … #define mmCRTCV_TRIGB_CNTL … #define mmCRTCV_TRIGB_MANUAL_TRIG … #define mmCRTCV_FORCE_COUNT_NOW_CNTL … #define mmCRTCV_FLOW_CONTROL … #define mmCRTCV_STEREO_FORCE_NEXT_EYE … #define mmCRTCV_AVSYNC_COUNTER … #define mmCRTCV_CONTROL … #define mmCRTCV_BLANK_CONTROL … #define mmCRTCV_INTERLACE_CONTROL … #define mmCRTCV_INTERLACE_STATUS … #define mmCRTCV_FIELD_INDICATION_CONTROL … #define mmCRTCV_PIXEL_DATA_READBACK0 … #define mmCRTCV_PIXEL_DATA_READBACK1 … #define mmCRTCV_STATUS … #define mmCRTCV_STATUS_POSITION … #define mmCRTCV_NOM_VERT_POSITION … #define mmCRTCV_STATUS_FRAME_COUNT … #define mmCRTCV_STATUS_VF_COUNT … #define mmCRTCV_STATUS_HV_COUNT … #define mmCRTCV_COUNT_CONTROL … #define mmCRTCV_COUNT_RESET … #define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTCV_VERT_SYNC_CONTROL … #define mmCRTCV_STEREO_STATUS … #define mmCRTCV_STEREO_CONTROL … #define mmCRTCV_SNAPSHOT_STATUS … #define mmCRTCV_SNAPSHOT_CONTROL … #define mmCRTCV_SNAPSHOT_POSITION … #define mmCRTCV_SNAPSHOT_FRAME … #define mmCRTCV_START_LINE_CONTROL … #define mmCRTCV_INTERRUPT_CONTROL … #define mmCRTCV_UPDATE_LOCK … #define mmCRTCV_DOUBLE_BUFFER_CONTROL … #define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTCV_TEST_PATTERN_CONTROL … #define mmCRTCV_TEST_PATTERN_PARAMETERS … #define mmCRTCV_TEST_PATTERN_COLOR … #define mmCRTCV_MASTER_UPDATE_LOCK … #define mmCRTCV_MASTER_UPDATE_MODE … #define mmCRTCV_MVP_INBAND_CNTL_INSERT … #define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTCV_MVP_STATUS … #define mmCRTCV_MASTER_EN … #define mmCRTCV_ALLOW_STOP_OFF_V_CNT … #define mmCRTCV_V_UPDATE_INT_STATUS … #define mmCRTCV_OVERSCAN_COLOR … #define mmCRTCV_OVERSCAN_COLOR_EXT … #define mmCRTCV_BLANK_DATA_COLOR … #define mmCRTCV_BLANK_DATA_COLOR_EXT … #define mmCRTCV_BLACK_COLOR … #define mmCRTCV_BLACK_COLOR_EXT … #define mmCRTCV_VERTICAL_INTERRUPT0_POSITION … #define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTCV_VERTICAL_INTERRUPT1_POSITION … #define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTCV_VERTICAL_INTERRUPT2_POSITION … #define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTCV_CRC_CNTL … #define mmCRTCV_CRC0_WINDOWA_X_CONTROL … #define mmCRTCV_CRC0_WINDOWA_Y_CONTROL … #define mmCRTCV_CRC0_WINDOWB_X_CONTROL … #define mmCRTCV_CRC0_WINDOWB_Y_CONTROL … #define mmCRTCV_CRC0_DATA_RG … #define mmCRTCV_CRC0_DATA_B … #define mmCRTCV_CRC1_WINDOWA_X_CONTROL … #define mmCRTCV_CRC1_WINDOWA_Y_CONTROL … #define mmCRTCV_CRC1_WINDOWB_X_CONTROL … #define mmCRTCV_CRC1_WINDOWB_Y_CONTROL … #define mmCRTCV_CRC1_DATA_RG … #define mmCRTCV_CRC1_DATA_B … #define mmCRTCV_STATIC_SCREEN_CONTROL … #define mmCRTCV_3D_STRUCTURE_CONTROL … #define mmCRTCV_GSL_VSYNC_GAP … #define mmCRTCV_GSL_WINDOW … #define mmCRTCV_GSL_CONTROL … #define mmCRTCV_TEST_DEBUG_INDEX … #define mmCRTCV_TEST_DEBUG_DATA … #define mmXDMA_MC_PCIE_CLIENT_CONFIG … #define mmXDMA_LOCAL_SURFACE_TILING1 … #define mmXDMA_LOCAL_SURFACE_TILING2 … #define mmXDMA_INTERRUPT … #define mmXDMA_CLOCK_GATING_CNTL … #define mmXDMA_MEM_POWER_CNTL … #define mmXDMA_IF_BIF_STATUS … #define mmXDMA_PERF_MEAS_STATUS … #define mmXDMA_IF_STATUS … #define mmXDMA_TEST_DEBUG_INDEX … #define mmXDMA_TEST_DEBUG_DATA … #define mmXDMA_RBBMIF_RDWR_CNTL … #define mmXDMA_PG_CONTROL … #define mmXDMA_PG_WDATA … #define mmXDMA_PG_STATUS … #define mmXDMA_AON_TEST_DEBUG_INDEX … #define mmXDMA_AON_TEST_DEBUG_DATA … #define mmXDMA_MSTR_CNTL … #define mmXDMA_MSTR_STATUS … #define mmXDMA_MSTR_MEM_CLIENT_CONFIG … #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR … #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH … #define mmXDMA_MSTR_CMD_URGENT_CNTL … #define mmXDMA_MSTR_MEM_URGENT_CNTL … #define mmXDMA_MSTR_PCIE_NACK_STATUS … #define mmXDMA_MSTR_MEM_NACK_STATUS … #define mmXDMA_MSTR_VSYNC_GSL_CHECK … #define mmXDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL … #define mmXDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND … #define mmXDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM … #define mmXDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT … #define mmXDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE … #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH … #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS … #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR … #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH … #define mmXDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE … #define mmXDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START … #define mmXDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS … #define mmXDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL … #define mmXDMA_SLV_CNTL … #define mmXDMA_SLV_MEM_CLIENT_CONFIG … #define mmXDMA_SLV_SLS_PITCH … #define mmXDMA_SLV_READ_URGENT_CNTL … #define mmXDMA_SLV_WRITE_URGENT_CNTL … #define mmXDMA_SLV_WB_RATE_CNTL … #define mmXDMA_SLV_READ_LATENCY_MINMAX … #define mmXDMA_SLV_READ_LATENCY_AVE … #define mmXDMA_SLV_PCIE_NACK_STATUS … #define mmXDMA_SLV_MEM_NACK_STATUS … #define mmXDMA_SLV_RDRET_BUF_STATUS … #define mmXDMA_SLV_READ_LATENCY_TIMER … #define mmXDMA_SLV_FLIP_PENDING … #define mmXDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL … #define mmXDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS … #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH … #endif /* DCE_11_0_D_H */
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