linux/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "nbio_v2_3.h"

#include "nbio/nbio_2_3_default.h"
#include "nbio/nbio_2_3_offset.h"
#include "nbio/nbio_2_3_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>
#include <linux/device.h>
#include <linux/pci.h>

#define smnPCIE_CONFIG_CNTL
#define smnCPM_CONTROL
#define smnPCIE_CNTL2
#define smnPCIE_LC_CNTL
#define smnPCIE_LC_CNTL3
#define smnPCIE_LC_CNTL6
#define smnPCIE_LC_CNTL7
#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2
#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
#define smnPSWUSP0_PCIE_LC_CNTL2
#define smnNBIF_MGCG_CTRL_LCLK

#define mmBIF_SDMA2_DOORBELL_RANGE
#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX
#define mmBIF_SDMA3_DOORBELL_RANGE
#define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX

#define mmBIF_MMSCH1_DOORBELL_RANGE
#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX

#define smnPCIE_LC_LINK_WIDTH_CNTL

#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK
#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK

static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
{}

static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{}

static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
{}

static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
{}

static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
					  bool use_doorbell, int doorbell_index,
					  int doorbell_size)
{}

static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
					 int doorbell_index, int instance)
{}

static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev,
					       bool enable)
{}

static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
							bool enable)
{}


static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev,
					bool use_doorbell, int doorbell_index)
{}

static void nbio_v2_3_ih_control(struct amdgpu_device *adev)
{}

static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
						       bool enable)
{}

static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
						      bool enable)
{}

static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev,
					    u64 *flags)
{}

static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{}

static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{}

static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)
{}

static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
{}

const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg =;

static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
{}

#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT
#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT
#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT

static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
				  bool enable)
{}

#ifdef CONFIG_PCIEASPM
static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
{}
#endif

static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
{}

static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
{}

static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev)
{}

static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
{}

#define MMIO_REG_HOLE_OFFSET

static void nbio_v2_3_set_reg_remap(struct amdgpu_device *adev)
{}

const struct amdgpu_nbio_funcs nbio_v2_3_funcs =;