/* SPDX-License-Identifier: GPL-2.0 */ /* * Imagination E5010 JPEG Encoder driver. * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * * Author: David Huang <[email protected]> * Author: Devarsh Thakkar <[email protected]> */ #ifndef _E5010_MMU_REGS_H #define _E5010_MMU_REGS_H #define MMU_MMU_DIR_BASE_ADDR_OFFSET … #define MMU_MMU_DIR_BASE_ADDR_STRIDE … #define MMU_MMU_DIR_BASE_ADDR_NO_ENTRIES … #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK … #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT … #define MMU_MMU_TILE_CFG_OFFSET … #define MMU_MMU_TILE_CFG_STRIDE … #define MMU_MMU_TILE_CFG_NO_ENTRIES … #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK … #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_SHIFT … #define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK … #define MMU_MMU_TILE_CFG_TILE_ENABLE_SHIFT … #define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK … #define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT … #define MMU_MMU_TILE_MIN_ADDR_OFFSET … #define MMU_MMU_TILE_MIN_ADDR_STRIDE … #define MMU_MMU_TILE_MIN_ADDR_NO_ENTRIES … #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK … #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_SHIFT … #define MMU_MMU_TILE_MAX_ADDR_OFFSET … #define MMU_MMU_TILE_MAX_ADDR_STRIDE … #define MMU_MMU_TILE_MAX_ADDR_NO_ENTRIES … #define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_MASK … #define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_SHIFT … #define MMU_MMU_CONTROL0_OFFSET … #define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_MASK … #define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_SHIFT … #define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_MASK … #define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_SHIFT … #define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_MASK … #define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_SHIFT … #define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_MASK … #define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_SHIFT … #define MMU_MMU_CONTROL1_OFFSET … #define MMU_MMU_CONTROL1_MMU_FLUSH_MASK … #define MMU_MMU_CONTROL1_MMU_FLUSH_SHIFT … #define MMU_MMU_CONTROL1_MMU_FLUSH_NO_REPS … #define MMU_MMU_CONTROL1_MMU_FLUSH_SIZE … #define MMU_MMU_CONTROL1_MMU_INVALDC_MASK … #define MMU_MMU_CONTROL1_MMU_INVALDC_SHIFT … #define MMU_MMU_CONTROL1_MMU_INVALDC_NO_REPS … #define MMU_MMU_CONTROL1_MMU_INVALDC_SIZE … #define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_MASK … #define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_SHIFT … #define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_MASK … #define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_SHIFT … #define MMU_MMU_CONTROL1_MMU_PAUSE_SET_MASK … #define MMU_MMU_CONTROL1_MMU_PAUSE_SET_SHIFT … #define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_MASK … #define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_SHIFT … #define MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK … #define MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT … #define MMU_MMU_BANK_INDEX_OFFSET … #define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_MASK … #define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SHIFT … #define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_NO_REPS … #define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SIZE … #define MMU_REQUEST_PRIORITY_ENABLE_OFFSET … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_MASK … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SHIFT … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_NO_REPS … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SIZE … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_MASK … #define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_SHIFT … #define MMU_REQUEST_LIMITED_THROUGHPUT_OFFSET … #define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_MASK … #define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_SHIFT … #define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_MASK … #define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_SHIFT … #define MMU_MMU_ADDRESS_CONTROL_OFFSET … #define MMU_MMU_ADDRESS_CONTROL_TRUSTED … #define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK … #define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT … #define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_MASK … #define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_SHIFT … #define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_MASK … #define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_SHIFT … #define MMU_MMU_CONFIG0_OFFSET … #define MMU_MMU_CONFIG0_NUM_REQUESTORS_MASK … #define MMU_MMU_CONFIG0_NUM_REQUESTORS_SHIFT … #define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_MASK … #define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_SHIFT … #define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_MASK … #define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_SHIFT … #define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_MASK … #define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_SHIFT … #define MMU_MMU_CONFIG0_MMU_SUPPORTED_MASK … #define MMU_MMU_CONFIG0_MMU_SUPPORTED_SHIFT … #define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_MASK … #define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_SHIFT … #define MMU_MMU_CONFIG0_NO_READ_REORDER_MASK … #define MMU_MMU_CONFIG0_NO_READ_REORDER_SHIFT … #define MMU_MMU_CONFIG0_TAGS_SUPPORTED_MASK … #define MMU_MMU_CONFIG0_TAGS_SUPPORTED_SHIFT … #define MMU_MMU_CONFIG1_OFFSET … #define MMU_MMU_CONFIG1_PAGE_SIZE_MASK … #define MMU_MMU_CONFIG1_PAGE_SIZE_SHIFT … #define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_MASK … #define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_SHIFT … #define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_MASK … #define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_SHIFT … #define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_MASK … #define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_SHIFT … #define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_MASK … #define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_SHIFT … #define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_MASK … #define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_SHIFT … #define MMU_MMU_STATUS0_OFFSET … #define MMU_MMU_STATUS0_MMU_PF_N_RW_MASK … #define MMU_MMU_STATUS0_MMU_PF_N_RW_SHIFT … #define MMU_MMU_STATUS0_MMU_FAULT_ADDR_MASK … #define MMU_MMU_STATUS0_MMU_FAULT_ADDR_SHIFT … #define MMU_MMU_STATUS1_OFFSET … #define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_MASK … #define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_SHIFT … #define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_MASK … #define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_SHIFT … #define MMU_MMU_STATUS1_MMU_FAULT_INDEX_MASK … #define MMU_MMU_STATUS1_MMU_FAULT_INDEX_SHIFT … #define MMU_MMU_STATUS1_MMU_FAULT_RNW_MASK … #define MMU_MMU_STATUS1_MMU_FAULT_RNW_SHIFT … #define MMU_MMU_MEM_REQ_OFFSET … #define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_MASK … #define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_SHIFT … #define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_MASK … #define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_SHIFT … #define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_MASK … #define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_SHIFT … #define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_MASK … #define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_SHIFT … #define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_MASK … #define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SHIFT … #define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_NO_REPS … #define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SIZE … #define MMU_MMU_FAULT_SELECT_OFFSET … #define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_MASK … #define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_SHIFT … #define MMU_PROTOCOL_FAULT_OFFSET … #define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_MASK … #define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_SHIFT … #define MMU_PROTOCOL_FAULT_FAULT_WRITE_MASK … #define MMU_PROTOCOL_FAULT_FAULT_WRITE_SHIFT … #define MMU_PROTOCOL_FAULT_FAULT_READ_MASK … #define MMU_PROTOCOL_FAULT_FAULT_READ_SHIFT … #define MMU_TOTAL_READ_REQ_OFFSET … #define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_MASK … #define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_SHIFT … #define MMU_TOTAL_WRITE_REQ_OFFSET … #define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_MASK … #define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_SHIFT … #define MMU_READS_LESS_64_REQ_OFFSET … #define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_MASK … #define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_SHIFT … #define MMU_WRITES_LESS_64_REQ_OFFSET … #define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_MASK … #define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_SHIFT … #define MMU_EXT_CMD_STALL_OFFSET … #define MMU_EXT_CMD_STALL_EXT_CMD_STALL_MASK … #define MMU_EXT_CMD_STALL_EXT_CMD_STALL_SHIFT … #define MMU_WRITE_REQ_STALL_OFFSET … #define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_MASK … #define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_SHIFT … #define MMU_MMU_MISS_STALL_OFFSET … #define MMU_MMU_MISS_STALL_MMU_MISS_STALL_MASK … #define MMU_MMU_MISS_STALL_MMU_MISS_STALL_SHIFT … #define MMU_ADDRESS_STALL_OFFSET … #define MMU_ADDRESS_STALL_ADDRESS_STALL_MASK … #define MMU_ADDRESS_STALL_ADDRESS_STALL_SHIFT … #define MMU_TAG_STALL_OFFSET … #define MMU_TAG_STALL_TAG_STALL_MASK … #define MMU_TAG_STALL_TAG_STALL_SHIFT … #define MMU_PEAK_READ_OUTSTANDING_OFFSET … #define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_MASK … #define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_SHIFT … #define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_MASK … #define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_SHIFT … #define MMU_AVERAGE_READ_LATENCY_OFFSET … #define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_MASK … #define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_SHIFT … #define MMU_STATISTICS_CONTROL_OFFSET … #define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_MASK … #define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_SHIFT … #define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_MASK … #define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_SHIFT … #define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_MASK … #define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_SHIFT … #define MMU_MMU_VERSION_OFFSET … #define MMU_MMU_VERSION_MMU_MAJOR_REV_MASK … #define MMU_MMU_VERSION_MMU_MAJOR_REV_SHIFT … #define MMU_MMU_VERSION_MMU_MINOR_REV_MASK … #define MMU_MMU_VERSION_MMU_MINOR_REV_SHIFT … #define MMU_MMU_VERSION_MMU_MAINT_REV_MASK … #define MMU_MMU_VERSION_MMU_MAINT_REV_SHIFT … #define MMU_BYTE_SIZE … #endif
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