/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2020-2024 Intel Corporation */ #ifndef __IVPU_HW_BTRS_LNL_REG_H__ #define __IVPU_HW_BTRS_LNL_REG_H__ #include <linux/bits.h> #define VPU_HW_BTRS_LNL_INTERRUPT_STAT … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK … #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK … #define VPU_HW_BTRS_LNL_LOCAL_INT_MASK … #define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK … #define VPU_HW_BTRS_LNL_HM_ATS … #define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 … #define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 … #define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR … #define VPU_HW_BTRS_LNL_CFI0_ERR_LOG … #define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR … #define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS … #define VPU_HW_BTRS_LNL_CFI1_ERR_LOG … #define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR … #define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH … #define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK … #define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK … #define VPU_HW_BTRS_LNL_WP_REQ_CMD … #define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK … #define VPU_HW_BTRS_LNL_PLL_FREQ … #define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK … #define VPU_HW_BTRS_LNL_TILE_FUSE … #define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK … #define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS … #define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK … #define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK … #define VPU_HW_BTRS_LNL_IP_RESET … #define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK … #define VPU_HW_BTRS_LNL_D0I3_CONTROL … #define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK … #define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK … #define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET … #define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE … #define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE … #define VPU_HW_BTRS_LNL_FMIN_FUSE … #define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK … #define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK … #define VPU_HW_BTRS_LNL_FMAX_FUSE … #define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK … #endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
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