/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_MSR_INDEX_H #define _ASM_X86_MSR_INDEX_H #include <linux/bits.h> /* CPU model specific register (MSR) numbers. */ /* x86-64 specific MSRs */ #define MSR_EFER … #define MSR_STAR … #define MSR_LSTAR … #define MSR_CSTAR … #define MSR_SYSCALL_MASK … #define MSR_FS_BASE … #define MSR_GS_BASE … #define MSR_KERNEL_GS_BASE … #define MSR_TSC_AUX … /* EFER bits: */ #define _EFER_SCE … #define _EFER_LME … #define _EFER_LMA … #define _EFER_NX … #define _EFER_SVME … #define _EFER_LMSLE … #define _EFER_FFXSR … #define _EFER_AUTOIBRS … #define EFER_SCE … #define EFER_LME … #define EFER_LMA … #define EFER_NX … #define EFER_SVME … #define EFER_LMSLE … #define EFER_FFXSR … #define EFER_AUTOIBRS … /* FRED MSRs */ #define MSR_IA32_FRED_RSP0 … #define MSR_IA32_FRED_RSP1 … #define MSR_IA32_FRED_RSP2 … #define MSR_IA32_FRED_RSP3 … #define MSR_IA32_FRED_STKLVLS … #define MSR_IA32_FRED_SSP0 … #define MSR_IA32_FRED_SSP1 … #define MSR_IA32_FRED_SSP2 … #define MSR_IA32_FRED_SSP3 … #define MSR_IA32_FRED_CONFIG … /* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL … #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT … #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT … #define MSR_IA32_SPEC_CTRL … #define SPEC_CTRL_IBRS … #define SPEC_CTRL_STIBP_SHIFT … #define SPEC_CTRL_STIBP … #define SPEC_CTRL_SSBD_SHIFT … #define SPEC_CTRL_SSBD … #define SPEC_CTRL_RRSBA_DIS_S_SHIFT … #define SPEC_CTRL_RRSBA_DIS_S … #define SPEC_CTRL_BHI_DIS_S_SHIFT … #define SPEC_CTRL_BHI_DIS_S … /* A mask for bits which the kernel toggles when controlling mitigations */ #define SPEC_CTRL_MITIGATIONS_MASK … #define MSR_IA32_PRED_CMD … #define PRED_CMD_IBPB … #define PRED_CMD_SBPB … #define MSR_PPIN_CTL … #define MSR_PPIN … #define MSR_IA32_PERFCTR0 … #define MSR_IA32_PERFCTR1 … #define MSR_FSB_FREQ … #define MSR_PLATFORM_INFO … #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT … #define MSR_PLATFORM_INFO_CPUID_FAULT … #define MSR_IA32_UMWAIT_CONTROL … #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE … #define MSR_IA32_UMWAIT_CONTROL_RESERVED … /* * The time field is bit[31:2], but representing a 32bit value with * bit[1:0] zero. */ #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK … /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ #define MSR_IA32_CORE_CAPS … #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT … #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS … #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT … #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT … #define MSR_PKG_CST_CONFIG_CONTROL … #define NHM_C3_AUTO_DEMOTE … #define NHM_C1_AUTO_DEMOTE … #define ATM_LNC_C6_AUTO_DEMOTE … #define SNB_C3_AUTO_UNDEMOTE … #define SNB_C1_AUTO_UNDEMOTE … #define MSR_MTRRcap … #define MSR_IA32_ARCH_CAPABILITIES … #define ARCH_CAP_RDCL_NO … #define ARCH_CAP_IBRS_ALL … #define ARCH_CAP_RSBA … #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH … #define ARCH_CAP_SSB_NO … #define ARCH_CAP_MDS_NO … #define ARCH_CAP_PSCHANGE_MC_NO … #define ARCH_CAP_TSX_CTRL_MSR … #define ARCH_CAP_TAA_NO … #define ARCH_CAP_SBDR_SSDP_NO … #define ARCH_CAP_FBSDP_NO … #define ARCH_CAP_PSDP_NO … #define ARCH_CAP_FB_CLEAR … #define ARCH_CAP_FB_CLEAR_CTRL … #define ARCH_CAP_RRSBA … #define ARCH_CAP_BHI_NO … #define ARCH_CAP_XAPIC_DISABLE … #define ARCH_CAP_PBRSB_NO … #define ARCH_CAP_GDS_CTRL … #define ARCH_CAP_GDS_NO … #define ARCH_CAP_RFDS_NO … #define ARCH_CAP_RFDS_CLEAR … #define MSR_IA32_FLUSH_CMD … #define L1D_FLUSH … #define MSR_IA32_BBL_CR_CTL … #define MSR_IA32_BBL_CR_CTL3 … #define MSR_IA32_TSX_CTRL … #define TSX_CTRL_RTM_DISABLE … #define TSX_CTRL_CPUID_CLEAR … #define MSR_IA32_MCU_OPT_CTRL … #define RNGDS_MITG_DIS … #define RTM_ALLOW … #define FB_CLEAR_DIS … #define GDS_MITG_DIS … #define GDS_MITG_LOCKED … #define MSR_IA32_SYSENTER_CS … #define MSR_IA32_SYSENTER_ESP … #define MSR_IA32_SYSENTER_EIP … #define MSR_IA32_MCG_CAP … #define MSR_IA32_MCG_STATUS … #define MSR_IA32_MCG_CTL … #define MSR_ERROR_CONTROL … #define MSR_IA32_MCG_EXT_CTL … #define MSR_OFFCORE_RSP_0 … #define MSR_OFFCORE_RSP_1 … #define MSR_TURBO_RATIO_LIMIT … #define MSR_TURBO_RATIO_LIMIT1 … #define MSR_TURBO_RATIO_LIMIT2 … #define MSR_SNOOP_RSP_0 … #define MSR_SNOOP_RSP_1 … #define MSR_LBR_SELECT … #define MSR_LBR_TOS … #define MSR_IA32_POWER_CTL … #define MSR_IA32_POWER_CTL_BIT_EE … /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ #define MSR_INTEGRITY_CAPS … #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT … #define MSR_INTEGRITY_CAPS_ARRAY_BIST … #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT … #define MSR_INTEGRITY_CAPS_PERIODIC_BIST … #define MSR_INTEGRITY_CAPS_SAF_GEN_MASK … #define MSR_LBR_NHM_FROM … #define MSR_LBR_NHM_TO … #define MSR_LBR_CORE_FROM … #define MSR_LBR_CORE_TO … #define MSR_LBR_INFO_0 … #define LBR_INFO_MISPRED … #define LBR_INFO_IN_TX … #define LBR_INFO_ABORT … #define LBR_INFO_CYC_CNT_VALID … #define LBR_INFO_CYCLES … #define LBR_INFO_BR_TYPE_OFFSET … #define LBR_INFO_BR_TYPE … #define LBR_INFO_BR_CNTR_OFFSET … #define LBR_INFO_BR_CNTR_NUM … #define LBR_INFO_BR_CNTR_BITS … #define LBR_INFO_BR_CNTR_MASK … #define LBR_INFO_BR_CNTR_FULL_MASK … #define MSR_ARCH_LBR_CTL … #define ARCH_LBR_CTL_LBREN … #define ARCH_LBR_CTL_CPL_OFFSET … #define ARCH_LBR_CTL_CPL … #define ARCH_LBR_CTL_STACK_OFFSET … #define ARCH_LBR_CTL_STACK … #define ARCH_LBR_CTL_FILTER_OFFSET … #define ARCH_LBR_CTL_FILTER … #define MSR_ARCH_LBR_DEPTH … #define MSR_ARCH_LBR_FROM_0 … #define MSR_ARCH_LBR_TO_0 … #define MSR_ARCH_LBR_INFO_0 … #define MSR_IA32_PEBS_ENABLE … #define MSR_PEBS_DATA_CFG … #define MSR_IA32_DS_AREA … #define MSR_IA32_PERF_CAPABILITIES … #define PERF_CAP_METRICS_IDX … #define PERF_CAP_PT_IDX … #define MSR_PEBS_LD_LAT_THRESHOLD … #define PERF_CAP_PEBS_TRAP … #define PERF_CAP_ARCH_REG … #define PERF_CAP_PEBS_FORMAT … #define PERF_CAP_PEBS_BASELINE … #define PERF_CAP_PEBS_MASK … #define MSR_IA32_RTIT_CTL … #define RTIT_CTL_TRACEEN … #define RTIT_CTL_CYCLEACC … #define RTIT_CTL_OS … #define RTIT_CTL_USR … #define RTIT_CTL_PWR_EVT_EN … #define RTIT_CTL_FUP_ON_PTW … #define RTIT_CTL_FABRIC_EN … #define RTIT_CTL_CR3EN … #define RTIT_CTL_TOPA … #define RTIT_CTL_MTC_EN … #define RTIT_CTL_TSC_EN … #define RTIT_CTL_DISRETC … #define RTIT_CTL_PTW_EN … #define RTIT_CTL_BRANCH_EN … #define RTIT_CTL_EVENT_EN … #define RTIT_CTL_NOTNT … #define RTIT_CTL_MTC_RANGE_OFFSET … #define RTIT_CTL_MTC_RANGE … #define RTIT_CTL_CYC_THRESH_OFFSET … #define RTIT_CTL_CYC_THRESH … #define RTIT_CTL_PSB_FREQ_OFFSET … #define RTIT_CTL_PSB_FREQ … #define RTIT_CTL_ADDR0_OFFSET … #define RTIT_CTL_ADDR0 … #define RTIT_CTL_ADDR1_OFFSET … #define RTIT_CTL_ADDR1 … #define RTIT_CTL_ADDR2_OFFSET … #define RTIT_CTL_ADDR2 … #define RTIT_CTL_ADDR3_OFFSET … #define RTIT_CTL_ADDR3 … #define MSR_IA32_RTIT_STATUS … #define RTIT_STATUS_FILTEREN … #define RTIT_STATUS_CONTEXTEN … #define RTIT_STATUS_TRIGGEREN … #define RTIT_STATUS_BUFFOVF … #define RTIT_STATUS_ERROR … #define RTIT_STATUS_STOPPED … #define RTIT_STATUS_BYTECNT_OFFSET … #define RTIT_STATUS_BYTECNT … #define MSR_IA32_RTIT_ADDR0_A … #define MSR_IA32_RTIT_ADDR0_B … #define MSR_IA32_RTIT_ADDR1_A … #define MSR_IA32_RTIT_ADDR1_B … #define MSR_IA32_RTIT_ADDR2_A … #define MSR_IA32_RTIT_ADDR2_B … #define MSR_IA32_RTIT_ADDR3_A … #define MSR_IA32_RTIT_ADDR3_B … #define MSR_IA32_RTIT_CR3_MATCH … #define MSR_IA32_RTIT_OUTPUT_BASE … #define MSR_IA32_RTIT_OUTPUT_MASK … #define MSR_MTRRfix64K_00000 … #define MSR_MTRRfix16K_80000 … #define MSR_MTRRfix16K_A0000 … #define MSR_MTRRfix4K_C0000 … #define MSR_MTRRfix4K_C8000 … #define MSR_MTRRfix4K_D0000 … #define MSR_MTRRfix4K_D8000 … #define MSR_MTRRfix4K_E0000 … #define MSR_MTRRfix4K_E8000 … #define MSR_MTRRfix4K_F0000 … #define MSR_MTRRfix4K_F8000 … #define MSR_MTRRdefType … #define MSR_IA32_CR_PAT … #define MSR_IA32_DEBUGCTLMSR … #define MSR_IA32_LASTBRANCHFROMIP … #define MSR_IA32_LASTBRANCHTOIP … #define MSR_IA32_LASTINTFROMIP … #define MSR_IA32_LASTINTTOIP … #define MSR_IA32_PASID … #define MSR_IA32_PASID_VALID … /* DEBUGCTLMSR bits (others vary by model): */ #define DEBUGCTLMSR_LBR … #define DEBUGCTLMSR_BTF_SHIFT … #define DEBUGCTLMSR_BTF … #define DEBUGCTLMSR_BUS_LOCK_DETECT … #define DEBUGCTLMSR_TR … #define DEBUGCTLMSR_BTS … #define DEBUGCTLMSR_BTINT … #define DEBUGCTLMSR_BTS_OFF_OS … #define DEBUGCTLMSR_BTS_OFF_USR … #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI … #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI … #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT … #define DEBUGCTLMSR_FREEZE_IN_SMM … #define MSR_PEBS_FRONTEND … #define MSR_IA32_MC0_CTL … #define MSR_IA32_MC0_STATUS … #define MSR_IA32_MC0_ADDR … #define MSR_IA32_MC0_MISC … /* C-state Residency Counters */ #define MSR_PKG_C3_RESIDENCY … #define MSR_PKG_C6_RESIDENCY … #define MSR_ATOM_PKG_C6_RESIDENCY … #define MSR_PKG_C7_RESIDENCY … #define MSR_CORE_C3_RESIDENCY … #define MSR_CORE_C6_RESIDENCY … #define MSR_CORE_C7_RESIDENCY … #define MSR_KNL_CORE_C6_RESIDENCY … #define MSR_PKG_C2_RESIDENCY … #define MSR_PKG_C8_RESIDENCY … #define MSR_PKG_C9_RESIDENCY … #define MSR_PKG_C10_RESIDENCY … /* Interrupt Response Limit */ #define MSR_PKGC3_IRTL … #define MSR_PKGC6_IRTL … #define MSR_PKGC7_IRTL … #define MSR_PKGC8_IRTL … #define MSR_PKGC9_IRTL … #define MSR_PKGC10_IRTL … /* Run Time Average Power Limiting (RAPL) Interface */ #define MSR_VR_CURRENT_CONFIG … #define MSR_RAPL_POWER_UNIT … #define MSR_PKG_POWER_LIMIT … #define MSR_PKG_ENERGY_STATUS … #define MSR_PKG_PERF_STATUS … #define MSR_PKG_POWER_INFO … #define MSR_DRAM_POWER_LIMIT … #define MSR_DRAM_ENERGY_STATUS … #define MSR_DRAM_PERF_STATUS … #define MSR_DRAM_POWER_INFO … #define MSR_PP0_POWER_LIMIT … #define MSR_PP0_ENERGY_STATUS … #define MSR_PP0_POLICY … #define MSR_PP0_PERF_STATUS … #define MSR_PP1_POWER_LIMIT … #define MSR_PP1_ENERGY_STATUS … #define MSR_PP1_POLICY … #define MSR_AMD_RAPL_POWER_UNIT … #define MSR_AMD_CORE_ENERGY_STATUS … #define MSR_AMD_PKG_ENERGY_STATUS … /* Config TDP MSRs */ #define MSR_CONFIG_TDP_NOMINAL … #define MSR_CONFIG_TDP_LEVEL_1 … #define MSR_CONFIG_TDP_LEVEL_2 … #define MSR_CONFIG_TDP_CONTROL … #define MSR_TURBO_ACTIVATION_RATIO … #define MSR_PLATFORM_ENERGY_STATUS … #define MSR_SECONDARY_TURBO_RATIO_LIMIT … #define MSR_PKG_WEIGHTED_CORE_C0_RES … #define MSR_PKG_ANY_CORE_C0_RES … #define MSR_PKG_ANY_GFXE_C0_RES … #define MSR_PKG_BOTH_CORE_GFXE_C0_RES … #define MSR_CORE_C1_RES … #define MSR_MODULE_C6_RES_MS … #define MSR_CC6_DEMOTION_POLICY_CONFIG … #define MSR_MC6_DEMOTION_POLICY_CONFIG … #define MSR_ATOM_CORE_RATIOS … #define MSR_ATOM_CORE_VIDS … #define MSR_ATOM_CORE_TURBO_RATIOS … #define MSR_ATOM_CORE_TURBO_VIDS … #define MSR_CORE_PERF_LIMIT_REASONS … #define MSR_GFX_PERF_LIMIT_REASONS … #define MSR_RING_PERF_LIMIT_REASONS … /* Control-flow Enforcement Technology MSRs */ #define MSR_IA32_U_CET … #define MSR_IA32_S_CET … #define CET_SHSTK_EN … #define CET_WRSS_EN … #define CET_ENDBR_EN … #define CET_LEG_IW_EN … #define CET_NO_TRACK_EN … #define CET_SUPPRESS_DISABLE … #define CET_RESERVED … #define CET_SUPPRESS … #define CET_WAIT_ENDBR … #define MSR_IA32_PL0_SSP … #define MSR_IA32_PL1_SSP … #define MSR_IA32_PL2_SSP … #define MSR_IA32_PL3_SSP … #define MSR_IA32_INT_SSP_TAB … /* Hardware P state interface */ #define MSR_PPERF … #define MSR_PERF_LIMIT_REASONS … #define MSR_PM_ENABLE … #define MSR_HWP_CAPABILITIES … #define MSR_HWP_REQUEST_PKG … #define MSR_HWP_INTERRUPT … #define MSR_HWP_REQUEST … #define MSR_HWP_STATUS … /* CPUID.6.EAX */ #define HWP_BASE_BIT … #define HWP_NOTIFICATIONS_BIT … #define HWP_ACTIVITY_WINDOW_BIT … #define HWP_ENERGY_PERF_PREFERENCE_BIT … #define HWP_PACKAGE_LEVEL_REQUEST_BIT … /* IA32_HWP_CAPABILITIES */ #define HWP_HIGHEST_PERF(x) … #define HWP_GUARANTEED_PERF(x) … #define HWP_MOSTEFFICIENT_PERF(x) … #define HWP_LOWEST_PERF(x) … /* IA32_HWP_REQUEST */ #define HWP_MIN_PERF(x) … #define HWP_MAX_PERF(x) … #define HWP_DESIRED_PERF(x) … #define HWP_ENERGY_PERF_PREFERENCE(x) … #define HWP_EPP_PERFORMANCE … #define HWP_EPP_BALANCE_PERFORMANCE … #define HWP_EPP_BALANCE_POWERSAVE … #define HWP_EPP_POWERSAVE … #define HWP_ACTIVITY_WINDOW(x) … #define HWP_PACKAGE_CONTROL(x) … /* IA32_HWP_STATUS */ #define HWP_GUARANTEED_CHANGE(x) … #define HWP_EXCURSION_TO_MINIMUM(x) … /* IA32_HWP_INTERRUPT */ #define HWP_CHANGE_TO_GUARANTEED_INT(x) … #define HWP_EXCURSION_TO_MINIMUM_INT(x) … #define MSR_AMD64_MC0_MASK … #define MSR_IA32_MCx_CTL(x) … #define MSR_IA32_MCx_STATUS(x) … #define MSR_IA32_MCx_ADDR(x) … #define MSR_IA32_MCx_MISC(x) … #define MSR_AMD64_MCx_MASK(x) … /* These are consecutive and not in the normal 4er MCE bank block */ #define MSR_IA32_MC0_CTL2 … #define MSR_IA32_MCx_CTL2(x) … #define MSR_P6_PERFCTR0 … #define MSR_P6_PERFCTR1 … #define MSR_P6_EVNTSEL0 … #define MSR_P6_EVNTSEL1 … #define MSR_KNC_PERFCTR0 … #define MSR_KNC_PERFCTR1 … #define MSR_KNC_EVNTSEL0 … #define MSR_KNC_EVNTSEL1 … /* Alternative perfctr range with full access. */ #define MSR_IA32_PMC0 … /* Auto-reload via MSR instead of DS area */ #define MSR_RELOAD_PMC0 … #define MSR_RELOAD_FIXED_CTR0 … /* V6 PMON MSR range */ #define MSR_IA32_PMC_V6_GP0_CTR … #define MSR_IA32_PMC_V6_GP0_CFG_A … #define MSR_IA32_PMC_V6_FX0_CTR … #define MSR_IA32_PMC_V6_STEP … /* KeyID partitioning between MKTME and TDX */ #define MSR_IA32_MKTME_KEYID_PARTITIONING … /* * AMD64 MSRs. Not complete. See the architecture manual for a more * complete list. */ #define MSR_AMD64_PATCH_LEVEL … #define MSR_AMD64_TSC_RATIO … #define MSR_AMD64_NB_CFG … #define MSR_AMD64_PATCH_LOADER … #define MSR_AMD_PERF_CTL … #define MSR_AMD_PERF_STATUS … #define MSR_AMD_PSTATE_DEF_BASE … #define MSR_AMD64_OSVW_ID_LENGTH … #define MSR_AMD64_OSVW_STATUS … #define MSR_AMD_PPIN_CTL … #define MSR_AMD_PPIN … #define MSR_AMD64_CPUID_FN_1 … #define MSR_AMD64_LS_CFG … #define MSR_AMD64_DC_CFG … #define MSR_AMD64_TW_CFG … #define MSR_AMD64_DE_CFG … #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT … #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE … #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT … #define MSR_AMD64_BU_CFG2 … #define MSR_AMD64_IBSFETCHCTL … #define MSR_AMD64_IBSFETCHLINAD … #define MSR_AMD64_IBSFETCHPHYSAD … #define MSR_AMD64_IBSFETCH_REG_COUNT … #define MSR_AMD64_IBSFETCH_REG_MASK … #define MSR_AMD64_IBSOPCTL … #define MSR_AMD64_IBSOPRIP … #define MSR_AMD64_IBSOPDATA … #define MSR_AMD64_IBSOPDATA2 … #define MSR_AMD64_IBSOPDATA3 … #define MSR_AMD64_IBSDCLINAD … #define MSR_AMD64_IBSDCPHYSAD … #define MSR_AMD64_IBSOP_REG_COUNT … #define MSR_AMD64_IBSOP_REG_MASK … #define MSR_AMD64_IBSCTL … #define MSR_AMD64_IBSBRTARGET … #define MSR_AMD64_ICIBSEXTDCTL … #define MSR_AMD64_IBSOPDATA4 … #define MSR_AMD64_IBS_REG_COUNT_MAX … #define MSR_AMD64_SVM_AVIC_DOORBELL … #define MSR_AMD64_VM_PAGE_FLUSH … #define MSR_AMD64_SEV_ES_GHCB … #define MSR_AMD64_SEV … #define MSR_AMD64_SEV_ENABLED_BIT … #define MSR_AMD64_SEV_ENABLED … #define MSR_AMD64_SEV_ES_ENABLED_BIT … #define MSR_AMD64_SEV_ES_ENABLED … #define MSR_AMD64_SEV_SNP_ENABLED_BIT … #define MSR_AMD64_SEV_SNP_ENABLED … #define MSR_AMD64_SNP_VTOM_BIT … #define MSR_AMD64_SNP_VTOM … #define MSR_AMD64_SNP_REFLECT_VC_BIT … #define MSR_AMD64_SNP_REFLECT_VC … #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT … #define MSR_AMD64_SNP_RESTRICTED_INJ … #define MSR_AMD64_SNP_ALT_INJ_BIT … #define MSR_AMD64_SNP_ALT_INJ … #define MSR_AMD64_SNP_DEBUG_SWAP_BIT … #define MSR_AMD64_SNP_DEBUG_SWAP … #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT … #define MSR_AMD64_SNP_PREVENT_HOST_IBS … #define MSR_AMD64_SNP_BTB_ISOLATION_BIT … #define MSR_AMD64_SNP_BTB_ISOLATION … #define MSR_AMD64_SNP_VMPL_SSS_BIT … #define MSR_AMD64_SNP_VMPL_SSS … #define MSR_AMD64_SNP_SECURE_TSC_BIT … #define MSR_AMD64_SNP_SECURE_TSC … #define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT … #define MSR_AMD64_SNP_VMGEXIT_PARAM … #define MSR_AMD64_SNP_RESERVED_BIT13 … #define MSR_AMD64_SNP_IBS_VIRT_BIT … #define MSR_AMD64_SNP_IBS_VIRT … #define MSR_AMD64_SNP_RESERVED_BIT15 … #define MSR_AMD64_SNP_VMSA_REG_PROT_BIT … #define MSR_AMD64_SNP_VMSA_REG_PROT … #define MSR_AMD64_SNP_SMT_PROT_BIT … #define MSR_AMD64_SNP_SMT_PROT … #define MSR_AMD64_SNP_RESV_BIT … #define MSR_AMD64_SNP_RESERVED_MASK … #define MSR_AMD64_VIRT_SPEC_CTRL … #define MSR_AMD64_RMP_BASE … #define MSR_AMD64_RMP_END … #define MSR_SVSM_CAA … /* AMD Collaborative Processor Performance Control MSRs */ #define MSR_AMD_CPPC_CAP1 … #define MSR_AMD_CPPC_ENABLE … #define MSR_AMD_CPPC_CAP2 … #define MSR_AMD_CPPC_REQ … #define MSR_AMD_CPPC_STATUS … #define AMD_CPPC_LOWEST_PERF(x) … #define AMD_CPPC_LOWNONLIN_PERF(x) … #define AMD_CPPC_NOMINAL_PERF(x) … #define AMD_CPPC_HIGHEST_PERF(x) … #define AMD_CPPC_MAX_PERF(x) … #define AMD_CPPC_MIN_PERF(x) … #define AMD_CPPC_DES_PERF(x) … #define AMD_CPPC_ENERGY_PERF_PREF(x) … /* AMD Performance Counter Global Status and Control MSRs */ #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS … #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL … #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR … /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT … /* Zen4 */ #define MSR_ZEN4_BP_CFG … #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT … /* Fam 19h MSRs */ #define MSR_F19H_UMC_PERF_CTL … #define MSR_F19H_UMC_PERF_CTR … /* Zen 2 */ #define MSR_ZEN2_SPECTRAL_CHICKEN … #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT … /* Fam 17h MSRs */ #define MSR_F17H_IRPERF … /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL … #define MSR_F16H_L2I_PERF_CTR … #define MSR_F16H_DR1_ADDR_MASK … #define MSR_F16H_DR2_ADDR_MASK … #define MSR_F16H_DR3_ADDR_MASK … #define MSR_F16H_DR0_ADDR_MASK … /* Fam 15h MSRs */ #define MSR_F15H_CU_PWR_ACCUMULATOR … #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR … #define MSR_F15H_PERF_CTL … #define MSR_F15H_PERF_CTL0 … #define MSR_F15H_PERF_CTL1 … #define MSR_F15H_PERF_CTL2 … #define MSR_F15H_PERF_CTL3 … #define MSR_F15H_PERF_CTL4 … #define MSR_F15H_PERF_CTL5 … #define MSR_F15H_PERF_CTR … #define MSR_F15H_PERF_CTR0 … #define MSR_F15H_PERF_CTR1 … #define MSR_F15H_PERF_CTR2 … #define MSR_F15H_PERF_CTR3 … #define MSR_F15H_PERF_CTR4 … #define MSR_F15H_PERF_CTR5 … #define MSR_F15H_NB_PERF_CTL … #define MSR_F15H_NB_PERF_CTR … #define MSR_F15H_PTSC … #define MSR_F15H_IC_CFG … #define MSR_F15H_EX_CFG … /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE … #define FAM10H_MMIO_CONF_ENABLE … #define FAM10H_MMIO_CONF_BUSRANGE_MASK … #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT … #define FAM10H_MMIO_CONF_BASE_MASK … #define FAM10H_MMIO_CONF_BASE_SHIFT … #define MSR_FAM10H_NODE_ID … /* K8 MSRs */ #define MSR_K8_TOP_MEM1 … #define MSR_K8_TOP_MEM2 … #define MSR_AMD64_SYSCFG … #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT … #define MSR_AMD64_SYSCFG_MEM_ENCRYPT … #define MSR_AMD64_SYSCFG_SNP_EN_BIT … #define MSR_AMD64_SYSCFG_SNP_EN … #define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT … #define MSR_AMD64_SYSCFG_SNP_VMPL_EN … #define MSR_AMD64_SYSCFG_MFDM_BIT … #define MSR_AMD64_SYSCFG_MFDM … #define MSR_K8_INT_PENDING_MSG … /* C1E active bits in int pending message */ #define K8_INTP_C1E_ACTIVE_MASK … #define MSR_K8_TSEG_ADDR … #define MSR_K8_TSEG_MASK … #define K8_MTRRFIXRANGE_DRAM_ENABLE … #define K8_MTRRFIXRANGE_DRAM_MODIFY … #define K8_MTRR_RDMEM_WRMEM_MASK … /* K7 MSRs */ #define MSR_K7_EVNTSEL0 … #define MSR_K7_PERFCTR0 … #define MSR_K7_EVNTSEL1 … #define MSR_K7_PERFCTR1 … #define MSR_K7_EVNTSEL2 … #define MSR_K7_PERFCTR2 … #define MSR_K7_EVNTSEL3 … #define MSR_K7_PERFCTR3 … #define MSR_K7_CLK_CTL … #define MSR_K7_HWCR … #define MSR_K7_HWCR_SMMLOCK_BIT … #define MSR_K7_HWCR_SMMLOCK … #define MSR_K7_HWCR_IRPERF_EN_BIT … #define MSR_K7_HWCR_IRPERF_EN … #define MSR_K7_FID_VID_CTL … #define MSR_K7_FID_VID_STATUS … #define MSR_K7_HWCR_CPB_DIS_BIT … #define MSR_K7_HWCR_CPB_DIS … /* K6 MSRs */ #define MSR_K6_WHCR … #define MSR_K6_UWCCR … #define MSR_K6_EPMR … #define MSR_K6_PSOR … #define MSR_K6_PFIR … /* Centaur-Hauls/IDT defined MSRs. */ #define MSR_IDT_FCR1 … #define MSR_IDT_FCR2 … #define MSR_IDT_FCR3 … #define MSR_IDT_FCR4 … #define MSR_IDT_MCR0 … #define MSR_IDT_MCR1 … #define MSR_IDT_MCR2 … #define MSR_IDT_MCR3 … #define MSR_IDT_MCR4 … #define MSR_IDT_MCR5 … #define MSR_IDT_MCR6 … #define MSR_IDT_MCR7 … #define MSR_IDT_MCR_CTRL … /* VIA Cyrix defined MSRs*/ #define MSR_VIA_FCR … #define MSR_VIA_LONGHAUL … #define MSR_VIA_RNG … #define MSR_VIA_BCR2 … /* Transmeta defined MSRs */ #define MSR_TMTA_LONGRUN_CTRL … #define MSR_TMTA_LONGRUN_FLAGS … #define MSR_TMTA_LRTI_READOUT … #define MSR_TMTA_LRTI_VOLT_MHZ … /* Intel defined MSRs. */ #define MSR_IA32_P5_MC_ADDR … #define MSR_IA32_P5_MC_TYPE … #define MSR_IA32_TSC … #define MSR_IA32_PLATFORM_ID … #define MSR_IA32_EBL_CR_POWERON … #define MSR_EBC_FREQUENCY_ID … #define MSR_SMI_COUNT … /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ #define MSR_IA32_FEAT_CTL … #define FEAT_CTL_LOCKED … #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX … #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX … #define FEAT_CTL_SGX_LC_ENABLED … #define FEAT_CTL_SGX_ENABLED … #define FEAT_CTL_LMCE_ENABLED … #define MSR_IA32_TSC_ADJUST … #define MSR_IA32_BNDCFGS … #define MSR_IA32_BNDCFGS_RSVD … #define MSR_IA32_XFD … #define MSR_IA32_XFD_ERR … #define MSR_IA32_XSS … #define MSR_IA32_APICBASE … #define MSR_IA32_APICBASE_BSP … #define MSR_IA32_APICBASE_ENABLE … #define MSR_IA32_APICBASE_BASE … #define MSR_IA32_UCODE_WRITE … #define MSR_IA32_UCODE_REV … /* Intel SGX Launch Enclave Public Key Hash MSRs */ #define MSR_IA32_SGXLEPUBKEYHASH0 … #define MSR_IA32_SGXLEPUBKEYHASH1 … #define MSR_IA32_SGXLEPUBKEYHASH2 … #define MSR_IA32_SGXLEPUBKEYHASH3 … #define MSR_IA32_SMM_MONITOR_CTL … #define MSR_IA32_SMBASE … #define MSR_IA32_PERF_STATUS … #define MSR_IA32_PERF_CTL … #define INTEL_PERF_CTL_MASK … /* AMD Branch Sampling configuration */ #define MSR_AMD_DBG_EXTN_CFG … #define MSR_AMD_SAMP_BR_FROM … #define DBG_EXTN_CFG_LBRV2EN … #define MSR_IA32_MPERF … #define MSR_IA32_APERF … #define MSR_IA32_THERM_CONTROL … #define MSR_IA32_THERM_INTERRUPT … #define THERM_INT_HIGH_ENABLE … #define THERM_INT_LOW_ENABLE … #define THERM_INT_PLN_ENABLE … #define MSR_IA32_THERM_STATUS … #define THERM_STATUS_PROCHOT … #define THERM_STATUS_POWER_LIMIT … #define MSR_THERM2_CTL … #define MSR_THERM2_CTL_TM_SELECT … #define MSR_IA32_MISC_ENABLE … #define MSR_IA32_TEMPERATURE_TARGET … #define MSR_MISC_FEATURE_CONTROL … #define MSR_MISC_PWR_MGMT … #define MSR_IA32_ENERGY_PERF_BIAS … #define ENERGY_PERF_BIAS_PERFORMANCE … #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE … #define ENERGY_PERF_BIAS_NORMAL … #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE … #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE … #define ENERGY_PERF_BIAS_POWERSAVE … #define MSR_IA32_PACKAGE_THERM_STATUS … #define PACKAGE_THERM_STATUS_PROCHOT … #define PACKAGE_THERM_STATUS_POWER_LIMIT … #define PACKAGE_THERM_STATUS_HFI_UPDATED … #define MSR_IA32_PACKAGE_THERM_INTERRUPT … #define PACKAGE_THERM_INT_HIGH_ENABLE … #define PACKAGE_THERM_INT_LOW_ENABLE … #define PACKAGE_THERM_INT_PLN_ENABLE … #define PACKAGE_THERM_INT_HFI_ENABLE … /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE … #define THERM_SHIFT_THRESHOLD0 … #define THERM_MASK_THRESHOLD0 … #define THERM_INT_THRESHOLD1_ENABLE … #define THERM_SHIFT_THRESHOLD1 … #define THERM_MASK_THRESHOLD1 … #define THERM_STATUS_THRESHOLD0 … #define THERM_LOG_THRESHOLD0 … #define THERM_STATUS_THRESHOLD1 … #define THERM_LOG_THRESHOLD1 … /* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT … #define MSR_IA32_MISC_ENABLE_FAST_STRING … #define MSR_IA32_MISC_ENABLE_TCC_BIT … #define MSR_IA32_MISC_ENABLE_TCC … #define MSR_IA32_MISC_ENABLE_EMON_BIT … #define MSR_IA32_MISC_ENABLE_EMON … #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT … #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL … #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT … #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL … #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT … #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP … #define MSR_IA32_MISC_ENABLE_MWAIT_BIT … #define MSR_IA32_MISC_ENABLE_MWAIT … #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT … #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID … #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE … #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_XD_DISABLE … /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT … #define MSR_IA32_MISC_ENABLE_X87_COMPAT … #define MSR_IA32_MISC_ENABLE_TM1_BIT … #define MSR_IA32_MISC_ENABLE_TM1 … #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE … #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE … #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT … #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK … #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE … #define MSR_IA32_MISC_ENABLE_FERR_BIT … #define MSR_IA32_MISC_ENABLE_FERR … #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT … #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX … #define MSR_IA32_MISC_ENABLE_TM2_BIT … #define MSR_IA32_MISC_ENABLE_TM2 … #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE … #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT … #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK … #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT … #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT … #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE … #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE … #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT … #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE … /* MISC_FEATURES_ENABLES non-architectural features */ #define MSR_MISC_FEATURES_ENABLES … #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT … #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT … #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT … #define MSR_IA32_TSC_DEADLINE … #define MSR_TSX_FORCE_ABORT … #define MSR_TFA_RTM_FORCE_ABORT_BIT … #define MSR_TFA_RTM_FORCE_ABORT … #define MSR_TFA_TSX_CPUID_CLEAR_BIT … #define MSR_TFA_TSX_CPUID_CLEAR … #define MSR_TFA_SDV_ENABLE_RTM_BIT … #define MSR_TFA_SDV_ENABLE_RTM … /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX … #define MSR_IA32_MCG_EBX … #define MSR_IA32_MCG_ECX … #define MSR_IA32_MCG_EDX … #define MSR_IA32_MCG_ESI … #define MSR_IA32_MCG_EDI … #define MSR_IA32_MCG_EBP … #define MSR_IA32_MCG_ESP … #define MSR_IA32_MCG_EFLAGS … #define MSR_IA32_MCG_EIP … #define MSR_IA32_MCG_RESERVED … /* Pentium IV performance counter MSRs */ #define MSR_P4_BPU_PERFCTR0 … #define MSR_P4_BPU_PERFCTR1 … #define MSR_P4_BPU_PERFCTR2 … #define MSR_P4_BPU_PERFCTR3 … #define MSR_P4_MS_PERFCTR0 … #define MSR_P4_MS_PERFCTR1 … #define MSR_P4_MS_PERFCTR2 … #define MSR_P4_MS_PERFCTR3 … #define MSR_P4_FLAME_PERFCTR0 … #define MSR_P4_FLAME_PERFCTR1 … #define MSR_P4_FLAME_PERFCTR2 … #define MSR_P4_FLAME_PERFCTR3 … #define MSR_P4_IQ_PERFCTR0 … #define MSR_P4_IQ_PERFCTR1 … #define MSR_P4_IQ_PERFCTR2 … #define MSR_P4_IQ_PERFCTR3 … #define MSR_P4_IQ_PERFCTR4 … #define MSR_P4_IQ_PERFCTR5 … #define MSR_P4_BPU_CCCR0 … #define MSR_P4_BPU_CCCR1 … #define MSR_P4_BPU_CCCR2 … #define MSR_P4_BPU_CCCR3 … #define MSR_P4_MS_CCCR0 … #define MSR_P4_MS_CCCR1 … #define MSR_P4_MS_CCCR2 … #define MSR_P4_MS_CCCR3 … #define MSR_P4_FLAME_CCCR0 … #define MSR_P4_FLAME_CCCR1 … #define MSR_P4_FLAME_CCCR2 … #define MSR_P4_FLAME_CCCR3 … #define MSR_P4_IQ_CCCR0 … #define MSR_P4_IQ_CCCR1 … #define MSR_P4_IQ_CCCR2 … #define MSR_P4_IQ_CCCR3 … #define MSR_P4_IQ_CCCR4 … #define MSR_P4_IQ_CCCR5 … #define MSR_P4_ALF_ESCR0 … #define MSR_P4_ALF_ESCR1 … #define MSR_P4_BPU_ESCR0 … #define MSR_P4_BPU_ESCR1 … #define MSR_P4_BSU_ESCR0 … #define MSR_P4_BSU_ESCR1 … #define MSR_P4_CRU_ESCR0 … #define MSR_P4_CRU_ESCR1 … #define MSR_P4_CRU_ESCR2 … #define MSR_P4_CRU_ESCR3 … #define MSR_P4_CRU_ESCR4 … #define MSR_P4_CRU_ESCR5 … #define MSR_P4_DAC_ESCR0 … #define MSR_P4_DAC_ESCR1 … #define MSR_P4_FIRM_ESCR0 … #define MSR_P4_FIRM_ESCR1 … #define MSR_P4_FLAME_ESCR0 … #define MSR_P4_FLAME_ESCR1 … #define MSR_P4_FSB_ESCR0 … #define MSR_P4_FSB_ESCR1 … #define MSR_P4_IQ_ESCR0 … #define MSR_P4_IQ_ESCR1 … #define MSR_P4_IS_ESCR0 … #define MSR_P4_IS_ESCR1 … #define MSR_P4_ITLB_ESCR0 … #define MSR_P4_ITLB_ESCR1 … #define MSR_P4_IX_ESCR0 … #define MSR_P4_IX_ESCR1 … #define MSR_P4_MOB_ESCR0 … #define MSR_P4_MOB_ESCR1 … #define MSR_P4_MS_ESCR0 … #define MSR_P4_MS_ESCR1 … #define MSR_P4_PMH_ESCR0 … #define MSR_P4_PMH_ESCR1 … #define MSR_P4_RAT_ESCR0 … #define MSR_P4_RAT_ESCR1 … #define MSR_P4_SAAT_ESCR0 … #define MSR_P4_SAAT_ESCR1 … #define MSR_P4_SSU_ESCR0 … #define MSR_P4_SSU_ESCR1 … #define MSR_P4_TBPU_ESCR0 … #define MSR_P4_TBPU_ESCR1 … #define MSR_P4_TC_ESCR0 … #define MSR_P4_TC_ESCR1 … #define MSR_P4_U2L_ESCR0 … #define MSR_P4_U2L_ESCR1 … #define MSR_P4_PEBS_MATRIX_VERT … /* Intel Core-based CPU performance counters */ #define MSR_CORE_PERF_FIXED_CTR0 … #define MSR_CORE_PERF_FIXED_CTR1 … #define MSR_CORE_PERF_FIXED_CTR2 … #define MSR_CORE_PERF_FIXED_CTR3 … #define MSR_CORE_PERF_FIXED_CTR_CTRL … #define MSR_CORE_PERF_GLOBAL_STATUS … #define MSR_CORE_PERF_GLOBAL_CTRL … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL … #define MSR_PERF_METRICS … /* PERF_GLOBAL_OVF_CTL bits */ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT … #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD … /* Geode defined MSRs */ #define MSR_GEODE_BUSCONT_CONF0 … /* Intel VT MSRs */ #define MSR_IA32_VMX_BASIC … #define MSR_IA32_VMX_PINBASED_CTLS … #define MSR_IA32_VMX_PROCBASED_CTLS … #define MSR_IA32_VMX_EXIT_CTLS … #define MSR_IA32_VMX_ENTRY_CTLS … #define MSR_IA32_VMX_MISC … #define MSR_IA32_VMX_CR0_FIXED0 … #define MSR_IA32_VMX_CR0_FIXED1 … #define MSR_IA32_VMX_CR4_FIXED0 … #define MSR_IA32_VMX_CR4_FIXED1 … #define MSR_IA32_VMX_VMCS_ENUM … #define MSR_IA32_VMX_PROCBASED_CTLS2 … #define MSR_IA32_VMX_EPT_VPID_CAP … #define MSR_IA32_VMX_TRUE_PINBASED_CTLS … #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS … #define MSR_IA32_VMX_TRUE_EXIT_CTLS … #define MSR_IA32_VMX_TRUE_ENTRY_CTLS … #define MSR_IA32_VMX_VMFUNC … #define MSR_IA32_VMX_PROCBASED_CTLS3 … /* VMX_BASIC bits and bitmasks */ #define VMX_BASIC_VMCS_SIZE_SHIFT … #define VMX_BASIC_TRUE_CTLS … #define VMX_BASIC_64 … #define VMX_BASIC_MEM_TYPE_SHIFT … #define VMX_BASIC_MEM_TYPE_MASK … #define VMX_BASIC_MEM_TYPE_WB … #define VMX_BASIC_INOUT … /* Resctrl MSRs: */ /* - Intel: */ #define MSR_IA32_L3_QOS_CFG … #define MSR_IA32_L2_QOS_CFG … #define MSR_IA32_QM_EVTSEL … #define MSR_IA32_QM_CTR … #define MSR_IA32_PQR_ASSOC … #define MSR_IA32_L3_CBM_BASE … #define MSR_RMID_SNC_CONFIG … #define MSR_IA32_L2_CBM_BASE … #define MSR_IA32_MBA_THRTL_BASE … /* - AMD: */ #define MSR_IA32_MBA_BW_BASE … #define MSR_IA32_SMBA_BW_BASE … #define MSR_IA32_EVT_CFG_BASE … /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT … #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS … #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE … /* AMD-V MSRs */ #define MSR_VM_CR … #define MSR_VM_IGNNE … #define MSR_VM_HSAVE_PA … #define SVM_VM_CR_VALID_MASK … #define SVM_VM_CR_SVM_LOCK_MASK … #define SVM_VM_CR_SVM_DIS_MASK … /* Hardware Feedback Interface */ #define MSR_IA32_HW_FEEDBACK_PTR … #define MSR_IA32_HW_FEEDBACK_CONFIG … /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS … #define LEGACY_XAPIC_DISABLED … #endif /* _ASM_X86_MSR_INDEX_H */
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