/* * Copyright (C) 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _gc_9_4_1_OFFSET_HEADER #define _gc_9_4_1_OFFSET_HEADER // addressBlock: gc_grbmdec // base address: 0x8000 #define mmGRBM_CNTL … #define mmGRBM_CNTL_BASE_IDX … #define mmGRBM_SKEW_CNTL … #define mmGRBM_SKEW_CNTL_BASE_IDX … #define mmGRBM_STATUS2 … #define mmGRBM_STATUS2_BASE_IDX … #define mmGRBM_PWR_CNTL … #define mmGRBM_PWR_CNTL_BASE_IDX … #define mmGRBM_STATUS … #define mmGRBM_STATUS_BASE_IDX … #define mmGRBM_STATUS_SE0 … #define mmGRBM_STATUS_SE0_BASE_IDX … #define mmGRBM_STATUS_SE1 … #define mmGRBM_STATUS_SE1_BASE_IDX … #define mmGRBM_SOFT_RESET … #define mmGRBM_SOFT_RESET_BASE_IDX … #define mmGRBM_GFX_CLKEN_CNTL … #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX … #define mmGRBM_WAIT_IDLE_CLOCKS … #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX … #define mmGRBM_STATUS_SE2 … #define mmGRBM_STATUS_SE2_BASE_IDX … #define mmGRBM_STATUS_SE3 … #define mmGRBM_STATUS_SE3_BASE_IDX … #define mmGRBM_READ_ERROR … #define mmGRBM_READ_ERROR_BASE_IDX … #define mmGRBM_READ_ERROR2 … #define mmGRBM_READ_ERROR2_BASE_IDX … #define mmGRBM_INT_CNTL … #define mmGRBM_INT_CNTL_BASE_IDX … #define mmGRBM_TRAP_OP … #define mmGRBM_TRAP_OP_BASE_IDX … #define mmGRBM_TRAP_ADDR … #define mmGRBM_TRAP_ADDR_BASE_IDX … #define mmGRBM_TRAP_ADDR_MSK … #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX … #define mmGRBM_TRAP_WD … #define mmGRBM_TRAP_WD_BASE_IDX … #define mmGRBM_TRAP_WD_MSK … #define mmGRBM_TRAP_WD_MSK_BASE_IDX … #define mmGRBM_DSM_BYPASS … #define mmGRBM_DSM_BYPASS_BASE_IDX … #define mmGRBM_WRITE_ERROR … #define mmGRBM_WRITE_ERROR_BASE_IDX … #define mmGRBM_IOV_ERROR … #define mmGRBM_IOV_ERROR_BASE_IDX … #define mmGRBM_CHIP_REVISION … #define mmGRBM_CHIP_REVISION_BASE_IDX … #define mmGRBM_GFX_CNTL … #define mmGRBM_GFX_CNTL_BASE_IDX … #define mmGRBM_RSMU_CFG … #define mmGRBM_RSMU_CFG_BASE_IDX … #define mmGRBM_IH_CREDIT … #define mmGRBM_IH_CREDIT_BASE_IDX … #define mmGRBM_PWR_CNTL2 … #define mmGRBM_PWR_CNTL2_BASE_IDX … #define mmGRBM_UTCL2_INVAL_RANGE_START … #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX … #define mmGRBM_UTCL2_INVAL_RANGE_END … #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX … #define mmGRBM_RSMU_READ_ERROR … #define mmGRBM_RSMU_READ_ERROR_BASE_IDX … #define mmGRBM_CHICKEN_BITS … #define mmGRBM_CHICKEN_BITS_BASE_IDX … #define mmGRBM_FENCE_RANGE0 … #define mmGRBM_FENCE_RANGE0_BASE_IDX … #define mmGRBM_FENCE_RANGE1 … #define mmGRBM_FENCE_RANGE1_BASE_IDX … #define mmGRBM_NOWHERE … #define mmGRBM_NOWHERE_BASE_IDX … #define mmGRBM_SCRATCH_REG0 … #define mmGRBM_SCRATCH_REG0_BASE_IDX … #define mmGRBM_SCRATCH_REG1 … #define mmGRBM_SCRATCH_REG1_BASE_IDX … #define mmGRBM_SCRATCH_REG2 … #define mmGRBM_SCRATCH_REG2_BASE_IDX … #define mmGRBM_SCRATCH_REG3 … #define mmGRBM_SCRATCH_REG3_BASE_IDX … #define mmGRBM_SCRATCH_REG4 … #define mmGRBM_SCRATCH_REG4_BASE_IDX … #define mmGRBM_SCRATCH_REG5 … #define mmGRBM_SCRATCH_REG5_BASE_IDX … #define mmGRBM_SCRATCH_REG6 … #define mmGRBM_SCRATCH_REG6_BASE_IDX … #define mmGRBM_SCRATCH_REG7 … #define mmGRBM_SCRATCH_REG7_BASE_IDX … // addressBlock: gc_cppdec2 // base address: 0xc600 #define mmCPF_EDC_TAG_CNT … #define mmCPF_EDC_TAG_CNT_BASE_IDX … #define mmCPF_EDC_ROQ_CNT … #define mmCPF_EDC_ROQ_CNT_BASE_IDX … #define mmCPG_EDC_TAG_CNT … #define mmCPG_EDC_TAG_CNT_BASE_IDX … #define mmCPG_EDC_DMA_CNT … #define mmCPG_EDC_DMA_CNT_BASE_IDX … #define mmCPC_EDC_SCRATCH_CNT … #define mmCPC_EDC_SCRATCH_CNT_BASE_IDX … #define mmCPC_EDC_UCODE_CNT … #define mmCPC_EDC_UCODE_CNT_BASE_IDX … #define mmDC_EDC_STATE_CNT … #define mmDC_EDC_STATE_CNT_BASE_IDX … #define mmDC_EDC_CSINVOC_CNT … #define mmDC_EDC_CSINVOC_CNT_BASE_IDX … #define mmDC_EDC_RESTORE_CNT … #define mmDC_EDC_RESTORE_CNT_BASE_IDX … // addressBlock: gc_gdsdec // base address: 0x9700 #define mmGDS_EDC_CNT … #define mmGDS_EDC_CNT_BASE_IDX … #define mmGDS_EDC_GRBM_CNT … #define mmGDS_EDC_GRBM_CNT_BASE_IDX … #define mmGDS_EDC_OA_DED … #define mmGDS_EDC_OA_DED_BASE_IDX … #define mmGDS_EDC_OA_PHY_CNT … #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX … #define mmGDS_EDC_OA_PIPE_CNT … #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX … // addressBlock: gc_shsdec // base address: 0x9000 #define mmSPI_EDC_CNT … #define mmSPI_EDC_CNT_BASE_IDX … // addressBlock: gc_sqdec // base address: 0x8c00 #define mmSQC_EDC_CNT2 … #define mmSQC_EDC_CNT2_BASE_IDX … #define mmSQC_EDC_CNT3 … #define mmSQC_EDC_CNT3_BASE_IDX … #define mmSQC_EDC_PARITY_CNT3 … #define mmSQC_EDC_PARITY_CNT3_BASE_IDX … #define mmSQC_EDC_CNT … #define mmSQC_EDC_CNT_BASE_IDX … #define mmSQ_EDC_SEC_CNT … #define mmSQ_EDC_SEC_CNT_BASE_IDX … #define mmSQ_EDC_DED_CNT … #define mmSQ_EDC_DED_CNT_BASE_IDX … #define mmSQ_EDC_INFO … #define mmSQ_EDC_INFO_BASE_IDX … #define mmSQ_EDC_CNT … #define mmSQ_EDC_CNT_BASE_IDX … // addressBlock: gc_tpdec // base address: 0x9400 #define mmTA_EDC_CNT … #define mmTA_EDC_CNT_BASE_IDX … // addressBlock: gc_tcdec // base address: 0xac00 #define mmTCP_EDC_CNT … #define mmTCP_EDC_CNT_BASE_IDX … #define mmTCP_EDC_CNT_NEW … #define mmTCP_EDC_CNT_NEW_BASE_IDX … #define mmTCP_ATC_EDC_GATCL1_CNT … #define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX … #define mmTCI_EDC_CNT … #define mmTCI_EDC_CNT_BASE_IDX … #define mmTCC_EDC_CNT … #define mmTCC_EDC_CNT_BASE_IDX … #define mmTCC_EDC_CNT2 … #define mmTCC_EDC_CNT2_BASE_IDX … #define mmTCA_EDC_CNT … #define mmTCA_EDC_CNT_BASE_IDX … // addressBlock: gc_tpdec // base address: 0x9400 #define mmTD_EDC_CNT … #define mmTD_EDC_CNT_BASE_IDX … #define mmTA_EDC_CNT … #define mmTA_EDC_CNT_BASE_IDX … // addressBlock: gc_ea_gceadec2 // base address: 0x9c00 #define mmGCEA_EDC_CNT … #define mmGCEA_EDC_CNT_BASE_IDX … #define mmGCEA_EDC_CNT2 … #define mmGCEA_EDC_CNT2_BASE_IDX … #define mmGCEA_EDC_CNT3 … #define mmGCEA_EDC_CNT3_BASE_IDX … #define mmGCEA_ERR_STATUS … #define mmGCEA_ERR_STATUS_BASE_IDX … // addressBlock: gc_gfxudec // base address: 0x30000 #define mmSCRATCH_REG0 … #define mmSCRATCH_REG0_BASE_IDX … #define mmSCRATCH_REG1 … #define mmSCRATCH_REG1_BASE_IDX … #define mmSCRATCH_REG2 … #define mmSCRATCH_REG2_BASE_IDX … #define mmSCRATCH_REG3 … #define mmSCRATCH_REG3_BASE_IDX … #define mmSCRATCH_REG4 … #define mmSCRATCH_REG4_BASE_IDX … #define mmSCRATCH_REG5 … #define mmSCRATCH_REG5_BASE_IDX … #define mmSCRATCH_REG6 … #define mmSCRATCH_REG6_BASE_IDX … #define mmSCRATCH_REG7 … #define mmSCRATCH_REG7_BASE_IDX … #define mmGRBM_GFX_INDEX … #define mmGRBM_GFX_INDEX_BASE_IDX … // addressBlock: gc_utcl2_atcl2dec // base address: 0xa000 #define mmATC_L2_CACHE_4K_DSM_INDEX … #define mmATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX … #define mmATC_L2_CACHE_2M_DSM_INDEX … #define mmATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX … #define mmATC_L2_CACHE_4K_DSM_CNTL … #define mmATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX … #define mmATC_L2_CACHE_2M_DSM_CNTL … #define mmATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX … // addressBlock: gc_utcl2_vml2pfdec // base address: 0xa100 #define mmVML2_MEM_ECC_INDEX … #define mmVML2_MEM_ECC_INDEX_BASE_IDX … #define mmVML2_WALKER_MEM_ECC_INDEX … #define mmVML2_WALKER_MEM_ECC_INDEX_BASE_IDX … #define mmUTCL2_MEM_ECC_INDEX … #define mmUTCL2_MEM_ECC_INDEX_BASE_IDX … #define mmVML2_MEM_ECC_CNTL … #define mmVML2_MEM_ECC_CNTL_BASE_IDX … #define mmVML2_WALKER_MEM_ECC_CNTL … #define mmVML2_WALKER_MEM_ECC_CNTL_BASE_IDX … #define mmUTCL2_MEM_ECC_CNTL … #define mmUTCL2_MEM_ECC_CNTL_BASE_IDX … // addressBlock: gc_rlcpdec // base address: 0x3b000 #define mmRLC_EDC_CNT … #define mmRLC_EDC_CNT_BASE_IDX … #define mmRLC_EDC_CNT2 … #define mmRLC_EDC_CNT2_BASE_IDX … #endif
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