/* * Copyright (C) 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _gc_9_4_1_SH_MASK_HEADER #define _gc_9_4_1_SH_MASK_HEADER // addressBlock: gc_cppdec2 //CPF_EDC_TAG_CNT #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT … #define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT … #define CPF_EDC_TAG_CNT__DED_COUNT_MASK … #define CPF_EDC_TAG_CNT__SEC_COUNT_MASK … //CPF_EDC_ROQ_CNT #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT … #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT … #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT … #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT … #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK … #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK … #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK … #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK … //CPG_EDC_TAG_CNT #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT … #define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT … #define CPG_EDC_TAG_CNT__DED_COUNT_MASK … #define CPG_EDC_TAG_CNT__SEC_COUNT_MASK … //CPG_EDC_DMA_CNT #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT … #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT … #define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT … #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT … #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK … #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK … #define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK … #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK … //CPC_EDC_SCRATCH_CNT #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT … #define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT … #define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK … #define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK … //CPC_EDC_UCODE_CNT #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT … #define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT … #define CPC_EDC_UCODE_CNT__DED_COUNT_MASK … #define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK … //DC_EDC_STATE_CNT #define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT … #define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT … #define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK … #define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK … //DC_EDC_CSINVOC_CNT #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT … #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT … #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT … #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT … #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK … #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK … #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK … #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK … //DC_EDC_RESTORE_CNT #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT … #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT … #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT … #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT … #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK … #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK … #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK … #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK … // addressBlock: gc_gdsdec //GDS_EDC_CNT #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT … #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT … #define GDS_EDC_CNT__UNUSED__SHIFT … #define GDS_EDC_CNT__GDS_MEM_DED_MASK … #define GDS_EDC_CNT__GDS_MEM_SEC_MASK … #define GDS_EDC_CNT__UNUSED_MASK … //GDS_EDC_GRBM_CNT #define GDS_EDC_GRBM_CNT__DED__SHIFT … #define GDS_EDC_GRBM_CNT__SEC__SHIFT … #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT … #define GDS_EDC_GRBM_CNT__DED_MASK … #define GDS_EDC_GRBM_CNT__SEC_MASK … #define GDS_EDC_GRBM_CNT__UNUSED_MASK … //GDS_EDC_OA_DED #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT … #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT … #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT … #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT … #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT … #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT … #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT … #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT … #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT … #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT … #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT … #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT … #define GDS_EDC_OA_DED__UNUSED1__SHIFT … #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK … #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK … #define GDS_EDC_OA_DED__ME0_CS_DED_MASK … #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK … #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK … #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK … #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK … #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK … #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK … #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK … #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK … #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK … #define GDS_EDC_OA_DED__UNUSED1_MASK … //GDS_EDC_OA_PHY_CNT #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT … #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT … #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT … #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT … #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT … #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT … #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT … #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK … #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK … #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK … #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK … #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK … #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK … #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK … //GDS_EDC_OA_PIPE_CNT #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT … #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK … #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK … #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK … // addressBlock: gc_shsdec //SPI_EDC_CNT #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT … #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK … #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK … #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK … #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK … #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK … #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK … #define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT_MASK … #define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT_MASK … #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK … #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK … // addressBlock: gc_sqdec //SQC_EDC_CNT2 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT … #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK … #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK … //SQC_EDC_CNT3 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT … #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT … #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK … #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK … #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK … //SQC_EDC_PARITY_CNT3 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT … #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK … #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK … //SQC_EDC_CNT #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT … #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK … #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK … //SQ_EDC_SEC_CNT #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT … #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT … #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT … #define SQ_EDC_SEC_CNT__LDS_SEC_MASK … #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK … #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK … //SQ_EDC_DED_CNT #define SQ_EDC_DED_CNT__LDS_DED__SHIFT … #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT … #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT … #define SQ_EDC_DED_CNT__LDS_DED_MASK … #define SQ_EDC_DED_CNT__SGPR_DED_MASK … #define SQ_EDC_DED_CNT__VGPR_DED_MASK … //SQ_EDC_INFO #define SQ_EDC_INFO__WAVE_ID__SHIFT … #define SQ_EDC_INFO__SIMD_ID__SHIFT … #define SQ_EDC_INFO__SOURCE__SHIFT … #define SQ_EDC_INFO__VM_ID__SHIFT … #define SQ_EDC_INFO__WAVE_ID_MASK … #define SQ_EDC_INFO__SIMD_ID_MASK … #define SQ_EDC_INFO__SOURCE_MASK … #define SQ_EDC_INFO__VM_ID_MASK … //SQ_EDC_CNT #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT … #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT … #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT … #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT … #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK … #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK … #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK … #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK … #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK … #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK … #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK … #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK … #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK … #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK … #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK … #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK … // addressBlock: gc_tpdec //TA_EDC_CNT #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK … // addressBlock: gc_tcdec //TCP_EDC_CNT #define TCP_EDC_CNT__SEC_COUNT__SHIFT … #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT … #define TCP_EDC_CNT__DED_COUNT__SHIFT … #define TCP_EDC_CNT__SEC_COUNT_MASK … #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK … #define TCP_EDC_CNT__DED_COUNT_MASK … //TCP_EDC_CNT_NEW #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT … #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK … #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK … #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK … #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK … #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK … #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK … //TCP_ATC_EDC_GATCL1_CNT #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT … #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK … //TCI_EDC_CNT #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT … #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT … #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK … #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK … //TCA_EDC_CNT #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT … #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT … #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT … #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT … #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK … #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK … #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK … #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK … //TCC_EDC_CNT #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT … #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT … #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT … #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT … #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT … #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT … #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT … #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT … #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK … #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK … #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK … #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK … #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK … #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK … #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK … #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK … #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK … #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK … #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK … #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK … #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK … #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK … //TCC_EDC_CNT2 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT … #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT … #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK … #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK … #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK … #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK … #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK … #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK … #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK … #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK … #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK … #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK … #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK … #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK … #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK … #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK … #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK … #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK … // addressBlock: gc_tpdec //TD_EDC_CNT #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT … #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT … #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT … #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT … #define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT … #define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT … #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK … #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK … #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK … #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK … #define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK … #define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK … //TA_EDC_CNT #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT … #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK … #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK … #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK … // addressBlock: gc_ea_gceadec2 //GCEA_EDC_CNT #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT_MASK … //GCEA_EDC_CNT2 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK … //GCEA_EDC_CNT3 #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT … #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT … #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK … #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK … //GCEA_ERR_STATUS #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT … #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT … #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT … #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT … #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT … #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT … #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT … #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK … #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK … #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK … #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK … #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK … #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK … #define GCEA_ERR_STATUS__FUE_FLAG_MASK … // addressBlock: gc_gfxudec //GRBM_GFX_INDEX #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT … #define GRBM_GFX_INDEX__SH_INDEX__SHIFT … #define GRBM_GFX_INDEX__SE_INDEX__SHIFT … #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT … #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK … #define GRBM_GFX_INDEX__SH_INDEX_MASK … #define GRBM_GFX_INDEX__SE_INDEX_MASK … #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK … #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK … #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK … // addressBlock: gc_utcl2_atcl2dec //ATC_L2_CNTL //ATC_L2_CACHE_4K_DSM_INDEX #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT … #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK … //ATC_L2_CACHE_2M_DSM_INDEX #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT … #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK … //ATC_L2_CACHE_4K_DSM_CNTL #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT … #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT … #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK … #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK … //ATC_L2_CACHE_2M_DSM_CNTL #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT … #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT … #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK … #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK … // addressBlock: gc_utcl2_vml2pfdec //VML2_MEM_ECC_INDEX #define VML2_MEM_ECC_INDEX__INDEX__SHIFT … #define VML2_MEM_ECC_INDEX__INDEX_MASK … //VML2_WALKER_MEM_ECC_INDEX #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT … #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK … //UTCL2_MEM_ECC_INDEX #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT … #define UTCL2_MEM_ECC_INDEX__INDEX_MASK … //VML2_MEM_ECC_CNTL #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT … #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT … #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK … #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK … //VML2_WALKER_MEM_ECC_CNTL #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT … #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT … #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK … #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK … //UTCL2_MEM_ECC_CNTL #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT … #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT … #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK … #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK … // addressBlock: gc_rlcpdec //RLC_EDC_CNT #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK … //RLC_EDC_CNT2 #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT … #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK … #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK … #endif
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