linux/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/kernel.h>

#include "amdgpu.h"
#include "amdgpu_gfx.h"
#include "soc15.h"
#include "soc15d.h"
#include "amdgpu_atomfirmware.h"
#include "amdgpu_pm.h"

#include "gc/gc_9_4_1_offset.h"
#include "gc/gc_9_4_1_sh_mask.h"
#include "soc15_common.h"

#include "gfx_v9_4.h"
#include "amdgpu_ras.h"

static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = …;

static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
				  u32 sh_num, u32 instance)
{ … }

static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = …;

static const char * const vml2_mems[] = …;

static const char * const vml2_walker_mems[] = …;

static const char * const utcl2_router_mems[] = …;

static const char * const atc_l2_cache_2m_mems[] = …;

static const char * const atc_l2_cache_4k_mems[] = …;

static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
					 struct ras_err_data *err_data)
{ … }

static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev,
				    const struct soc15_reg_entry *reg,
				    uint32_t se_id, uint32_t inst_id,
				    uint32_t value, uint32_t *sec_count,
				    uint32_t *ded_count)
{ … }

static void gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
					  void *ras_error_status)
{ … }

static void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
{ … }

static const struct soc15_reg_entry gfx_v9_4_ea_err_status_regs = …;

static void gfx_v9_4_query_ras_error_status(struct amdgpu_device *adev)
{ … }


const struct amdgpu_ras_block_hw_ops  gfx_v9_4_ras_ops = …;

struct amdgpu_gfx_ras gfx_v9_4_ras = …;