/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_gfx.h" #include "soc15.h" #include "soc15d.h" #include "soc15_common.h" #include "vega10_enum.h" #include "v9_structs.h" #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" #include "gc/gc_9_4_3_offset.h" #include "gc/gc_9_4_3_sh_mask.h" #include "gfx_v9_4_3.h" #include "amdgpu_xcp.h" #include "amdgpu_aca.h" MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; #define GFX9_MEC_HPD_SIZE … #define RLCG_UCODE_LOADING_START_ADDRESS … #define GOLDEN_GB_ADDR_CONFIG … #define CP_HQD_PERSISTENT_STATE_DEFAULT … #define mmSMNAID_XCD0_MCA_SMU … #define mmSMNAID_XCD1_MCA_SMU … #define mmSMNXCD_XCD0_MCA_SMU … #define XCC_REG_RANGE_0_LOW … #define XCC_REG_RANGE_0_HIGH … #define XCC_REG_RANGE_1_LOW … #define XCC_REG_RANGE_1_HIGH … #define NORMALIZE_XCC_REG_OFFSET(offset) … struct amdgpu_gfx_ras gfx_v9_4_3_ras; static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) { … } static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, struct amdgpu_ring *ring, enum amdgpu_unmap_queues_action action, u64 gpu_addr, u64 seq) { … } static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, struct amdgpu_ring *ring, u64 addr, u64 seq) { … } static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, uint16_t pasid, uint32_t flush_type, bool all_hub) { … } static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = …; static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) { … } static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) { … } static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, bool wc, uint32_t reg, uint32_t val) { … } static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, int mem_space, int opt, uint32_t addr0, uint32_t addr1, uint32_t ref, uint32_t mask, uint32_t inv) { … } static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) { … } static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) { … } /* This value might differs per partition */ static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, const char *chip_name) { … } static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) { … } static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, const char *chip_name) { … } static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) { … } static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) { … } static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) { … } static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { … } static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) { … } static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) { … } static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) { … } static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, int num_xccs_per_xcp) { … } static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) { … } static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = …; static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) { … } static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) { … } static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = …; static const struct aca_info gfx_v9_4_3_aca_info = …; static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, int xcc_id, int mec, int pipe, int queue) { … } static int gfx_v9_4_3_sw_init(void *handle) { … } static int gfx_v9_4_3_sw_fini(void *handle) { … } #define DEFAULT_SH_MEM_BASES … static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) { … } static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) { … } static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) { … } static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = …; static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) { … } static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) { … } static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, int xcc_id) { … } /* KIQ functions */ static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) { … } static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) { … } static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) { … } static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, int xcc_id) { … } static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, int xcc_id) { … } static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) { … } static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) { … } static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_hw_init(void *handle) { … } static int gfx_v9_4_3_hw_fini(void *handle) { … } static int gfx_v9_4_3_suspend(void *handle) { … } static int gfx_v9_4_3_resume(void *handle) { … } static bool gfx_v9_4_3_is_idle(void *handle) { … } static int gfx_v9_4_3_wait_for_idle(void *handle) { … } static int gfx_v9_4_3_soft_reset(void *handle) { … } static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) { … } static int gfx_v9_4_3_early_init(void *handle) { … } static int gfx_v9_4_3_late_init(void *handle) { … } static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static void gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static void gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) { … } static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = …; static int gfx_v9_4_3_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static int gfx_v9_4_3_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) { … } static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { … } static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) { … } static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned int flags) { … } static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) { … } static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) { … } static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state, int xcc_id) { … } static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void gfx_v9_4_3_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { … } static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) { … } static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { … } static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) { … } enum amdgpu_gfx_cp_ras_mem_id { … }; enum amdgpu_gfx_gcea_ras_mem_id { … }; enum amdgpu_gfx_gc_cane_ras_mem_id { … }; enum amdgpu_gfx_gcutcl2_ras_mem_id { … }; enum amdgpu_gfx_gds_ras_mem_id { … }; enum amdgpu_gfx_lds_ras_mem_id { … }; enum amdgpu_gfx_rlc_ras_mem_id { … }; enum amdgpu_gfx_sp_ras_mem_id { … }; enum amdgpu_gfx_spi_ras_mem_id { … }; enum amdgpu_gfx_sqc_ras_mem_id { … }; enum amdgpu_gfx_sq_ras_mem_id { … }; enum amdgpu_gfx_ta_ras_mem_id { … }; enum amdgpu_gfx_tcc_ras_mem_id { … }; enum amdgpu_gfx_tca_ras_mem_id { … }; enum amdgpu_gfx_tci_ras_mem_id { … }; enum amdgpu_gfx_tcp_ras_mem_id { … }; enum amdgpu_gfx_td_ras_mem_id { … }; enum amdgpu_gfx_tcx_ras_mem_id { … }; enum amdgpu_gfx_atc_l2_ras_mem_id { … }; enum amdgpu_gfx_utcl2_ras_mem_id { … }; enum amdgpu_gfx_vml2_ras_mem_id { … }; enum amdgpu_gfx_vml2_walker_ras_mem_id { … }; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = …; static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = …; static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = …; static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = …; static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = …; static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) { … } static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) { … } static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) { … } static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) { … } static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) { … } static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = …; static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = …; static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = …; static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = …; static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = …; static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = …; static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) { … } static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap, int xcc_id) { … } static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) { … } static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) { … } const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = …; static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) { … } static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) { … } struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = …; struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = …; static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) { … } struct amdgpu_gfx_ras gfx_v9_4_3_ras = …;
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