// SPDX-License-Identifier: GPL-2.0-only /* * * Copyright (C) STMicroelectronics SA 2017 * Author(s): M'boumba Cedric Madianga <[email protected]> * Pierre-Yves Mordret <[email protected]> * * Driver for STM32 MDMA controller * * Inspired by stm32-dma.c and dma-jz4780.c */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/jiffies.h> #include <linux/list.h> #include <linux/log2.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_dma.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include "../virt-dma.h" #define STM32_MDMA_GISR0 … /* MDMA Channel x interrupt/status register */ #define STM32_MDMA_CISR(x) … #define STM32_MDMA_CISR_CRQA … #define STM32_MDMA_CISR_TCIF … #define STM32_MDMA_CISR_BTIF … #define STM32_MDMA_CISR_BRTIF … #define STM32_MDMA_CISR_CTCIF … #define STM32_MDMA_CISR_TEIF … /* MDMA Channel x interrupt flag clear register */ #define STM32_MDMA_CIFCR(x) … #define STM32_MDMA_CIFCR_CLTCIF … #define STM32_MDMA_CIFCR_CBTIF … #define STM32_MDMA_CIFCR_CBRTIF … #define STM32_MDMA_CIFCR_CCTCIF … #define STM32_MDMA_CIFCR_CTEIF … #define STM32_MDMA_CIFCR_CLEAR_ALL … /* MDMA Channel x error status register */ #define STM32_MDMA_CESR(x) … #define STM32_MDMA_CESR_BSE … #define STM32_MDMA_CESR_ASR … #define STM32_MDMA_CESR_TEMD … #define STM32_MDMA_CESR_TELD … #define STM32_MDMA_CESR_TED … #define STM32_MDMA_CESR_TEA_MASK … /* MDMA Channel x control register */ #define STM32_MDMA_CCR(x) … #define STM32_MDMA_CCR_SWRQ … #define STM32_MDMA_CCR_WEX … #define STM32_MDMA_CCR_HEX … #define STM32_MDMA_CCR_BEX … #define STM32_MDMA_CCR_SM … #define STM32_MDMA_CCR_PL_MASK … #define STM32_MDMA_CCR_PL(n) … #define STM32_MDMA_CCR_TCIE … #define STM32_MDMA_CCR_BTIE … #define STM32_MDMA_CCR_BRTIE … #define STM32_MDMA_CCR_CTCIE … #define STM32_MDMA_CCR_TEIE … #define STM32_MDMA_CCR_EN … #define STM32_MDMA_CCR_IRQ_MASK … /* MDMA Channel x transfer configuration register */ #define STM32_MDMA_CTCR(x) … #define STM32_MDMA_CTCR_BWM … #define STM32_MDMA_CTCR_SWRM … #define STM32_MDMA_CTCR_TRGM_MSK … #define STM32_MDMA_CTCR_TRGM(n) … #define STM32_MDMA_CTCR_TRGM_GET(n) … #define STM32_MDMA_CTCR_PAM_MASK … #define STM32_MDMA_CTCR_PAM(n) … #define STM32_MDMA_CTCR_PKE … #define STM32_MDMA_CTCR_TLEN_MSK … #define STM32_MDMA_CTCR_TLEN(n) … #define STM32_MDMA_CTCR_TLEN_GET(n) … #define STM32_MDMA_CTCR_LEN2_MSK … #define STM32_MDMA_CTCR_LEN2(n) … #define STM32_MDMA_CTCR_LEN2_GET(n) … #define STM32_MDMA_CTCR_DBURST_MASK … #define STM32_MDMA_CTCR_DBURST(n) … #define STM32_MDMA_CTCR_SBURST_MASK … #define STM32_MDMA_CTCR_SBURST(n) … #define STM32_MDMA_CTCR_DINCOS_MASK … #define STM32_MDMA_CTCR_DINCOS(n) … #define STM32_MDMA_CTCR_SINCOS_MASK … #define STM32_MDMA_CTCR_SINCOS(n) … #define STM32_MDMA_CTCR_DSIZE_MASK … #define STM32_MDMA_CTCR_DSIZE(n) … #define STM32_MDMA_CTCR_SSIZE_MASK … #define STM32_MDMA_CTCR_SSIZE(n) … #define STM32_MDMA_CTCR_DINC_MASK … #define STM32_MDMA_CTCR_DINC(n) … #define STM32_MDMA_CTCR_SINC_MASK … #define STM32_MDMA_CTCR_SINC(n) … #define STM32_MDMA_CTCR_CFG_MASK … /* MDMA Channel x block number of data register */ #define STM32_MDMA_CBNDTR(x) … #define STM32_MDMA_CBNDTR_BRC_MK … #define STM32_MDMA_CBNDTR_BRC(n) … #define STM32_MDMA_CBNDTR_BRC_GET(n) … #define STM32_MDMA_CBNDTR_BRDUM … #define STM32_MDMA_CBNDTR_BRSUM … #define STM32_MDMA_CBNDTR_BNDT_MASK … #define STM32_MDMA_CBNDTR_BNDT(n) … /* MDMA Channel x source address register */ #define STM32_MDMA_CSAR(x) … /* MDMA Channel x destination address register */ #define STM32_MDMA_CDAR(x) … /* MDMA Channel x block repeat address update register */ #define STM32_MDMA_CBRUR(x) … #define STM32_MDMA_CBRUR_DUV_MASK … #define STM32_MDMA_CBRUR_DUV(n) … #define STM32_MDMA_CBRUR_SUV_MASK … #define STM32_MDMA_CBRUR_SUV(n) … /* MDMA Channel x link address register */ #define STM32_MDMA_CLAR(x) … /* MDMA Channel x trigger and bus selection register */ #define STM32_MDMA_CTBR(x) … #define STM32_MDMA_CTBR_DBUS … #define STM32_MDMA_CTBR_SBUS … #define STM32_MDMA_CTBR_TSEL_MASK … #define STM32_MDMA_CTBR_TSEL(n) … /* MDMA Channel x mask address register */ #define STM32_MDMA_CMAR(x) … /* MDMA Channel x mask data register */ #define STM32_MDMA_CMDR(x) … #define STM32_MDMA_MAX_BUF_LEN … #define STM32_MDMA_MAX_BLOCK_LEN … #define STM32_MDMA_MAX_CHANNELS … #define STM32_MDMA_MAX_REQUESTS … #define STM32_MDMA_MAX_BURST … #define STM32_MDMA_VERY_HIGH_PRIORITY … enum stm32_mdma_trigger_mode { … }; enum stm32_mdma_width { … }; enum stm32_mdma_inc_mode { … }; struct stm32_mdma_chan_config { … }; struct stm32_mdma_hwdesc { … } __aligned(…); struct stm32_mdma_desc_node { … }; struct stm32_mdma_desc { … }; struct stm32_mdma_dma_config { … }; struct stm32_mdma_chan { … }; struct stm32_mdma_device { … }; static struct stm32_mdma_device *stm32_mdma_get_dev( struct stm32_mdma_chan *chan) { … } static struct stm32_mdma_chan *to_stm32_mdma_chan(struct dma_chan *c) { … } static struct stm32_mdma_desc *to_stm32_mdma_desc(struct virt_dma_desc *vdesc) { … } static struct device *chan2dev(struct stm32_mdma_chan *chan) { … } static struct device *mdma2dev(struct stm32_mdma_device *mdma_dev) { … } static u32 stm32_mdma_read(struct stm32_mdma_device *dmadev, u32 reg) { … } static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val) { … } static void stm32_mdma_set_bits(struct stm32_mdma_device *dmadev, u32 reg, u32 mask) { … } static void stm32_mdma_clr_bits(struct stm32_mdma_device *dmadev, u32 reg, u32 mask) { … } static struct stm32_mdma_desc *stm32_mdma_alloc_desc( struct stm32_mdma_chan *chan, u32 count) { … } static void stm32_mdma_desc_free(struct virt_dma_desc *vdesc) { … } static int stm32_mdma_get_width(struct stm32_mdma_chan *chan, enum dma_slave_buswidth width) { … } static enum dma_slave_buswidth stm32_mdma_get_max_width(dma_addr_t addr, u32 buf_len, u32 tlen) { … } static u32 stm32_mdma_get_best_burst(u32 buf_len, u32 tlen, u32 max_burst, enum dma_slave_buswidth width) { … } static int stm32_mdma_disable_chan(struct stm32_mdma_chan *chan) { … } static void stm32_mdma_stop(struct stm32_mdma_chan *chan) { … } static void stm32_mdma_set_bus(struct stm32_mdma_device *dmadev, u32 *ctbr, u32 ctbr_mask, u32 src_addr) { … } static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, enum dma_transfer_direction direction, u32 *mdma_ccr, u32 *mdma_ctcr, u32 *mdma_ctbr, dma_addr_t addr, u32 buf_len) { … } static void stm32_mdma_dump_hwdesc(struct stm32_mdma_chan *chan, struct stm32_mdma_desc_node *node) { … } static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan, struct stm32_mdma_desc *desc, enum dma_transfer_direction dir, u32 count, dma_addr_t src_addr, dma_addr_t dst_addr, u32 len, u32 ctcr, u32 ctbr, bool is_last, bool is_first, bool is_cyclic) { … } static int stm32_mdma_setup_xfer(struct stm32_mdma_chan *chan, struct stm32_mdma_desc *desc, struct scatterlist *sgl, u32 sg_len, enum dma_transfer_direction direction) { … } static struct dma_async_tx_descriptor * stm32_mdma_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl, u32 sg_len, enum dma_transfer_direction direction, unsigned long flags, void *context) { … } static struct dma_async_tx_descriptor * stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags) { … } static struct dma_async_tx_descriptor * stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { … } static void stm32_mdma_dump_reg(struct stm32_mdma_chan *chan) { … } static void stm32_mdma_start_transfer(struct stm32_mdma_chan *chan) { … } static void stm32_mdma_issue_pending(struct dma_chan *c) { … } static int stm32_mdma_pause(struct dma_chan *c) { … } static int stm32_mdma_resume(struct dma_chan *c) { … } static int stm32_mdma_terminate_all(struct dma_chan *c) { … } static void stm32_mdma_synchronize(struct dma_chan *c) { … } static int stm32_mdma_slave_config(struct dma_chan *c, struct dma_slave_config *config) { … } static size_t stm32_mdma_desc_residue(struct stm32_mdma_chan *chan, struct stm32_mdma_desc *desc, u32 curr_hwdesc, struct dma_tx_state *state) { … } static enum dma_status stm32_mdma_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *state) { … } static void stm32_mdma_xfer_end(struct stm32_mdma_chan *chan) { … } static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid) { … } static int stm32_mdma_alloc_chan_resources(struct dma_chan *c) { … } static void stm32_mdma_free_chan_resources(struct dma_chan *c) { … } static bool stm32_mdma_filter_fn(struct dma_chan *c, void *fn_param) { … } static struct dma_chan *stm32_mdma_of_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { … } static const struct of_device_id stm32_mdma_of_match[] = …; MODULE_DEVICE_TABLE(of, stm32_mdma_of_match); static int stm32_mdma_probe(struct platform_device *pdev) { … } #ifdef CONFIG_PM static int stm32_mdma_runtime_suspend(struct device *dev) { … } static int stm32_mdma_runtime_resume(struct device *dev) { … } #endif #ifdef CONFIG_PM_SLEEP static int stm32_mdma_pm_suspend(struct device *dev) { … } static int stm32_mdma_pm_resume(struct device *dev) { … } #endif static const struct dev_pm_ops stm32_mdma_pm_ops = …; static struct platform_driver stm32_mdma_driver = …; static int __init stm32_mdma_init(void) { … } subsys_initcall(stm32_mdma_init); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …;
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