/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_imu.h" #include "amdgpu_dpm.h" #include "imu_v11_0_3.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; static int imu_v11_0_init_microcode(struct amdgpu_device *adev) { … } static int imu_v11_0_load_microcode(struct amdgpu_device *adev) { … } static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev) { … } static void imu_v11_0_setup(struct amdgpu_device *adev) { … } static int imu_v11_0_start(struct amdgpu_device *adev) { … } static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = …; static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11_0_2[] = …; static void program_imu_rlc_ram(struct amdgpu_device *adev, const struct imu_rlc_ram_golden *regs, const u32 array_size) { … } static void imu_v11_0_program_rlc_ram(struct amdgpu_device *adev) { … } const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = …;