/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _smuio_13_0_6_SH_MASK_HEADER #define _smuio_13_0_6_SH_MASK_HEADER // addressBlock: smuio_smuio_reset_SmuSmuioDec //SMUIO_MP_RESET_INTR #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT … #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK … //SMUIO_SOC_HALT #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT … #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT … #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK … #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK … // addressBlock: smuio_smuio_tsc_SmuSmuioDec //PWROK_REFCLK_GAP_CYCLES #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT … #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT … #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK … #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK … //GOLDEN_TSC_INCREMENT_UPPER #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT … #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK … //GOLDEN_TSC_INCREMENT_LOWER #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT … #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK … //GOLDEN_TSC_COUNT_UPPER #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT … #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK … //GOLDEN_TSC_COUNT_LOWER #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT … #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK … //SOC_GOLDEN_TSC_SHADOW_UPPER #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT … #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK … //SOC_GOLDEN_TSC_SHADOW_LOWER #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT … #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK … //SOC_GAP_PWROK #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT … #define SOC_GAP_PWROK__soc_gap_pwrok_MASK … // addressBlock: smuio_smuio_swtimer_SmuSmuioDec //PWR_DISP_TIMER_CONTROL #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK … #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK … //PWR_DISP_TIMER_DEBUG #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK … #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK … //PWR_DISP_TIMER2_CONTROL #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK … #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK … //PWR_DISP_TIMER2_DEBUG #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK … #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK … //PWR_DISP_TIMER_GLOBAL_CONTROL #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT … #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT … #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK … #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK … //PWR_IH_CONTROL #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT … #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT … #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT … #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT … #define PWR_IH_CONTROL__MAX_CREDIT_MASK … #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK … #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK … #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK … // addressBlock: smuio_smuio_misc_SmuSmuioDec //SMUIO_MCM_CONFIG #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT … #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT … #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT … #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT … #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT … #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT … #define SMUIO_MCM_CONFIG__DIE_ID_MASK … #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK … #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK … #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK … #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK … #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK … //IP_DISCOVERY_VERSION #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT … #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK … //SCRATCH_REGISTER0 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT … #define SCRATCH_REGISTER0__ScratchPad0_MASK … //SCRATCH_REGISTER1 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT … #define SCRATCH_REGISTER1__ScratchPad1_MASK … //SCRATCH_REGISTER2 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT … #define SCRATCH_REGISTER2__ScratchPad2_MASK … //SCRATCH_REGISTER3 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT … #define SCRATCH_REGISTER3__ScratchPad3_MASK … //SCRATCH_REGISTER4 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT … #define SCRATCH_REGISTER4__ScratchPad4_MASK … //SCRATCH_REGISTER5 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT … #define SCRATCH_REGISTER5__ScratchPad5_MASK … //SCRATCH_REGISTER6 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT … #define SCRATCH_REGISTER6__ScratchPad6_MASK … //SCRATCH_REGISTER7 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT … #define SCRATCH_REGISTER7__ScratchPad7_MASK … // addressBlock: smuio_smuio_i2c_SmuSmuioDec //CKSVII2C_IC_CON #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT … #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT … #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT … #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT … #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT … #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT … #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT … #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT … #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT … #define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL__SHIFT … #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK … #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK … #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK … #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK … #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK … #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK … #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK … #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK … #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK … #define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL_MASK … //CKSVII2C_IC_TAR #define CKSVII2C_IC_TAR__IC_TAR__SHIFT … #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT … #define CKSVII2C_IC_TAR__SPECIAL__SHIFT … #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT … #define CKSVII2C_IC_TAR__IC_TAR_MASK … #define CKSVII2C_IC_TAR__GC_OR_START_MASK … #define CKSVII2C_IC_TAR__SPECIAL_MASK … #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK … //CKSVII2C_IC_SAR #define CKSVII2C_IC_SAR__IC_SAR__SHIFT … #define CKSVII2C_IC_SAR__IC_SAR_MASK … //CKSVII2C_IC_HS_MADDR #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT … #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK … //CKSVII2C_IC_DATA_CMD #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT … #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT … #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT … #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT … #define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE__SHIFT … #define CKSVII2C_IC_DATA_CMD__DAT_MASK … #define CKSVII2C_IC_DATA_CMD__CMD_MASK … #define CKSVII2C_IC_DATA_CMD__STOP_MASK … #define CKSVII2C_IC_DATA_CMD__RESTART_MASK … #define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE_MASK … //CKSVII2C_IC_SS_SCL_HCNT #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT … #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK … //CKSVII2C_IC_SS_SCL_LCNT #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT … #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK … //CKSVII2C_IC_FS_SCL_HCNT #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT … #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK … //CKSVII2C_IC_FS_SCL_LCNT #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT … #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK … //CKSVII2C_IC_HS_SCL_HCNT #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT … #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK … //CKSVII2C_IC_HS_SCL_LCNT #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT … #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK … //CKSVII2C_IC_INTR_STAT #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW__SHIFT … #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK … #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK … #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK … #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK … #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK … #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK … #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK … #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK … #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK … #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK … #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK … #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK … #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK … #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK … #define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW_MASK … //CKSVII2C_IC_INTR_MASK #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW__SHIFT … #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK … #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK … #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK … #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK … #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK … #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK … #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK … #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK … #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK … #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK … #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK … #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK … #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK … #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK … #define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW_MASK … //CKSVII2C_IC_RAW_INTR_STAT //CKSVII2C_IC_RX_TL #define CKSVII2C_IC_RX_TL__RX_TL__SHIFT … #define CKSVII2C_IC_RX_TL__RX_TL_MASK … //CKSVII2C_IC_TX_TL #define CKSVII2C_IC_TX_TL__TX_TL__SHIFT … #define CKSVII2C_IC_TX_TL__TX_TL_MASK … //CKSVII2C_IC_CLR_INTR //CKSVII2C_IC_CLR_RX_UNDER //CKSVII2C_IC_CLR_RX_OVER //CKSVII2C_IC_CLR_TX_OVER //CKSVII2C_IC_CLR_RD_REQ //CKSVII2C_IC_CLR_TX_ABRT //CKSVII2C_IC_CLR_RX_DONE //CKSVII2C_IC_CLR_ACTIVITY //CKSVII2C_IC_CLR_STOP_DET //CKSVII2C_IC_CLR_START_DET //CKSVII2C_IC_CLR_GEN_CALL //CKSVII2C_IC_ENABLE #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT … #define CKSVII2C_IC_ENABLE__ABORT__SHIFT … #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT … #define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE__SHIFT … #define CKSVII2C_IC_ENABLE__ENABLE_MASK … #define CKSVII2C_IC_ENABLE__ABORT_MASK … #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK_MASK … #define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE_MASK … //CKSVII2C_IC_STATUS #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT … #define CKSVII2C_IC_STATUS__TFNF__SHIFT … #define CKSVII2C_IC_STATUS__TFE__SHIFT … #define CKSVII2C_IC_STATUS__RFNE__SHIFT … #define CKSVII2C_IC_STATUS__RFF__SHIFT … #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT … #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT … #define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY__SHIFT … #define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL__SHIFT … #define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY__SHIFT … #define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT … #define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED__SHIFT … #define CKSVII2C_IC_STATUS__ACTIVITY_MASK … #define CKSVII2C_IC_STATUS__TFNF_MASK … #define CKSVII2C_IC_STATUS__TFE_MASK … #define CKSVII2C_IC_STATUS__RFNE_MASK … #define CKSVII2C_IC_STATUS__RFF_MASK … #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK … #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK … #define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY_MASK … #define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL_MASK … #define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY_MASK … #define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL_MASK … #define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED_MASK … //CKSVII2C_IC_TXFLR #define CKSVII2C_IC_TXFLR__TXFLR__SHIFT … #define CKSVII2C_IC_TXFLR__TXFLR_MASK … //CKSVII2C_IC_RXFLR #define CKSVII2C_IC_RXFLR__RXFLR__SHIFT … #define CKSVII2C_IC_RXFLR__RXFLR_MASK … //CKSVII2C_IC_SDA_HOLD #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT … #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT … #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD_MASK … #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD_MASK … //CKSVII2C_IC_TX_ABRT_SOURCE //CKSVII2C_IC_SLV_DATA_NACK_ONLY //CKSVII2C_IC_DMA_CR //CKSVII2C_IC_DMA_TDLR //CKSVII2C_IC_DMA_RDLR //CKSVII2C_IC_SDA_SETUP #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT … #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK … //CKSVII2C_IC_ACK_GENERAL_CALL #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT … #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK … //CKSVII2C_IC_ENABLE_STATUS #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT … #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT … #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT … #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK … #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY_MASK … #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST_MASK … //CKSVII2C_IC_FS_SPKLEN #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT … #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK … //CKSVII2C_IC_HS_SPKLEN #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT … #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK … //CKSVII2C_IC_CLR_RESTART_DET //CKSVII2C_IC_COMP_PARAM_1 #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT … #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH_MASK … #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE_MASK … #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES_MASK … #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO_MASK … #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA_MASK … #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS_MASK … #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH_MASK … #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH_MASK … //CKSVII2C_IC_COMP_VERSION #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT … #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK … //CKSVII2C_IC_COMP_TYPE #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT … #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK … //CKSVII2C1_IC_CON #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT … #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT … #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT … #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT … #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT … #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT … #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT … #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT … #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT … #define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1__SHIFT … #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK … #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK … #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK … #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK … #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK … #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK … #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK … #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK … #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK … #define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1_MASK … //CKSVII2C1_IC_TAR #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT … #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT … #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT … #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT … #define CKSVII2C1_IC_TAR__IC1_TAR_MASK … #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK … #define CKSVII2C1_IC_TAR__SPECIAL1_MASK … #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK … //CKSVII2C1_IC_SAR #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT … #define CKSVII2C1_IC_SAR__IC1_SAR_MASK … //CKSVII2C1_IC_HS_MADDR #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT … #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK … //CKSVII2C1_IC_DATA_CMD #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT … #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT … #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT … #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT … #define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE__SHIFT … #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK … #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK … #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK … #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK … #define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE_MASK … //CKSVII2C1_IC_SS_SCL_HCNT #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT … #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK … //CKSVII2C1_IC_SS_SCL_LCNT #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT … #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK … //CKSVII2C1_IC_FS_SCL_HCNT #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT … #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK … //CKSVII2C1_IC_FS_SCL_LCNT #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT … #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK … //CKSVII2C1_IC_HS_SCL_HCNT #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT … #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK … //CKSVII2C1_IC_HS_SCL_LCNT #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT … #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK … //CKSVII2C1_IC_INTR_STAT #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW__SHIFT … #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK … #define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW_MASK … //CKSVII2C1_IC_INTR_MASK #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW__SHIFT … #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK … #define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW_MASK … //CKSVII2C1_IC_RAW_INTR_STAT //CKSVII2C1_IC_RX_TL #define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT … #define CKSVII2C1_IC_RX_TL__RX1_TL_MASK … //CKSVII2C1_IC_TX_TL #define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT … #define CKSVII2C1_IC_TX_TL__TX1_TL_MASK … //CKSVII2C1_IC_CLR_INTR //CKSVII2C1_IC_CLR_RX_UNDER //CKSVII2C1_IC_CLR_RX_OVER //CKSVII2C1_IC_CLR_TX_OVER //CKSVII2C1_IC_CLR_RD_REQ //CKSVII2C1_IC_CLR_TX_ABRT //CKSVII2C1_IC_CLR_RX_DONE //CKSVII2C1_IC_CLR_ACTIVITY //CKSVII2C1_IC_CLR_STOP_DET //CKSVII2C1_IC_CLR_START_DET //CKSVII2C1_IC_CLR_GEN_CALL //CKSVII2C1_IC_ENABLE #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT … #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT … #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT … #define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE__SHIFT … #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK … #define CKSVII2C1_IC_ENABLE__ABORT1_MASK … #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK_MASK … #define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE_MASK … //CKSVII2C1_IC_STATUS #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT … #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT … #define CKSVII2C1_IC_STATUS__TFE1__SHIFT … #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT … #define CKSVII2C1_IC_STATUS__RFF1__SHIFT … #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT … #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT … #define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY__SHIFT … #define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL__SHIFT … #define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY__SHIFT … #define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL__SHIFT … #define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED__SHIFT … #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK … #define CKSVII2C1_IC_STATUS__TFNF1_MASK … #define CKSVII2C1_IC_STATUS__TFE1_MASK … #define CKSVII2C1_IC_STATUS__RFNE1_MASK … #define CKSVII2C1_IC_STATUS__RFF1_MASK … #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK … #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK … #define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY_MASK … #define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL_MASK … #define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY_MASK … #define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL_MASK … #define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED_MASK … //CKSVII2C1_IC_TXFLR #define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT … #define CKSVII2C1_IC_TXFLR__TXFLR1_MASK … //CKSVII2C1_IC_RXFLR #define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT … #define CKSVII2C1_IC_RXFLR__RXFLR1_MASK … //CKSVII2C1_IC_SDA_HOLD #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT … #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT … #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD_MASK … #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD_MASK … //CKSVII2C1_IC_TX_ABRT_SOURCE //CKSVII2C1_IC_SLV_DATA_NACK_ONLY //CKSVII2C1_IC_DMA_CR //CKSVII2C1_IC_DMA_TDLR //CKSVII2C1_IC_DMA_RDLR //CKSVII2C1_IC_SDA_SETUP #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT … #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK … //CKSVII2C1_IC_ACK_GENERAL_CALL #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT … #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK … //CKSVII2C1_IC_ENABLE_STATUS #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT … #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT … #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT … #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK … #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY_MASK … #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST_MASK … //CKSVII2C1_IC_FS_SPKLEN #define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN__SHIFT … #define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN_MASK … //CKSVII2C1_IC_HS_SPKLEN #define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN__SHIFT … #define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN_MASK … //CKSVII2C1_IC_CLR_RESTART_DET //CKSVII2C1_IC_COMP_PARAM_1 #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT … #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH_MASK … #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH_MASK … //CKSVII2C1_IC_COMP_VERSION #define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION__SHIFT … #define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION_MASK … //CKSVII2C1_IC_COMP_TYPE #define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE__SHIFT … #define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE_MASK … //SMUIO_PWRMGT #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT … #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT … #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK … #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK … // addressBlock: smuio_smuio_rom_SmuSmuioDec //ROM_CNTL #define ROM_CNTL__CLOCK_GATING_EN__SHIFT … #define ROM_CNTL__READ_MODE__SHIFT … #define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT … #define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT … #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT … #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT … #define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT … #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT … #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT … #define ROM_CNTL__SPI_FAST_MODE__SHIFT … #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT … #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT … #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT … #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT … #define ROM_CNTL__PAD_SAMPLE_MODE__SHIFT … #define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE__SHIFT … #define ROM_CNTL__CLOCK_GATING_EN_MASK … #define ROM_CNTL__READ_MODE_MASK … #define ROM_CNTL__READ_MODE_OVERRIDE_MASK … #define ROM_CNTL__SPI_TIMING_RELAX_SCK_MASK … #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE_MASK … #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE_MASK … #define ROM_CNTL__DUMMY_CYCLE_NUM_MASK … #define ROM_CNTL__SPI_TIMING_RELAX_MASK … #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK … #define ROM_CNTL__SPI_FAST_MODE_MASK … #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK … #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK … #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK … #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE_MASK … #define ROM_CNTL__PAD_SAMPLE_MODE_MASK … #define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE_MASK … //PAGE_MIRROR_CNTL #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK … #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK … //ROM_STATUS #define ROM_STATUS__ROM_BUSY__SHIFT … #define ROM_STATUS__ROM_BUSY_MASK … //CGTT_ROM_CLK_CTRL0 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT … #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT … #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT … #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT … #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK … #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK … #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK … #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK … //ROM_INDEX #define ROM_INDEX__ROM_INDEX__SHIFT … #define ROM_INDEX__ROM_INDEX_MASK … //ROM_DATA #define ROM_DATA__ROM_DATA__SHIFT … #define ROM_DATA__ROM_DATA_MASK … //ROM_START #define ROM_START__ROM_START__SHIFT … #define ROM_START__ROM_START_MASK … //ROM_SW_CNTL #define ROM_SW_CNTL__DATA_SIZE__SHIFT … #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT … #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT … #define ROM_SW_CNTL__DATA_SIZE_MASK … #define ROM_SW_CNTL__COMMAND_SIZE_MASK … #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK … //ROM_SW_STATUS #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT … #define ROM_SW_STATUS__ROM_SW_DONE_MASK … //ROM_SW_COMMAND #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT … #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT … #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK … #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK … //ROM_SW_DATA_1 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_1__ROM_SW_DATA_MASK … //ROM_SW_DATA_2 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_2__ROM_SW_DATA_MASK … //ROM_SW_DATA_3 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_3__ROM_SW_DATA_MASK … //ROM_SW_DATA_4 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_4__ROM_SW_DATA_MASK … //ROM_SW_DATA_5 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_5__ROM_SW_DATA_MASK … //ROM_SW_DATA_6 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_6__ROM_SW_DATA_MASK … //ROM_SW_DATA_7 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_7__ROM_SW_DATA_MASK … //ROM_SW_DATA_8 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_8__ROM_SW_DATA_MASK … //ROM_SW_DATA_9 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_9__ROM_SW_DATA_MASK … //ROM_SW_DATA_10 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_10__ROM_SW_DATA_MASK … //ROM_SW_DATA_11 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_11__ROM_SW_DATA_MASK … //ROM_SW_DATA_12 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_12__ROM_SW_DATA_MASK … //ROM_SW_DATA_13 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_13__ROM_SW_DATA_MASK … //ROM_SW_DATA_14 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_14__ROM_SW_DATA_MASK … //ROM_SW_DATA_15 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_15__ROM_SW_DATA_MASK … //ROM_SW_DATA_16 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_16__ROM_SW_DATA_MASK … //ROM_SW_DATA_17 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_17__ROM_SW_DATA_MASK … //ROM_SW_DATA_18 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_18__ROM_SW_DATA_MASK … //ROM_SW_DATA_19 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_19__ROM_SW_DATA_MASK … //ROM_SW_DATA_20 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_20__ROM_SW_DATA_MASK … //ROM_SW_DATA_21 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_21__ROM_SW_DATA_MASK … //ROM_SW_DATA_22 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_22__ROM_SW_DATA_MASK … //ROM_SW_DATA_23 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_23__ROM_SW_DATA_MASK … //ROM_SW_DATA_24 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_24__ROM_SW_DATA_MASK … //ROM_SW_DATA_25 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_25__ROM_SW_DATA_MASK … //ROM_SW_DATA_26 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_26__ROM_SW_DATA_MASK … //ROM_SW_DATA_27 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_27__ROM_SW_DATA_MASK … //ROM_SW_DATA_28 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_28__ROM_SW_DATA_MASK … //ROM_SW_DATA_29 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_29__ROM_SW_DATA_MASK … //ROM_SW_DATA_30 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_30__ROM_SW_DATA_MASK … //ROM_SW_DATA_31 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_31__ROM_SW_DATA_MASK … //ROM_SW_DATA_32 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_32__ROM_SW_DATA_MASK … //ROM_SW_DATA_33 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_33__ROM_SW_DATA_MASK … //ROM_SW_DATA_34 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_34__ROM_SW_DATA_MASK … //ROM_SW_DATA_35 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_35__ROM_SW_DATA_MASK … //ROM_SW_DATA_36 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_36__ROM_SW_DATA_MASK … //ROM_SW_DATA_37 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_37__ROM_SW_DATA_MASK … //ROM_SW_DATA_38 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_38__ROM_SW_DATA_MASK … //ROM_SW_DATA_39 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_39__ROM_SW_DATA_MASK … //ROM_SW_DATA_40 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_40__ROM_SW_DATA_MASK … //ROM_SW_DATA_41 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_41__ROM_SW_DATA_MASK … //ROM_SW_DATA_42 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_42__ROM_SW_DATA_MASK … //ROM_SW_DATA_43 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_43__ROM_SW_DATA_MASK … //ROM_SW_DATA_44 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_44__ROM_SW_DATA_MASK … //ROM_SW_DATA_45 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_45__ROM_SW_DATA_MASK … //ROM_SW_DATA_46 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_46__ROM_SW_DATA_MASK … //ROM_SW_DATA_47 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_47__ROM_SW_DATA_MASK … //ROM_SW_DATA_48 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_48__ROM_SW_DATA_MASK … //ROM_SW_DATA_49 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_49__ROM_SW_DATA_MASK … //ROM_SW_DATA_50 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_50__ROM_SW_DATA_MASK … //ROM_SW_DATA_51 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_51__ROM_SW_DATA_MASK … //ROM_SW_DATA_52 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_52__ROM_SW_DATA_MASK … //ROM_SW_DATA_53 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_53__ROM_SW_DATA_MASK … //ROM_SW_DATA_54 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_54__ROM_SW_DATA_MASK … //ROM_SW_DATA_55 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_55__ROM_SW_DATA_MASK … //ROM_SW_DATA_56 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_56__ROM_SW_DATA_MASK … //ROM_SW_DATA_57 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_57__ROM_SW_DATA_MASK … //ROM_SW_DATA_58 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_58__ROM_SW_DATA_MASK … //ROM_SW_DATA_59 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_59__ROM_SW_DATA_MASK … //ROM_SW_DATA_60 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_60__ROM_SW_DATA_MASK … //ROM_SW_DATA_61 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_61__ROM_SW_DATA_MASK … //ROM_SW_DATA_62 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_62__ROM_SW_DATA_MASK … //ROM_SW_DATA_63 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_63__ROM_SW_DATA_MASK … //ROM_SW_DATA_64 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT … #define ROM_SW_DATA_64__ROM_SW_DATA_MASK … // addressBlock: smuio_smuio_gpio_SmuSmuioDec //SMU_GPIOPAD_SW_INT_STAT #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT … #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK … //SMU_GPIOPAD_MASK #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT … #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK … //SMU_GPIOPAD_A #define SMU_GPIOPAD_A__GPIO_A__SHIFT … #define SMU_GPIOPAD_A__GPIO_A_MASK … //SMU_GPIOPAD_TXIMPSEL #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT … #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK … //SMU_GPIOPAD_EN #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT … #define SMU_GPIOPAD_EN__GPIO_EN_MASK … //SMU_GPIOPAD_Y #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT … #define SMU_GPIOPAD_Y__GPIO_Y_MASK … //SMU_GPIOPAD_RXEN #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT … #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK … //SMU_GPIOPAD_RCVR_SEL0 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT … #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK … //SMU_GPIOPAD_RCVR_SEL1 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT … #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK … //SMU_GPIOPAD_PU_EN #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT … #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK … //SMU_GPIOPAD_PD_EN #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT … #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK … //SMU_GPIOPAD_PINSTRAPS #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK … #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK … //DFT_PINSTRAPS #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT … #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK … //SMU_GPIOPAD_INT_STAT_EN #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT … #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT … #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK … #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK … //SMU_GPIOPAD_INT_STAT #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT … #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT … #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK … #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK … //SMU_GPIOPAD_INT_STAT_AK #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK … #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK … #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK … //SMU_GPIOPAD_INT_EN #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT … #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT … #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK … #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK … //SMU_GPIOPAD_INT_TYPE #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT … #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT … #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK … #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK … //SMU_GPIOPAD_INT_POLARITY #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT … #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT … #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK … #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK … //SMUIO_PCC_GPIO_SELECT #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT … #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK … //SMU_GPIOPAD_S0 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT … #define SMU_GPIOPAD_S0__GPIO_S0_MASK … //SMU_GPIOPAD_S1 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT … #define SMU_GPIOPAD_S1__GPIO_S1_MASK … //SMU_GPIOPAD_SCHMEN #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT … #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK … //SMU_GPIOPAD_SCL_EN #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT … #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK … //SMU_GPIOPAD_SDA_EN #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT … #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK … //SMUIO_GPIO_INT0_SELECT #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT … #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK … //SMUIO_GPIO_INT1_SELECT #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT … #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK … //SMUIO_GPIO_INT2_SELECT #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT … #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK … //SMUIO_GPIO_INT3_SELECT #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT … #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK … //SMU_GPIOPAD_MP_INT0_STAT #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT … #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK … //SMU_GPIOPAD_MP_INT1_STAT #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT … #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK … //SMU_GPIOPAD_MP_INT2_STAT #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT … #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK … //SMU_GPIOPAD_MP_INT3_STAT #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT … #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK … //SMIO_INDEX #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT … #define SMIO_INDEX__SW_SMIO_INDEX_MASK … //S0_VID_SMIO_CNTL #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT … #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK … //S1_VID_SMIO_CNTL #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT … #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK … //OPEN_DRAIN_SELECT #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT … #define OPEN_DRAIN_SELECT__RESERVED__SHIFT … #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK … #define OPEN_DRAIN_SELECT__RESERVED_MASK … //SMIO_ENABLE #define SMIO_ENABLE__SMIO_ENABLE__SHIFT … #define SMIO_ENABLE__SMIO_ENABLE_MASK … #endif
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