/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/pci.h> #include <drm/drm_cache.h> #include "amdgpu.h" #include "amdgpu_atomfirmware.h" #include "gmc_v10_0.h" #include "umc_v8_7.h" #include "athub/athub_2_0_0_sh_mask.h" #include "athub/athub_2_0_0_offset.h" #include "dcn/dcn_2_0_0_offset.h" #include "dcn/dcn_2_0_0_sh_mask.h" #include "oss/osssys_5_0_0_offset.h" #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" #include "navi10_enum.h" #include "soc15.h" #include "soc15d.h" #include "soc15_common.h" #include "nbio_v2_3.h" #include "gfxhub_v2_0.h" #include "gfxhub_v2_1.h" #include "mmhub_v2_0.h" #include "mmhub_v2_3.h" #include "athub_v2_0.h" #include "athub_v2_1.h" static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) { … } static int gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) { … } static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = …; static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = …; static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) { … } /** * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore * * @adev: amdgpu_device pointer * @vmhub: vmhub type * */ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, uint32_t vmhub) { … } static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) { … } /* * GART * VMID 0 is the physical GPU addresses as used by the kernel. * VMIDs 1-15 are used for userspace clients and are handled * by the amdgpu vm/hsa code. */ /** * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback * * @adev: amdgpu_device pointer * @vmid: vm instance to flush * @vmhub: vmhub type * @flush_type: the flush type * * Flush the TLB for the requested page table. */ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { … } /** * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid * * @adev: amdgpu_device pointer * @pasid: pasid to be flush * @flush_type: the flush type * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() * @inst: is used to select which instance of KIQ to use for the invalidation * * Flush the TLB for the requested pasid. */ static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) { … } static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) { … } /* * PTE format on NAVI 10: * 63:59 reserved * 58 reserved and for sienna_cichlid is used for MALL noalloc * 57 reserved * 56 F * 55 L * 54 reserved * 53:52 SW * 51 T * 50:48 mtype * 47:12 4k physical page base address * 11:7 fragment * 6 write * 5 read * 4 exe * 3 Z * 2 snooped * 1 system * 0 valid * * PDE format on NAVI 10: * 63:59 block fragment size * 58:55 reserved * 54 P * 53:48 reserved * 47:6 physical base address of PD or PTE * 5:3 reserved * 2 C * 1 system * 0 valid */ static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) { … } static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { … } static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping, uint64_t *flags) { … } static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) { … } static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = …; static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) { … } static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) { … } static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) { … } static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) { … } static int gmc_v10_0_early_init(void *handle) { … } static int gmc_v10_0_late_init(void *handle) { … } static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) { … } /** * gmc_v10_0_mc_init - initialize the memory controller driver params * * @adev: amdgpu_device pointer * * Look up the amount of vram, vram width, and decide how to place * vram and gart within the GPU's physical address space. * Returns 0 for success. */ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) { … } static int gmc_v10_0_gart_init(struct amdgpu_device *adev) { … } static int gmc_v10_0_sw_init(void *handle) { … } /** * gmc_v10_0_gart_fini - vm fini callback * * @adev: amdgpu_device pointer * * Tears down the driver GART/VM setup (CIK). */ static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) { … } static int gmc_v10_0_sw_fini(void *handle) { … } static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) { … } /** * gmc_v10_0_gart_enable - gart enable * * @adev: amdgpu_device pointer */ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) { … } static int gmc_v10_0_hw_init(void *handle) { … } /** * gmc_v10_0_gart_disable - gart disable * * @adev: amdgpu_device pointer * * This disables all VM page table. */ static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) { … } static int gmc_v10_0_hw_fini(void *handle) { … } static int gmc_v10_0_suspend(void *handle) { … } static int gmc_v10_0_resume(void *handle) { … } static bool gmc_v10_0_is_idle(void *handle) { … } static int gmc_v10_0_wait_for_idle(void *handle) { … } static int gmc_v10_0_soft_reset(void *handle) { … } static int gmc_v10_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) { … } static int gmc_v10_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } const struct amd_ip_funcs gmc_v10_0_ip_funcs = …; const struct amdgpu_ip_block_version gmc_v10_0_ip_block = …;
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