linux/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _sdma_4_4_0_OFFSET_HEADER
#define _sdma_4_4_0_OFFSET_HEADER


// addressBlock: sdma0_sdma0dec
// base address: 0x4980
#define regSDMA0_UCODE_ADDR
#define regSDMA0_UCODE_ADDR_BASE_IDX
#define regSDMA0_UCODE_DATA
#define regSDMA0_UCODE_DATA_BASE_IDX
#define regSDMA0_VF_ENABLE
#define regSDMA0_VF_ENABLE_BASE_IDX
#define regSDMA0_CONTEXT_GROUP_BOUNDARY
#define regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define regSDMA0_POWER_CNTL
#define regSDMA0_POWER_CNTL_BASE_IDX
#define regSDMA0_CLK_CTRL
#define regSDMA0_CLK_CTRL_BASE_IDX
#define regSDMA0_CNTL
#define regSDMA0_CNTL_BASE_IDX
#define regSDMA0_CHICKEN_BITS
#define regSDMA0_CHICKEN_BITS_BASE_IDX
#define regSDMA0_GB_ADDR_CONFIG
#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX
#define regSDMA0_GB_ADDR_CONFIG_READ
#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX
#define regSDMA0_RB_RPTR_FETCH_HI
#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX
#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define regSDMA0_RB_RPTR_FETCH
#define regSDMA0_RB_RPTR_FETCH_BASE_IDX
#define regSDMA0_IB_OFFSET_FETCH
#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX
#define regSDMA0_PROGRAM
#define regSDMA0_PROGRAM_BASE_IDX
#define regSDMA0_STATUS_REG
#define regSDMA0_STATUS_REG_BASE_IDX
#define regSDMA0_STATUS1_REG
#define regSDMA0_STATUS1_REG_BASE_IDX
#define regSDMA0_RD_BURST_CNTL
#define regSDMA0_RD_BURST_CNTL_BASE_IDX
#define regSDMA0_HBM_PAGE_CONFIG
#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX
#define regSDMA0_UCODE_CHECKSUM
#define regSDMA0_UCODE_CHECKSUM_BASE_IDX
#define regSDMA0_F32_CNTL
#define regSDMA0_F32_CNTL_BASE_IDX
#define regSDMA0_FREEZE
#define regSDMA0_FREEZE_BASE_IDX
#define regSDMA0_PHASE0_QUANTUM
#define regSDMA0_PHASE0_QUANTUM_BASE_IDX
#define regSDMA0_PHASE1_QUANTUM
#define regSDMA0_PHASE1_QUANTUM_BASE_IDX
#define regSDMA_POWER_GATING
#define regSDMA_POWER_GATING_BASE_IDX
#define regSDMA_PGFSM_CONFIG
#define regSDMA_PGFSM_CONFIG_BASE_IDX
#define regSDMA_PGFSM_WRITE
#define regSDMA_PGFSM_WRITE_BASE_IDX
#define regSDMA_PGFSM_READ
#define regSDMA_PGFSM_READ_BASE_IDX
#define regCC_SDMA0_EDC_CONFIG
#define regCC_SDMA0_EDC_CONFIG_BASE_IDX
#define regSDMA0_BA_THRESHOLD
#define regSDMA0_BA_THRESHOLD_BASE_IDX
#define regSDMA0_ID
#define regSDMA0_ID_BASE_IDX
#define regSDMA0_VERSION
#define regSDMA0_VERSION_BASE_IDX
#define regSDMA0_EDC_COUNTER
#define regSDMA0_EDC_COUNTER_BASE_IDX
#define regSDMA0_EDC_COUNTER2
#define regSDMA0_EDC_COUNTER2_BASE_IDX
#define regSDMA0_STATUS2_REG
#define regSDMA0_STATUS2_REG_BASE_IDX
#define regSDMA0_ATOMIC_CNTL
#define regSDMA0_ATOMIC_CNTL_BASE_IDX
#define regSDMA0_ATOMIC_PREOP_LO
#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX
#define regSDMA0_ATOMIC_PREOP_HI
#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX
#define regSDMA0_UTCL1_CNTL
#define regSDMA0_UTCL1_CNTL_BASE_IDX
#define regSDMA0_UTCL1_WATERMK
#define regSDMA0_UTCL1_WATERMK_BASE_IDX
#define regSDMA0_UTCL1_RD_STATUS
#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX
#define regSDMA0_UTCL1_WR_STATUS
#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX
#define regSDMA0_UTCL1_INV0
#define regSDMA0_UTCL1_INV0_BASE_IDX
#define regSDMA0_UTCL1_INV1
#define regSDMA0_UTCL1_INV1_BASE_IDX
#define regSDMA0_UTCL1_INV2
#define regSDMA0_UTCL1_INV2_BASE_IDX
#define regSDMA0_UTCL1_RD_XNACK0
#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX
#define regSDMA0_UTCL1_RD_XNACK1
#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX
#define regSDMA0_UTCL1_WR_XNACK0
#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX
#define regSDMA0_UTCL1_WR_XNACK1
#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX
#define regSDMA0_UTCL1_TIMEOUT
#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX
#define regSDMA0_UTCL1_PAGE
#define regSDMA0_UTCL1_PAGE_BASE_IDX
#define regSDMA0_POWER_CNTL_IDLE
#define regSDMA0_POWER_CNTL_IDLE_BASE_IDX
#define regSDMA0_RELAX_ORDERING_LUT
#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX
#define regSDMA0_CHICKEN_BITS_2
#define regSDMA0_CHICKEN_BITS_2_BASE_IDX
#define regSDMA0_STATUS3_REG
#define regSDMA0_STATUS3_REG_BASE_IDX
#define regSDMA0_PHYSICAL_ADDR_LO
#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX
#define regSDMA0_PHYSICAL_ADDR_HI
#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX
#define regSDMA0_PHASE2_QUANTUM
#define regSDMA0_PHASE2_QUANTUM_BASE_IDX
#define regSDMA0_ERROR_LOG
#define regSDMA0_ERROR_LOG_BASE_IDX
#define regSDMA0_PUB_DUMMY_REG0
#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX
#define regSDMA0_PUB_DUMMY_REG1
#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX
#define regSDMA0_PUB_DUMMY_REG2
#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX
#define regSDMA0_PUB_DUMMY_REG3
#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX
#define regSDMA0_F32_COUNTER
#define regSDMA0_F32_COUNTER_BASE_IDX
#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG
#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX
#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG
#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX
#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX
#define regSDMA0_PERFCNT_MISC_CNTL
#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX
#define regSDMA0_PERFCNT_PERFCOUNTER_LO
#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX
#define regSDMA0_PERFCNT_PERFCOUNTER_HI
#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX
#define regSDMA0_CRD_CNTL
#define regSDMA0_CRD_CNTL_BASE_IDX
#define regSDMA0_ULV_CNTL
#define regSDMA0_ULV_CNTL_BASE_IDX
#define regSDMA0_EA_DBIT_ADDR_DATA
#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX
#define regSDMA0_EA_DBIT_ADDR_INDEX
#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX
#define regSDMA0_STATUS4_REG
#define regSDMA0_STATUS4_REG_BASE_IDX
#define regSDMA0_SCRATCH_RAM_DATA
#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX
#define regSDMA0_SCRATCH_RAM_ADDR
#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX
#define regSDMA0_CE_CTRL
#define regSDMA0_CE_CTRL_BASE_IDX
#define regSDMA0_RAS_STATUS
#define regSDMA0_RAS_STATUS_BASE_IDX
#define regSDMA0_CLK_STATUS
#define regSDMA0_CLK_STATUS_BASE_IDX
#define regSDMA0_GFX_RB_CNTL
#define regSDMA0_GFX_RB_CNTL_BASE_IDX
#define regSDMA0_GFX_RB_BASE
#define regSDMA0_GFX_RB_BASE_BASE_IDX
#define regSDMA0_GFX_RB_BASE_HI
#define regSDMA0_GFX_RB_BASE_HI_BASE_IDX
#define regSDMA0_GFX_RB_RPTR
#define regSDMA0_GFX_RB_RPTR_BASE_IDX
#define regSDMA0_GFX_RB_RPTR_HI
#define regSDMA0_GFX_RB_RPTR_HI_BASE_IDX
#define regSDMA0_GFX_RB_WPTR
#define regSDMA0_GFX_RB_WPTR_BASE_IDX
#define regSDMA0_GFX_RB_WPTR_HI
#define regSDMA0_GFX_RB_WPTR_HI_BASE_IDX
#define regSDMA0_GFX_RB_WPTR_POLL_CNTL
#define regSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_GFX_RB_RPTR_ADDR_HI
#define regSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_GFX_RB_RPTR_ADDR_LO
#define regSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_GFX_IB_CNTL
#define regSDMA0_GFX_IB_CNTL_BASE_IDX
#define regSDMA0_GFX_IB_RPTR
#define regSDMA0_GFX_IB_RPTR_BASE_IDX
#define regSDMA0_GFX_IB_OFFSET
#define regSDMA0_GFX_IB_OFFSET_BASE_IDX
#define regSDMA0_GFX_IB_BASE_LO
#define regSDMA0_GFX_IB_BASE_LO_BASE_IDX
#define regSDMA0_GFX_IB_BASE_HI
#define regSDMA0_GFX_IB_BASE_HI_BASE_IDX
#define regSDMA0_GFX_IB_SIZE
#define regSDMA0_GFX_IB_SIZE_BASE_IDX
#define regSDMA0_GFX_SKIP_CNTL
#define regSDMA0_GFX_SKIP_CNTL_BASE_IDX
#define regSDMA0_GFX_CONTEXT_STATUS
#define regSDMA0_GFX_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_GFX_DOORBELL
#define regSDMA0_GFX_DOORBELL_BASE_IDX
#define regSDMA0_GFX_CONTEXT_CNTL
#define regSDMA0_GFX_CONTEXT_CNTL_BASE_IDX
#define regSDMA0_GFX_STATUS
#define regSDMA0_GFX_STATUS_BASE_IDX
#define regSDMA0_GFX_DOORBELL_LOG
#define regSDMA0_GFX_DOORBELL_LOG_BASE_IDX
#define regSDMA0_GFX_WATERMARK
#define regSDMA0_GFX_WATERMARK_BASE_IDX
#define regSDMA0_GFX_DOORBELL_OFFSET
#define regSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_GFX_CSA_ADDR_LO
#define regSDMA0_GFX_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_GFX_CSA_ADDR_HI
#define regSDMA0_GFX_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_GFX_IB_SUB_REMAIN
#define regSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_GFX_PREEMPT
#define regSDMA0_GFX_PREEMPT_BASE_IDX
#define regSDMA0_GFX_DUMMY_REG
#define regSDMA0_GFX_DUMMY_REG_BASE_IDX
#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_GFX_RB_AQL_CNTL
#define regSDMA0_GFX_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_GFX_MINOR_PTR_UPDATE
#define regSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA0
#define regSDMA0_GFX_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA1
#define regSDMA0_GFX_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA2
#define regSDMA0_GFX_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA3
#define regSDMA0_GFX_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA4
#define regSDMA0_GFX_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA5
#define regSDMA0_GFX_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA6
#define regSDMA0_GFX_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA7
#define regSDMA0_GFX_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA8
#define regSDMA0_GFX_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA9
#define regSDMA0_GFX_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_GFX_MIDCMD_DATA10
#define regSDMA0_GFX_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_GFX_MIDCMD_CNTL
#define regSDMA0_GFX_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_PAGE_RB_CNTL
#define regSDMA0_PAGE_RB_CNTL_BASE_IDX
#define regSDMA0_PAGE_RB_BASE
#define regSDMA0_PAGE_RB_BASE_BASE_IDX
#define regSDMA0_PAGE_RB_BASE_HI
#define regSDMA0_PAGE_RB_BASE_HI_BASE_IDX
#define regSDMA0_PAGE_RB_RPTR
#define regSDMA0_PAGE_RB_RPTR_BASE_IDX
#define regSDMA0_PAGE_RB_RPTR_HI
#define regSDMA0_PAGE_RB_RPTR_HI_BASE_IDX
#define regSDMA0_PAGE_RB_WPTR
#define regSDMA0_PAGE_RB_WPTR_BASE_IDX
#define regSDMA0_PAGE_RB_WPTR_HI
#define regSDMA0_PAGE_RB_WPTR_HI_BASE_IDX
#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL
#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_PAGE_RB_RPTR_ADDR_HI
#define regSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_PAGE_RB_RPTR_ADDR_LO
#define regSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_PAGE_IB_CNTL
#define regSDMA0_PAGE_IB_CNTL_BASE_IDX
#define regSDMA0_PAGE_IB_RPTR
#define regSDMA0_PAGE_IB_RPTR_BASE_IDX
#define regSDMA0_PAGE_IB_OFFSET
#define regSDMA0_PAGE_IB_OFFSET_BASE_IDX
#define regSDMA0_PAGE_IB_BASE_LO
#define regSDMA0_PAGE_IB_BASE_LO_BASE_IDX
#define regSDMA0_PAGE_IB_BASE_HI
#define regSDMA0_PAGE_IB_BASE_HI_BASE_IDX
#define regSDMA0_PAGE_IB_SIZE
#define regSDMA0_PAGE_IB_SIZE_BASE_IDX
#define regSDMA0_PAGE_SKIP_CNTL
#define regSDMA0_PAGE_SKIP_CNTL_BASE_IDX
#define regSDMA0_PAGE_CONTEXT_STATUS
#define regSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_PAGE_DOORBELL
#define regSDMA0_PAGE_DOORBELL_BASE_IDX
#define regSDMA0_PAGE_STATUS
#define regSDMA0_PAGE_STATUS_BASE_IDX
#define regSDMA0_PAGE_DOORBELL_LOG
#define regSDMA0_PAGE_DOORBELL_LOG_BASE_IDX
#define regSDMA0_PAGE_WATERMARK
#define regSDMA0_PAGE_WATERMARK_BASE_IDX
#define regSDMA0_PAGE_DOORBELL_OFFSET
#define regSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_PAGE_CSA_ADDR_LO
#define regSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_PAGE_CSA_ADDR_HI
#define regSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_PAGE_IB_SUB_REMAIN
#define regSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_PAGE_PREEMPT
#define regSDMA0_PAGE_PREEMPT_BASE_IDX
#define regSDMA0_PAGE_DUMMY_REG
#define regSDMA0_PAGE_DUMMY_REG_BASE_IDX
#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_PAGE_RB_AQL_CNTL
#define regSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_PAGE_MINOR_PTR_UPDATE
#define regSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA0
#define regSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA1
#define regSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA2
#define regSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA3
#define regSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA4
#define regSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA5
#define regSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA6
#define regSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA7
#define regSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA8
#define regSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA9
#define regSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_DATA10
#define regSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_PAGE_MIDCMD_CNTL
#define regSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC0_RB_CNTL
#define regSDMA0_RLC0_RB_CNTL_BASE_IDX
#define regSDMA0_RLC0_RB_BASE
#define regSDMA0_RLC0_RB_BASE_BASE_IDX
#define regSDMA0_RLC0_RB_BASE_HI
#define regSDMA0_RLC0_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC0_RB_RPTR
#define regSDMA0_RLC0_RB_RPTR_BASE_IDX
#define regSDMA0_RLC0_RB_RPTR_HI
#define regSDMA0_RLC0_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC0_RB_WPTR
#define regSDMA0_RLC0_RB_WPTR_BASE_IDX
#define regSDMA0_RLC0_RB_WPTR_HI
#define regSDMA0_RLC0_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC0_RB_RPTR_ADDR_HI
#define regSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC0_RB_RPTR_ADDR_LO
#define regSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC0_IB_CNTL
#define regSDMA0_RLC0_IB_CNTL_BASE_IDX
#define regSDMA0_RLC0_IB_RPTR
#define regSDMA0_RLC0_IB_RPTR_BASE_IDX
#define regSDMA0_RLC0_IB_OFFSET
#define regSDMA0_RLC0_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC0_IB_BASE_LO
#define regSDMA0_RLC0_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC0_IB_BASE_HI
#define regSDMA0_RLC0_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC0_IB_SIZE
#define regSDMA0_RLC0_IB_SIZE_BASE_IDX
#define regSDMA0_RLC0_SKIP_CNTL
#define regSDMA0_RLC0_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC0_CONTEXT_STATUS
#define regSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC0_DOORBELL
#define regSDMA0_RLC0_DOORBELL_BASE_IDX
#define regSDMA0_RLC0_STATUS
#define regSDMA0_RLC0_STATUS_BASE_IDX
#define regSDMA0_RLC0_DOORBELL_LOG
#define regSDMA0_RLC0_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC0_WATERMARK
#define regSDMA0_RLC0_WATERMARK_BASE_IDX
#define regSDMA0_RLC0_DOORBELL_OFFSET
#define regSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC0_CSA_ADDR_LO
#define regSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC0_CSA_ADDR_HI
#define regSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC0_IB_SUB_REMAIN
#define regSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC0_PREEMPT
#define regSDMA0_RLC0_PREEMPT_BASE_IDX
#define regSDMA0_RLC0_DUMMY_REG
#define regSDMA0_RLC0_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC0_RB_AQL_CNTL
#define regSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC0_MINOR_PTR_UPDATE
#define regSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA0
#define regSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA1
#define regSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA2
#define regSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA3
#define regSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA4
#define regSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA5
#define regSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA6
#define regSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA7
#define regSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA8
#define regSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA9
#define regSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_DATA10
#define regSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC0_MIDCMD_CNTL
#define regSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC1_RB_CNTL
#define regSDMA0_RLC1_RB_CNTL_BASE_IDX
#define regSDMA0_RLC1_RB_BASE
#define regSDMA0_RLC1_RB_BASE_BASE_IDX
#define regSDMA0_RLC1_RB_BASE_HI
#define regSDMA0_RLC1_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC1_RB_RPTR
#define regSDMA0_RLC1_RB_RPTR_BASE_IDX
#define regSDMA0_RLC1_RB_RPTR_HI
#define regSDMA0_RLC1_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC1_RB_WPTR
#define regSDMA0_RLC1_RB_WPTR_BASE_IDX
#define regSDMA0_RLC1_RB_WPTR_HI
#define regSDMA0_RLC1_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC1_RB_RPTR_ADDR_HI
#define regSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC1_RB_RPTR_ADDR_LO
#define regSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC1_IB_CNTL
#define regSDMA0_RLC1_IB_CNTL_BASE_IDX
#define regSDMA0_RLC1_IB_RPTR
#define regSDMA0_RLC1_IB_RPTR_BASE_IDX
#define regSDMA0_RLC1_IB_OFFSET
#define regSDMA0_RLC1_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC1_IB_BASE_LO
#define regSDMA0_RLC1_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC1_IB_BASE_HI
#define regSDMA0_RLC1_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC1_IB_SIZE
#define regSDMA0_RLC1_IB_SIZE_BASE_IDX
#define regSDMA0_RLC1_SKIP_CNTL
#define regSDMA0_RLC1_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC1_CONTEXT_STATUS
#define regSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC1_DOORBELL
#define regSDMA0_RLC1_DOORBELL_BASE_IDX
#define regSDMA0_RLC1_STATUS
#define regSDMA0_RLC1_STATUS_BASE_IDX
#define regSDMA0_RLC1_DOORBELL_LOG
#define regSDMA0_RLC1_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC1_WATERMARK
#define regSDMA0_RLC1_WATERMARK_BASE_IDX
#define regSDMA0_RLC1_DOORBELL_OFFSET
#define regSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC1_CSA_ADDR_LO
#define regSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC1_CSA_ADDR_HI
#define regSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC1_IB_SUB_REMAIN
#define regSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC1_PREEMPT
#define regSDMA0_RLC1_PREEMPT_BASE_IDX
#define regSDMA0_RLC1_DUMMY_REG
#define regSDMA0_RLC1_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC1_RB_AQL_CNTL
#define regSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC1_MINOR_PTR_UPDATE
#define regSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA0
#define regSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA1
#define regSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA2
#define regSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA3
#define regSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA4
#define regSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA5
#define regSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA6
#define regSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA7
#define regSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA8
#define regSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA9
#define regSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_DATA10
#define regSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC1_MIDCMD_CNTL
#define regSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC2_RB_CNTL
#define regSDMA0_RLC2_RB_CNTL_BASE_IDX
#define regSDMA0_RLC2_RB_BASE
#define regSDMA0_RLC2_RB_BASE_BASE_IDX
#define regSDMA0_RLC2_RB_BASE_HI
#define regSDMA0_RLC2_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC2_RB_RPTR
#define regSDMA0_RLC2_RB_RPTR_BASE_IDX
#define regSDMA0_RLC2_RB_RPTR_HI
#define regSDMA0_RLC2_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC2_RB_WPTR
#define regSDMA0_RLC2_RB_WPTR_BASE_IDX
#define regSDMA0_RLC2_RB_WPTR_HI
#define regSDMA0_RLC2_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC2_RB_RPTR_ADDR_HI
#define regSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC2_RB_RPTR_ADDR_LO
#define regSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC2_IB_CNTL
#define regSDMA0_RLC2_IB_CNTL_BASE_IDX
#define regSDMA0_RLC2_IB_RPTR
#define regSDMA0_RLC2_IB_RPTR_BASE_IDX
#define regSDMA0_RLC2_IB_OFFSET
#define regSDMA0_RLC2_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC2_IB_BASE_LO
#define regSDMA0_RLC2_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC2_IB_BASE_HI
#define regSDMA0_RLC2_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC2_IB_SIZE
#define regSDMA0_RLC2_IB_SIZE_BASE_IDX
#define regSDMA0_RLC2_SKIP_CNTL
#define regSDMA0_RLC2_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC2_CONTEXT_STATUS
#define regSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC2_DOORBELL
#define regSDMA0_RLC2_DOORBELL_BASE_IDX
#define regSDMA0_RLC2_STATUS
#define regSDMA0_RLC2_STATUS_BASE_IDX
#define regSDMA0_RLC2_DOORBELL_LOG
#define regSDMA0_RLC2_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC2_WATERMARK
#define regSDMA0_RLC2_WATERMARK_BASE_IDX
#define regSDMA0_RLC2_DOORBELL_OFFSET
#define regSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC2_CSA_ADDR_LO
#define regSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC2_CSA_ADDR_HI
#define regSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC2_IB_SUB_REMAIN
#define regSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC2_PREEMPT
#define regSDMA0_RLC2_PREEMPT_BASE_IDX
#define regSDMA0_RLC2_DUMMY_REG
#define regSDMA0_RLC2_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC2_RB_AQL_CNTL
#define regSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC2_MINOR_PTR_UPDATE
#define regSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA0
#define regSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA1
#define regSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA2
#define regSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA3
#define regSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA4
#define regSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA5
#define regSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA6
#define regSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA7
#define regSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA8
#define regSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA9
#define regSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_DATA10
#define regSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC2_MIDCMD_CNTL
#define regSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC3_RB_CNTL
#define regSDMA0_RLC3_RB_CNTL_BASE_IDX
#define regSDMA0_RLC3_RB_BASE
#define regSDMA0_RLC3_RB_BASE_BASE_IDX
#define regSDMA0_RLC3_RB_BASE_HI
#define regSDMA0_RLC3_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC3_RB_RPTR
#define regSDMA0_RLC3_RB_RPTR_BASE_IDX
#define regSDMA0_RLC3_RB_RPTR_HI
#define regSDMA0_RLC3_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC3_RB_WPTR
#define regSDMA0_RLC3_RB_WPTR_BASE_IDX
#define regSDMA0_RLC3_RB_WPTR_HI
#define regSDMA0_RLC3_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC3_RB_RPTR_ADDR_HI
#define regSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC3_RB_RPTR_ADDR_LO
#define regSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC3_IB_CNTL
#define regSDMA0_RLC3_IB_CNTL_BASE_IDX
#define regSDMA0_RLC3_IB_RPTR
#define regSDMA0_RLC3_IB_RPTR_BASE_IDX
#define regSDMA0_RLC3_IB_OFFSET
#define regSDMA0_RLC3_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC3_IB_BASE_LO
#define regSDMA0_RLC3_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC3_IB_BASE_HI
#define regSDMA0_RLC3_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC3_IB_SIZE
#define regSDMA0_RLC3_IB_SIZE_BASE_IDX
#define regSDMA0_RLC3_SKIP_CNTL
#define regSDMA0_RLC3_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC3_CONTEXT_STATUS
#define regSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC3_DOORBELL
#define regSDMA0_RLC3_DOORBELL_BASE_IDX
#define regSDMA0_RLC3_STATUS
#define regSDMA0_RLC3_STATUS_BASE_IDX
#define regSDMA0_RLC3_DOORBELL_LOG
#define regSDMA0_RLC3_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC3_WATERMARK
#define regSDMA0_RLC3_WATERMARK_BASE_IDX
#define regSDMA0_RLC3_DOORBELL_OFFSET
#define regSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC3_CSA_ADDR_LO
#define regSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC3_CSA_ADDR_HI
#define regSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC3_IB_SUB_REMAIN
#define regSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC3_PREEMPT
#define regSDMA0_RLC3_PREEMPT_BASE_IDX
#define regSDMA0_RLC3_DUMMY_REG
#define regSDMA0_RLC3_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC3_RB_AQL_CNTL
#define regSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC3_MINOR_PTR_UPDATE
#define regSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA0
#define regSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA1
#define regSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA2
#define regSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA3
#define regSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA4
#define regSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA5
#define regSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA6
#define regSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA7
#define regSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA8
#define regSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA9
#define regSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_DATA10
#define regSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC3_MIDCMD_CNTL
#define regSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC4_RB_CNTL
#define regSDMA0_RLC4_RB_CNTL_BASE_IDX
#define regSDMA0_RLC4_RB_BASE
#define regSDMA0_RLC4_RB_BASE_BASE_IDX
#define regSDMA0_RLC4_RB_BASE_HI
#define regSDMA0_RLC4_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC4_RB_RPTR
#define regSDMA0_RLC4_RB_RPTR_BASE_IDX
#define regSDMA0_RLC4_RB_RPTR_HI
#define regSDMA0_RLC4_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC4_RB_WPTR
#define regSDMA0_RLC4_RB_WPTR_BASE_IDX
#define regSDMA0_RLC4_RB_WPTR_HI
#define regSDMA0_RLC4_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC4_RB_RPTR_ADDR_HI
#define regSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC4_RB_RPTR_ADDR_LO
#define regSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC4_IB_CNTL
#define regSDMA0_RLC4_IB_CNTL_BASE_IDX
#define regSDMA0_RLC4_IB_RPTR
#define regSDMA0_RLC4_IB_RPTR_BASE_IDX
#define regSDMA0_RLC4_IB_OFFSET
#define regSDMA0_RLC4_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC4_IB_BASE_LO
#define regSDMA0_RLC4_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC4_IB_BASE_HI
#define regSDMA0_RLC4_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC4_IB_SIZE
#define regSDMA0_RLC4_IB_SIZE_BASE_IDX
#define regSDMA0_RLC4_SKIP_CNTL
#define regSDMA0_RLC4_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC4_CONTEXT_STATUS
#define regSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC4_DOORBELL
#define regSDMA0_RLC4_DOORBELL_BASE_IDX
#define regSDMA0_RLC4_STATUS
#define regSDMA0_RLC4_STATUS_BASE_IDX
#define regSDMA0_RLC4_DOORBELL_LOG
#define regSDMA0_RLC4_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC4_WATERMARK
#define regSDMA0_RLC4_WATERMARK_BASE_IDX
#define regSDMA0_RLC4_DOORBELL_OFFSET
#define regSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC4_CSA_ADDR_LO
#define regSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC4_CSA_ADDR_HI
#define regSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC4_IB_SUB_REMAIN
#define regSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC4_PREEMPT
#define regSDMA0_RLC4_PREEMPT_BASE_IDX
#define regSDMA0_RLC4_DUMMY_REG
#define regSDMA0_RLC4_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC4_RB_AQL_CNTL
#define regSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC4_MINOR_PTR_UPDATE
#define regSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA0
#define regSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA1
#define regSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA2
#define regSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA3
#define regSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA4
#define regSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA5
#define regSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA6
#define regSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA7
#define regSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA8
#define regSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA9
#define regSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_DATA10
#define regSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC4_MIDCMD_CNTL
#define regSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC5_RB_CNTL
#define regSDMA0_RLC5_RB_CNTL_BASE_IDX
#define regSDMA0_RLC5_RB_BASE
#define regSDMA0_RLC5_RB_BASE_BASE_IDX
#define regSDMA0_RLC5_RB_BASE_HI
#define regSDMA0_RLC5_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC5_RB_RPTR
#define regSDMA0_RLC5_RB_RPTR_BASE_IDX
#define regSDMA0_RLC5_RB_RPTR_HI
#define regSDMA0_RLC5_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC5_RB_WPTR
#define regSDMA0_RLC5_RB_WPTR_BASE_IDX
#define regSDMA0_RLC5_RB_WPTR_HI
#define regSDMA0_RLC5_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC5_RB_RPTR_ADDR_HI
#define regSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC5_RB_RPTR_ADDR_LO
#define regSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC5_IB_CNTL
#define regSDMA0_RLC5_IB_CNTL_BASE_IDX
#define regSDMA0_RLC5_IB_RPTR
#define regSDMA0_RLC5_IB_RPTR_BASE_IDX
#define regSDMA0_RLC5_IB_OFFSET
#define regSDMA0_RLC5_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC5_IB_BASE_LO
#define regSDMA0_RLC5_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC5_IB_BASE_HI
#define regSDMA0_RLC5_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC5_IB_SIZE
#define regSDMA0_RLC5_IB_SIZE_BASE_IDX
#define regSDMA0_RLC5_SKIP_CNTL
#define regSDMA0_RLC5_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC5_CONTEXT_STATUS
#define regSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC5_DOORBELL
#define regSDMA0_RLC5_DOORBELL_BASE_IDX
#define regSDMA0_RLC5_STATUS
#define regSDMA0_RLC5_STATUS_BASE_IDX
#define regSDMA0_RLC5_DOORBELL_LOG
#define regSDMA0_RLC5_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC5_WATERMARK
#define regSDMA0_RLC5_WATERMARK_BASE_IDX
#define regSDMA0_RLC5_DOORBELL_OFFSET
#define regSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC5_CSA_ADDR_LO
#define regSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC5_CSA_ADDR_HI
#define regSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC5_IB_SUB_REMAIN
#define regSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC5_PREEMPT
#define regSDMA0_RLC5_PREEMPT_BASE_IDX
#define regSDMA0_RLC5_DUMMY_REG
#define regSDMA0_RLC5_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC5_RB_AQL_CNTL
#define regSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC5_MINOR_PTR_UPDATE
#define regSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA0
#define regSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA1
#define regSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA2
#define regSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA3
#define regSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA4
#define regSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA5
#define regSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA6
#define regSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA7
#define regSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA8
#define regSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA9
#define regSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_DATA10
#define regSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC5_MIDCMD_CNTL
#define regSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC6_RB_CNTL
#define regSDMA0_RLC6_RB_CNTL_BASE_IDX
#define regSDMA0_RLC6_RB_BASE
#define regSDMA0_RLC6_RB_BASE_BASE_IDX
#define regSDMA0_RLC6_RB_BASE_HI
#define regSDMA0_RLC6_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC6_RB_RPTR
#define regSDMA0_RLC6_RB_RPTR_BASE_IDX
#define regSDMA0_RLC6_RB_RPTR_HI
#define regSDMA0_RLC6_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC6_RB_WPTR
#define regSDMA0_RLC6_RB_WPTR_BASE_IDX
#define regSDMA0_RLC6_RB_WPTR_HI
#define regSDMA0_RLC6_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC6_RB_RPTR_ADDR_HI
#define regSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC6_RB_RPTR_ADDR_LO
#define regSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC6_IB_CNTL
#define regSDMA0_RLC6_IB_CNTL_BASE_IDX
#define regSDMA0_RLC6_IB_RPTR
#define regSDMA0_RLC6_IB_RPTR_BASE_IDX
#define regSDMA0_RLC6_IB_OFFSET
#define regSDMA0_RLC6_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC6_IB_BASE_LO
#define regSDMA0_RLC6_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC6_IB_BASE_HI
#define regSDMA0_RLC6_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC6_IB_SIZE
#define regSDMA0_RLC6_IB_SIZE_BASE_IDX
#define regSDMA0_RLC6_SKIP_CNTL
#define regSDMA0_RLC6_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC6_CONTEXT_STATUS
#define regSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC6_DOORBELL
#define regSDMA0_RLC6_DOORBELL_BASE_IDX
#define regSDMA0_RLC6_STATUS
#define regSDMA0_RLC6_STATUS_BASE_IDX
#define regSDMA0_RLC6_DOORBELL_LOG
#define regSDMA0_RLC6_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC6_WATERMARK
#define regSDMA0_RLC6_WATERMARK_BASE_IDX
#define regSDMA0_RLC6_DOORBELL_OFFSET
#define regSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC6_CSA_ADDR_LO
#define regSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC6_CSA_ADDR_HI
#define regSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC6_IB_SUB_REMAIN
#define regSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC6_PREEMPT
#define regSDMA0_RLC6_PREEMPT_BASE_IDX
#define regSDMA0_RLC6_DUMMY_REG
#define regSDMA0_RLC6_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC6_RB_AQL_CNTL
#define regSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC6_MINOR_PTR_UPDATE
#define regSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA0
#define regSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA1
#define regSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA2
#define regSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA3
#define regSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA4
#define regSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA5
#define regSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA6
#define regSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA7
#define regSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA8
#define regSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA9
#define regSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_DATA10
#define regSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC6_MIDCMD_CNTL
#define regSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX
#define regSDMA0_RLC7_RB_CNTL
#define regSDMA0_RLC7_RB_CNTL_BASE_IDX
#define regSDMA0_RLC7_RB_BASE
#define regSDMA0_RLC7_RB_BASE_BASE_IDX
#define regSDMA0_RLC7_RB_BASE_HI
#define regSDMA0_RLC7_RB_BASE_HI_BASE_IDX
#define regSDMA0_RLC7_RB_RPTR
#define regSDMA0_RLC7_RB_RPTR_BASE_IDX
#define regSDMA0_RLC7_RB_RPTR_HI
#define regSDMA0_RLC7_RB_RPTR_HI_BASE_IDX
#define regSDMA0_RLC7_RB_WPTR
#define regSDMA0_RLC7_RB_WPTR_BASE_IDX
#define regSDMA0_RLC7_RB_WPTR_HI
#define regSDMA0_RLC7_RB_WPTR_HI_BASE_IDX
#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL
#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA0_RLC7_RB_RPTR_ADDR_HI
#define regSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA0_RLC7_RB_RPTR_ADDR_LO
#define regSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA0_RLC7_IB_CNTL
#define regSDMA0_RLC7_IB_CNTL_BASE_IDX
#define regSDMA0_RLC7_IB_RPTR
#define regSDMA0_RLC7_IB_RPTR_BASE_IDX
#define regSDMA0_RLC7_IB_OFFSET
#define regSDMA0_RLC7_IB_OFFSET_BASE_IDX
#define regSDMA0_RLC7_IB_BASE_LO
#define regSDMA0_RLC7_IB_BASE_LO_BASE_IDX
#define regSDMA0_RLC7_IB_BASE_HI
#define regSDMA0_RLC7_IB_BASE_HI_BASE_IDX
#define regSDMA0_RLC7_IB_SIZE
#define regSDMA0_RLC7_IB_SIZE_BASE_IDX
#define regSDMA0_RLC7_SKIP_CNTL
#define regSDMA0_RLC7_SKIP_CNTL_BASE_IDX
#define regSDMA0_RLC7_CONTEXT_STATUS
#define regSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX
#define regSDMA0_RLC7_DOORBELL
#define regSDMA0_RLC7_DOORBELL_BASE_IDX
#define regSDMA0_RLC7_STATUS
#define regSDMA0_RLC7_STATUS_BASE_IDX
#define regSDMA0_RLC7_DOORBELL_LOG
#define regSDMA0_RLC7_DOORBELL_LOG_BASE_IDX
#define regSDMA0_RLC7_WATERMARK
#define regSDMA0_RLC7_WATERMARK_BASE_IDX
#define regSDMA0_RLC7_DOORBELL_OFFSET
#define regSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX
#define regSDMA0_RLC7_CSA_ADDR_LO
#define regSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX
#define regSDMA0_RLC7_CSA_ADDR_HI
#define regSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX
#define regSDMA0_RLC7_IB_SUB_REMAIN
#define regSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX
#define regSDMA0_RLC7_PREEMPT
#define regSDMA0_RLC7_PREEMPT_BASE_IDX
#define regSDMA0_RLC7_DUMMY_REG
#define regSDMA0_RLC7_DUMMY_REG_BASE_IDX
#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA0_RLC7_RB_AQL_CNTL
#define regSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX
#define regSDMA0_RLC7_MINOR_PTR_UPDATE
#define regSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA0
#define regSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA1
#define regSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA2
#define regSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA3
#define regSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA4
#define regSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA5
#define regSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA6
#define regSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA7
#define regSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA8
#define regSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA9
#define regSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_DATA10
#define regSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX
#define regSDMA0_RLC7_MIDCMD_CNTL
#define regSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX


// addressBlock: sdma0_sdma1dec
// base address: 0x6180
#define regSDMA1_UCODE_ADDR
#define regSDMA1_UCODE_ADDR_BASE_IDX
#define regSDMA1_UCODE_DATA
#define regSDMA1_UCODE_DATA_BASE_IDX
#define regSDMA1_VF_ENABLE
#define regSDMA1_VF_ENABLE_BASE_IDX
#define regSDMA1_CONTEXT_GROUP_BOUNDARY
#define regSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define regSDMA1_POWER_CNTL
#define regSDMA1_POWER_CNTL_BASE_IDX
#define regSDMA1_CLK_CTRL
#define regSDMA1_CLK_CTRL_BASE_IDX
#define regSDMA1_CNTL
#define regSDMA1_CNTL_BASE_IDX
#define regSDMA1_CHICKEN_BITS
#define regSDMA1_CHICKEN_BITS_BASE_IDX
#define regSDMA1_GB_ADDR_CONFIG
#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX
#define regSDMA1_GB_ADDR_CONFIG_READ
#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX
#define regSDMA1_RB_RPTR_FETCH_HI
#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX
#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL
#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define regSDMA1_RB_RPTR_FETCH
#define regSDMA1_RB_RPTR_FETCH_BASE_IDX
#define regSDMA1_IB_OFFSET_FETCH
#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX
#define regSDMA1_PROGRAM
#define regSDMA1_PROGRAM_BASE_IDX
#define regSDMA1_STATUS_REG
#define regSDMA1_STATUS_REG_BASE_IDX
#define regSDMA1_STATUS1_REG
#define regSDMA1_STATUS1_REG_BASE_IDX
#define regSDMA1_RD_BURST_CNTL
#define regSDMA1_RD_BURST_CNTL_BASE_IDX
#define regSDMA1_HBM_PAGE_CONFIG
#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX
#define regSDMA1_UCODE_CHECKSUM
#define regSDMA1_UCODE_CHECKSUM_BASE_IDX
#define regSDMA1_F32_CNTL
#define regSDMA1_F32_CNTL_BASE_IDX
#define regSDMA1_FREEZE
#define regSDMA1_FREEZE_BASE_IDX
#define regSDMA1_PHASE0_QUANTUM
#define regSDMA1_PHASE0_QUANTUM_BASE_IDX
#define regSDMA1_PHASE1_QUANTUM
#define regSDMA1_PHASE1_QUANTUM_BASE_IDX
#define regCC_SDMA1_EDC_CONFIG
#define regCC_SDMA1_EDC_CONFIG_BASE_IDX
#define regSDMA1_BA_THRESHOLD
#define regSDMA1_BA_THRESHOLD_BASE_IDX
#define regSDMA1_ID
#define regSDMA1_ID_BASE_IDX
#define regSDMA1_VERSION
#define regSDMA1_VERSION_BASE_IDX
#define regSDMA1_EDC_COUNTER
#define regSDMA1_EDC_COUNTER_BASE_IDX
#define regSDMA1_EDC_COUNTER2
#define regSDMA1_EDC_COUNTER2_BASE_IDX
#define regSDMA1_STATUS2_REG
#define regSDMA1_STATUS2_REG_BASE_IDX
#define regSDMA1_ATOMIC_CNTL
#define regSDMA1_ATOMIC_CNTL_BASE_IDX
#define regSDMA1_ATOMIC_PREOP_LO
#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX
#define regSDMA1_ATOMIC_PREOP_HI
#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX
#define regSDMA1_UTCL1_CNTL
#define regSDMA1_UTCL1_CNTL_BASE_IDX
#define regSDMA1_UTCL1_WATERMK
#define regSDMA1_UTCL1_WATERMK_BASE_IDX
#define regSDMA1_UTCL1_RD_STATUS
#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX
#define regSDMA1_UTCL1_WR_STATUS
#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX
#define regSDMA1_UTCL1_INV0
#define regSDMA1_UTCL1_INV0_BASE_IDX
#define regSDMA1_UTCL1_INV1
#define regSDMA1_UTCL1_INV1_BASE_IDX
#define regSDMA1_UTCL1_INV2
#define regSDMA1_UTCL1_INV2_BASE_IDX
#define regSDMA1_UTCL1_RD_XNACK0
#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX
#define regSDMA1_UTCL1_RD_XNACK1
#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX
#define regSDMA1_UTCL1_WR_XNACK0
#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX
#define regSDMA1_UTCL1_WR_XNACK1
#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX
#define regSDMA1_UTCL1_TIMEOUT
#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX
#define regSDMA1_UTCL1_PAGE
#define regSDMA1_UTCL1_PAGE_BASE_IDX
#define regSDMA1_POWER_CNTL_IDLE
#define regSDMA1_POWER_CNTL_IDLE_BASE_IDX
#define regSDMA1_RELAX_ORDERING_LUT
#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX
#define regSDMA1_CHICKEN_BITS_2
#define regSDMA1_CHICKEN_BITS_2_BASE_IDX
#define regSDMA1_STATUS3_REG
#define regSDMA1_STATUS3_REG_BASE_IDX
#define regSDMA1_PHYSICAL_ADDR_LO
#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX
#define regSDMA1_PHYSICAL_ADDR_HI
#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX
#define regSDMA1_PHASE2_QUANTUM
#define regSDMA1_PHASE2_QUANTUM_BASE_IDX
#define regSDMA1_ERROR_LOG
#define regSDMA1_ERROR_LOG_BASE_IDX
#define regSDMA1_PUB_DUMMY_REG0
#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX
#define regSDMA1_PUB_DUMMY_REG1
#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX
#define regSDMA1_PUB_DUMMY_REG2
#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX
#define regSDMA1_PUB_DUMMY_REG3
#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX
#define regSDMA1_F32_COUNTER
#define regSDMA1_F32_COUNTER_BASE_IDX
#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG
#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX
#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG
#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX
#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX
#define regSDMA1_PERFCNT_MISC_CNTL
#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX
#define regSDMA1_PERFCNT_PERFCOUNTER_LO
#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX
#define regSDMA1_PERFCNT_PERFCOUNTER_HI
#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX
#define regSDMA1_CRD_CNTL
#define regSDMA1_CRD_CNTL_BASE_IDX
#define regSDMA1_ULV_CNTL
#define regSDMA1_ULV_CNTL_BASE_IDX
#define regSDMA1_EA_DBIT_ADDR_DATA
#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX
#define regSDMA1_EA_DBIT_ADDR_INDEX
#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX
#define regSDMA1_STATUS4_REG
#define regSDMA1_STATUS4_REG_BASE_IDX
#define regSDMA1_SCRATCH_RAM_DATA
#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX
#define regSDMA1_SCRATCH_RAM_ADDR
#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX
#define regSDMA1_CE_CTRL
#define regSDMA1_CE_CTRL_BASE_IDX
#define regSDMA1_RAS_STATUS
#define regSDMA1_RAS_STATUS_BASE_IDX
#define regSDMA1_CLK_STATUS
#define regSDMA1_CLK_STATUS_BASE_IDX
#define regSDMA1_GFX_RB_CNTL
#define regSDMA1_GFX_RB_CNTL_BASE_IDX
#define regSDMA1_GFX_RB_BASE
#define regSDMA1_GFX_RB_BASE_BASE_IDX
#define regSDMA1_GFX_RB_BASE_HI
#define regSDMA1_GFX_RB_BASE_HI_BASE_IDX
#define regSDMA1_GFX_RB_RPTR
#define regSDMA1_GFX_RB_RPTR_BASE_IDX
#define regSDMA1_GFX_RB_RPTR_HI
#define regSDMA1_GFX_RB_RPTR_HI_BASE_IDX
#define regSDMA1_GFX_RB_WPTR
#define regSDMA1_GFX_RB_WPTR_BASE_IDX
#define regSDMA1_GFX_RB_WPTR_HI
#define regSDMA1_GFX_RB_WPTR_HI_BASE_IDX
#define regSDMA1_GFX_RB_WPTR_POLL_CNTL
#define regSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_GFX_RB_RPTR_ADDR_HI
#define regSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_GFX_RB_RPTR_ADDR_LO
#define regSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_GFX_IB_CNTL
#define regSDMA1_GFX_IB_CNTL_BASE_IDX
#define regSDMA1_GFX_IB_RPTR
#define regSDMA1_GFX_IB_RPTR_BASE_IDX
#define regSDMA1_GFX_IB_OFFSET
#define regSDMA1_GFX_IB_OFFSET_BASE_IDX
#define regSDMA1_GFX_IB_BASE_LO
#define regSDMA1_GFX_IB_BASE_LO_BASE_IDX
#define regSDMA1_GFX_IB_BASE_HI
#define regSDMA1_GFX_IB_BASE_HI_BASE_IDX
#define regSDMA1_GFX_IB_SIZE
#define regSDMA1_GFX_IB_SIZE_BASE_IDX
#define regSDMA1_GFX_SKIP_CNTL
#define regSDMA1_GFX_SKIP_CNTL_BASE_IDX
#define regSDMA1_GFX_CONTEXT_STATUS
#define regSDMA1_GFX_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_GFX_DOORBELL
#define regSDMA1_GFX_DOORBELL_BASE_IDX
#define regSDMA1_GFX_CONTEXT_CNTL
#define regSDMA1_GFX_CONTEXT_CNTL_BASE_IDX
#define regSDMA1_GFX_STATUS
#define regSDMA1_GFX_STATUS_BASE_IDX
#define regSDMA1_GFX_DOORBELL_LOG
#define regSDMA1_GFX_DOORBELL_LOG_BASE_IDX
#define regSDMA1_GFX_WATERMARK
#define regSDMA1_GFX_WATERMARK_BASE_IDX
#define regSDMA1_GFX_DOORBELL_OFFSET
#define regSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_GFX_CSA_ADDR_LO
#define regSDMA1_GFX_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_GFX_CSA_ADDR_HI
#define regSDMA1_GFX_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_GFX_IB_SUB_REMAIN
#define regSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_GFX_PREEMPT
#define regSDMA1_GFX_PREEMPT_BASE_IDX
#define regSDMA1_GFX_DUMMY_REG
#define regSDMA1_GFX_DUMMY_REG_BASE_IDX
#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_GFX_RB_AQL_CNTL
#define regSDMA1_GFX_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_GFX_MINOR_PTR_UPDATE
#define regSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA0
#define regSDMA1_GFX_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA1
#define regSDMA1_GFX_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA2
#define regSDMA1_GFX_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA3
#define regSDMA1_GFX_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA4
#define regSDMA1_GFX_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA5
#define regSDMA1_GFX_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA6
#define regSDMA1_GFX_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA7
#define regSDMA1_GFX_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA8
#define regSDMA1_GFX_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA9
#define regSDMA1_GFX_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_GFX_MIDCMD_DATA10
#define regSDMA1_GFX_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_GFX_MIDCMD_CNTL
#define regSDMA1_GFX_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_PAGE_RB_CNTL
#define regSDMA1_PAGE_RB_CNTL_BASE_IDX
#define regSDMA1_PAGE_RB_BASE
#define regSDMA1_PAGE_RB_BASE_BASE_IDX
#define regSDMA1_PAGE_RB_BASE_HI
#define regSDMA1_PAGE_RB_BASE_HI_BASE_IDX
#define regSDMA1_PAGE_RB_RPTR
#define regSDMA1_PAGE_RB_RPTR_BASE_IDX
#define regSDMA1_PAGE_RB_RPTR_HI
#define regSDMA1_PAGE_RB_RPTR_HI_BASE_IDX
#define regSDMA1_PAGE_RB_WPTR
#define regSDMA1_PAGE_RB_WPTR_BASE_IDX
#define regSDMA1_PAGE_RB_WPTR_HI
#define regSDMA1_PAGE_RB_WPTR_HI_BASE_IDX
#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL
#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_PAGE_RB_RPTR_ADDR_HI
#define regSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_PAGE_RB_RPTR_ADDR_LO
#define regSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_PAGE_IB_CNTL
#define regSDMA1_PAGE_IB_CNTL_BASE_IDX
#define regSDMA1_PAGE_IB_RPTR
#define regSDMA1_PAGE_IB_RPTR_BASE_IDX
#define regSDMA1_PAGE_IB_OFFSET
#define regSDMA1_PAGE_IB_OFFSET_BASE_IDX
#define regSDMA1_PAGE_IB_BASE_LO
#define regSDMA1_PAGE_IB_BASE_LO_BASE_IDX
#define regSDMA1_PAGE_IB_BASE_HI
#define regSDMA1_PAGE_IB_BASE_HI_BASE_IDX
#define regSDMA1_PAGE_IB_SIZE
#define regSDMA1_PAGE_IB_SIZE_BASE_IDX
#define regSDMA1_PAGE_SKIP_CNTL
#define regSDMA1_PAGE_SKIP_CNTL_BASE_IDX
#define regSDMA1_PAGE_CONTEXT_STATUS
#define regSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_PAGE_DOORBELL
#define regSDMA1_PAGE_DOORBELL_BASE_IDX
#define regSDMA1_PAGE_STATUS
#define regSDMA1_PAGE_STATUS_BASE_IDX
#define regSDMA1_PAGE_DOORBELL_LOG
#define regSDMA1_PAGE_DOORBELL_LOG_BASE_IDX
#define regSDMA1_PAGE_WATERMARK
#define regSDMA1_PAGE_WATERMARK_BASE_IDX
#define regSDMA1_PAGE_DOORBELL_OFFSET
#define regSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_PAGE_CSA_ADDR_LO
#define regSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_PAGE_CSA_ADDR_HI
#define regSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_PAGE_IB_SUB_REMAIN
#define regSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_PAGE_PREEMPT
#define regSDMA1_PAGE_PREEMPT_BASE_IDX
#define regSDMA1_PAGE_DUMMY_REG
#define regSDMA1_PAGE_DUMMY_REG_BASE_IDX
#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_PAGE_RB_AQL_CNTL
#define regSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_PAGE_MINOR_PTR_UPDATE
#define regSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA0
#define regSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA1
#define regSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA2
#define regSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA3
#define regSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA4
#define regSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA5
#define regSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA6
#define regSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA7
#define regSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA8
#define regSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA9
#define regSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_DATA10
#define regSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_PAGE_MIDCMD_CNTL
#define regSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC0_RB_CNTL
#define regSDMA1_RLC0_RB_CNTL_BASE_IDX
#define regSDMA1_RLC0_RB_BASE
#define regSDMA1_RLC0_RB_BASE_BASE_IDX
#define regSDMA1_RLC0_RB_BASE_HI
#define regSDMA1_RLC0_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC0_RB_RPTR
#define regSDMA1_RLC0_RB_RPTR_BASE_IDX
#define regSDMA1_RLC0_RB_RPTR_HI
#define regSDMA1_RLC0_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC0_RB_WPTR
#define regSDMA1_RLC0_RB_WPTR_BASE_IDX
#define regSDMA1_RLC0_RB_WPTR_HI
#define regSDMA1_RLC0_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC0_RB_RPTR_ADDR_HI
#define regSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC0_RB_RPTR_ADDR_LO
#define regSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC0_IB_CNTL
#define regSDMA1_RLC0_IB_CNTL_BASE_IDX
#define regSDMA1_RLC0_IB_RPTR
#define regSDMA1_RLC0_IB_RPTR_BASE_IDX
#define regSDMA1_RLC0_IB_OFFSET
#define regSDMA1_RLC0_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC0_IB_BASE_LO
#define regSDMA1_RLC0_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC0_IB_BASE_HI
#define regSDMA1_RLC0_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC0_IB_SIZE
#define regSDMA1_RLC0_IB_SIZE_BASE_IDX
#define regSDMA1_RLC0_SKIP_CNTL
#define regSDMA1_RLC0_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC0_CONTEXT_STATUS
#define regSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC0_DOORBELL
#define regSDMA1_RLC0_DOORBELL_BASE_IDX
#define regSDMA1_RLC0_STATUS
#define regSDMA1_RLC0_STATUS_BASE_IDX
#define regSDMA1_RLC0_DOORBELL_LOG
#define regSDMA1_RLC0_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC0_WATERMARK
#define regSDMA1_RLC0_WATERMARK_BASE_IDX
#define regSDMA1_RLC0_DOORBELL_OFFSET
#define regSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC0_CSA_ADDR_LO
#define regSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC0_CSA_ADDR_HI
#define regSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC0_IB_SUB_REMAIN
#define regSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC0_PREEMPT
#define regSDMA1_RLC0_PREEMPT_BASE_IDX
#define regSDMA1_RLC0_DUMMY_REG
#define regSDMA1_RLC0_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC0_RB_AQL_CNTL
#define regSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC0_MINOR_PTR_UPDATE
#define regSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA0
#define regSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA1
#define regSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA2
#define regSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA3
#define regSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA4
#define regSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA5
#define regSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA6
#define regSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA7
#define regSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA8
#define regSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA9
#define regSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_DATA10
#define regSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC0_MIDCMD_CNTL
#define regSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC1_RB_CNTL
#define regSDMA1_RLC1_RB_CNTL_BASE_IDX
#define regSDMA1_RLC1_RB_BASE
#define regSDMA1_RLC1_RB_BASE_BASE_IDX
#define regSDMA1_RLC1_RB_BASE_HI
#define regSDMA1_RLC1_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC1_RB_RPTR
#define regSDMA1_RLC1_RB_RPTR_BASE_IDX
#define regSDMA1_RLC1_RB_RPTR_HI
#define regSDMA1_RLC1_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC1_RB_WPTR
#define regSDMA1_RLC1_RB_WPTR_BASE_IDX
#define regSDMA1_RLC1_RB_WPTR_HI
#define regSDMA1_RLC1_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC1_RB_RPTR_ADDR_HI
#define regSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC1_RB_RPTR_ADDR_LO
#define regSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC1_IB_CNTL
#define regSDMA1_RLC1_IB_CNTL_BASE_IDX
#define regSDMA1_RLC1_IB_RPTR
#define regSDMA1_RLC1_IB_RPTR_BASE_IDX
#define regSDMA1_RLC1_IB_OFFSET
#define regSDMA1_RLC1_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC1_IB_BASE_LO
#define regSDMA1_RLC1_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC1_IB_BASE_HI
#define regSDMA1_RLC1_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC1_IB_SIZE
#define regSDMA1_RLC1_IB_SIZE_BASE_IDX
#define regSDMA1_RLC1_SKIP_CNTL
#define regSDMA1_RLC1_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC1_CONTEXT_STATUS
#define regSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC1_DOORBELL
#define regSDMA1_RLC1_DOORBELL_BASE_IDX
#define regSDMA1_RLC1_STATUS
#define regSDMA1_RLC1_STATUS_BASE_IDX
#define regSDMA1_RLC1_DOORBELL_LOG
#define regSDMA1_RLC1_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC1_WATERMARK
#define regSDMA1_RLC1_WATERMARK_BASE_IDX
#define regSDMA1_RLC1_DOORBELL_OFFSET
#define regSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC1_CSA_ADDR_LO
#define regSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC1_CSA_ADDR_HI
#define regSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC1_IB_SUB_REMAIN
#define regSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC1_PREEMPT
#define regSDMA1_RLC1_PREEMPT_BASE_IDX
#define regSDMA1_RLC1_DUMMY_REG
#define regSDMA1_RLC1_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC1_RB_AQL_CNTL
#define regSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC1_MINOR_PTR_UPDATE
#define regSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA0
#define regSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA1
#define regSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA2
#define regSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA3
#define regSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA4
#define regSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA5
#define regSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA6
#define regSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA7
#define regSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA8
#define regSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA9
#define regSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_DATA10
#define regSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC1_MIDCMD_CNTL
#define regSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC2_RB_CNTL
#define regSDMA1_RLC2_RB_CNTL_BASE_IDX
#define regSDMA1_RLC2_RB_BASE
#define regSDMA1_RLC2_RB_BASE_BASE_IDX
#define regSDMA1_RLC2_RB_BASE_HI
#define regSDMA1_RLC2_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC2_RB_RPTR
#define regSDMA1_RLC2_RB_RPTR_BASE_IDX
#define regSDMA1_RLC2_RB_RPTR_HI
#define regSDMA1_RLC2_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC2_RB_WPTR
#define regSDMA1_RLC2_RB_WPTR_BASE_IDX
#define regSDMA1_RLC2_RB_WPTR_HI
#define regSDMA1_RLC2_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC2_RB_RPTR_ADDR_HI
#define regSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC2_RB_RPTR_ADDR_LO
#define regSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC2_IB_CNTL
#define regSDMA1_RLC2_IB_CNTL_BASE_IDX
#define regSDMA1_RLC2_IB_RPTR
#define regSDMA1_RLC2_IB_RPTR_BASE_IDX
#define regSDMA1_RLC2_IB_OFFSET
#define regSDMA1_RLC2_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC2_IB_BASE_LO
#define regSDMA1_RLC2_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC2_IB_BASE_HI
#define regSDMA1_RLC2_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC2_IB_SIZE
#define regSDMA1_RLC2_IB_SIZE_BASE_IDX
#define regSDMA1_RLC2_SKIP_CNTL
#define regSDMA1_RLC2_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC2_CONTEXT_STATUS
#define regSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC2_DOORBELL
#define regSDMA1_RLC2_DOORBELL_BASE_IDX
#define regSDMA1_RLC2_STATUS
#define regSDMA1_RLC2_STATUS_BASE_IDX
#define regSDMA1_RLC2_DOORBELL_LOG
#define regSDMA1_RLC2_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC2_WATERMARK
#define regSDMA1_RLC2_WATERMARK_BASE_IDX
#define regSDMA1_RLC2_DOORBELL_OFFSET
#define regSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC2_CSA_ADDR_LO
#define regSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC2_CSA_ADDR_HI
#define regSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC2_IB_SUB_REMAIN
#define regSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC2_PREEMPT
#define regSDMA1_RLC2_PREEMPT_BASE_IDX
#define regSDMA1_RLC2_DUMMY_REG
#define regSDMA1_RLC2_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC2_RB_AQL_CNTL
#define regSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC2_MINOR_PTR_UPDATE
#define regSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA0
#define regSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA1
#define regSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA2
#define regSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA3
#define regSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA4
#define regSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA5
#define regSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA6
#define regSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA7
#define regSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA8
#define regSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA9
#define regSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_DATA10
#define regSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC2_MIDCMD_CNTL
#define regSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC3_RB_CNTL
#define regSDMA1_RLC3_RB_CNTL_BASE_IDX
#define regSDMA1_RLC3_RB_BASE
#define regSDMA1_RLC3_RB_BASE_BASE_IDX
#define regSDMA1_RLC3_RB_BASE_HI
#define regSDMA1_RLC3_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC3_RB_RPTR
#define regSDMA1_RLC3_RB_RPTR_BASE_IDX
#define regSDMA1_RLC3_RB_RPTR_HI
#define regSDMA1_RLC3_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC3_RB_WPTR
#define regSDMA1_RLC3_RB_WPTR_BASE_IDX
#define regSDMA1_RLC3_RB_WPTR_HI
#define regSDMA1_RLC3_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC3_RB_RPTR_ADDR_HI
#define regSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC3_RB_RPTR_ADDR_LO
#define regSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC3_IB_CNTL
#define regSDMA1_RLC3_IB_CNTL_BASE_IDX
#define regSDMA1_RLC3_IB_RPTR
#define regSDMA1_RLC3_IB_RPTR_BASE_IDX
#define regSDMA1_RLC3_IB_OFFSET
#define regSDMA1_RLC3_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC3_IB_BASE_LO
#define regSDMA1_RLC3_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC3_IB_BASE_HI
#define regSDMA1_RLC3_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC3_IB_SIZE
#define regSDMA1_RLC3_IB_SIZE_BASE_IDX
#define regSDMA1_RLC3_SKIP_CNTL
#define regSDMA1_RLC3_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC3_CONTEXT_STATUS
#define regSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC3_DOORBELL
#define regSDMA1_RLC3_DOORBELL_BASE_IDX
#define regSDMA1_RLC3_STATUS
#define regSDMA1_RLC3_STATUS_BASE_IDX
#define regSDMA1_RLC3_DOORBELL_LOG
#define regSDMA1_RLC3_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC3_WATERMARK
#define regSDMA1_RLC3_WATERMARK_BASE_IDX
#define regSDMA1_RLC3_DOORBELL_OFFSET
#define regSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC3_CSA_ADDR_LO
#define regSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC3_CSA_ADDR_HI
#define regSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC3_IB_SUB_REMAIN
#define regSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC3_PREEMPT
#define regSDMA1_RLC3_PREEMPT_BASE_IDX
#define regSDMA1_RLC3_DUMMY_REG
#define regSDMA1_RLC3_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC3_RB_AQL_CNTL
#define regSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC3_MINOR_PTR_UPDATE
#define regSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA0
#define regSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA1
#define regSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA2
#define regSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA3
#define regSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA4
#define regSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA5
#define regSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA6
#define regSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA7
#define regSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA8
#define regSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA9
#define regSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_DATA10
#define regSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC3_MIDCMD_CNTL
#define regSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC4_RB_CNTL
#define regSDMA1_RLC4_RB_CNTL_BASE_IDX
#define regSDMA1_RLC4_RB_BASE
#define regSDMA1_RLC4_RB_BASE_BASE_IDX
#define regSDMA1_RLC4_RB_BASE_HI
#define regSDMA1_RLC4_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC4_RB_RPTR
#define regSDMA1_RLC4_RB_RPTR_BASE_IDX
#define regSDMA1_RLC4_RB_RPTR_HI
#define regSDMA1_RLC4_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC4_RB_WPTR
#define regSDMA1_RLC4_RB_WPTR_BASE_IDX
#define regSDMA1_RLC4_RB_WPTR_HI
#define regSDMA1_RLC4_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC4_RB_RPTR_ADDR_HI
#define regSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC4_RB_RPTR_ADDR_LO
#define regSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC4_IB_CNTL
#define regSDMA1_RLC4_IB_CNTL_BASE_IDX
#define regSDMA1_RLC4_IB_RPTR
#define regSDMA1_RLC4_IB_RPTR_BASE_IDX
#define regSDMA1_RLC4_IB_OFFSET
#define regSDMA1_RLC4_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC4_IB_BASE_LO
#define regSDMA1_RLC4_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC4_IB_BASE_HI
#define regSDMA1_RLC4_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC4_IB_SIZE
#define regSDMA1_RLC4_IB_SIZE_BASE_IDX
#define regSDMA1_RLC4_SKIP_CNTL
#define regSDMA1_RLC4_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC4_CONTEXT_STATUS
#define regSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC4_DOORBELL
#define regSDMA1_RLC4_DOORBELL_BASE_IDX
#define regSDMA1_RLC4_STATUS
#define regSDMA1_RLC4_STATUS_BASE_IDX
#define regSDMA1_RLC4_DOORBELL_LOG
#define regSDMA1_RLC4_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC4_WATERMARK
#define regSDMA1_RLC4_WATERMARK_BASE_IDX
#define regSDMA1_RLC4_DOORBELL_OFFSET
#define regSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC4_CSA_ADDR_LO
#define regSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC4_CSA_ADDR_HI
#define regSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC4_IB_SUB_REMAIN
#define regSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC4_PREEMPT
#define regSDMA1_RLC4_PREEMPT_BASE_IDX
#define regSDMA1_RLC4_DUMMY_REG
#define regSDMA1_RLC4_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC4_RB_AQL_CNTL
#define regSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC4_MINOR_PTR_UPDATE
#define regSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA0
#define regSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA1
#define regSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA2
#define regSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA3
#define regSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA4
#define regSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA5
#define regSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA6
#define regSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA7
#define regSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA8
#define regSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA9
#define regSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_DATA10
#define regSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC4_MIDCMD_CNTL
#define regSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC5_RB_CNTL
#define regSDMA1_RLC5_RB_CNTL_BASE_IDX
#define regSDMA1_RLC5_RB_BASE
#define regSDMA1_RLC5_RB_BASE_BASE_IDX
#define regSDMA1_RLC5_RB_BASE_HI
#define regSDMA1_RLC5_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC5_RB_RPTR
#define regSDMA1_RLC5_RB_RPTR_BASE_IDX
#define regSDMA1_RLC5_RB_RPTR_HI
#define regSDMA1_RLC5_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC5_RB_WPTR
#define regSDMA1_RLC5_RB_WPTR_BASE_IDX
#define regSDMA1_RLC5_RB_WPTR_HI
#define regSDMA1_RLC5_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC5_RB_RPTR_ADDR_HI
#define regSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC5_RB_RPTR_ADDR_LO
#define regSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC5_IB_CNTL
#define regSDMA1_RLC5_IB_CNTL_BASE_IDX
#define regSDMA1_RLC5_IB_RPTR
#define regSDMA1_RLC5_IB_RPTR_BASE_IDX
#define regSDMA1_RLC5_IB_OFFSET
#define regSDMA1_RLC5_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC5_IB_BASE_LO
#define regSDMA1_RLC5_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC5_IB_BASE_HI
#define regSDMA1_RLC5_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC5_IB_SIZE
#define regSDMA1_RLC5_IB_SIZE_BASE_IDX
#define regSDMA1_RLC5_SKIP_CNTL
#define regSDMA1_RLC5_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC5_CONTEXT_STATUS
#define regSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC5_DOORBELL
#define regSDMA1_RLC5_DOORBELL_BASE_IDX
#define regSDMA1_RLC5_STATUS
#define regSDMA1_RLC5_STATUS_BASE_IDX
#define regSDMA1_RLC5_DOORBELL_LOG
#define regSDMA1_RLC5_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC5_WATERMARK
#define regSDMA1_RLC5_WATERMARK_BASE_IDX
#define regSDMA1_RLC5_DOORBELL_OFFSET
#define regSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC5_CSA_ADDR_LO
#define regSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC5_CSA_ADDR_HI
#define regSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC5_IB_SUB_REMAIN
#define regSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC5_PREEMPT
#define regSDMA1_RLC5_PREEMPT_BASE_IDX
#define regSDMA1_RLC5_DUMMY_REG
#define regSDMA1_RLC5_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC5_RB_AQL_CNTL
#define regSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC5_MINOR_PTR_UPDATE
#define regSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA0
#define regSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA1
#define regSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA2
#define regSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA3
#define regSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA4
#define regSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA5
#define regSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA6
#define regSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA7
#define regSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA8
#define regSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA9
#define regSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_DATA10
#define regSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC5_MIDCMD_CNTL
#define regSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC6_RB_CNTL
#define regSDMA1_RLC6_RB_CNTL_BASE_IDX
#define regSDMA1_RLC6_RB_BASE
#define regSDMA1_RLC6_RB_BASE_BASE_IDX
#define regSDMA1_RLC6_RB_BASE_HI
#define regSDMA1_RLC6_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC6_RB_RPTR
#define regSDMA1_RLC6_RB_RPTR_BASE_IDX
#define regSDMA1_RLC6_RB_RPTR_HI
#define regSDMA1_RLC6_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC6_RB_WPTR
#define regSDMA1_RLC6_RB_WPTR_BASE_IDX
#define regSDMA1_RLC6_RB_WPTR_HI
#define regSDMA1_RLC6_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC6_RB_RPTR_ADDR_HI
#define regSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC6_RB_RPTR_ADDR_LO
#define regSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC6_IB_CNTL
#define regSDMA1_RLC6_IB_CNTL_BASE_IDX
#define regSDMA1_RLC6_IB_RPTR
#define regSDMA1_RLC6_IB_RPTR_BASE_IDX
#define regSDMA1_RLC6_IB_OFFSET
#define regSDMA1_RLC6_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC6_IB_BASE_LO
#define regSDMA1_RLC6_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC6_IB_BASE_HI
#define regSDMA1_RLC6_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC6_IB_SIZE
#define regSDMA1_RLC6_IB_SIZE_BASE_IDX
#define regSDMA1_RLC6_SKIP_CNTL
#define regSDMA1_RLC6_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC6_CONTEXT_STATUS
#define regSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC6_DOORBELL
#define regSDMA1_RLC6_DOORBELL_BASE_IDX
#define regSDMA1_RLC6_STATUS
#define regSDMA1_RLC6_STATUS_BASE_IDX
#define regSDMA1_RLC6_DOORBELL_LOG
#define regSDMA1_RLC6_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC6_WATERMARK
#define regSDMA1_RLC6_WATERMARK_BASE_IDX
#define regSDMA1_RLC6_DOORBELL_OFFSET
#define regSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC6_CSA_ADDR_LO
#define regSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC6_CSA_ADDR_HI
#define regSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC6_IB_SUB_REMAIN
#define regSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC6_PREEMPT
#define regSDMA1_RLC6_PREEMPT_BASE_IDX
#define regSDMA1_RLC6_DUMMY_REG
#define regSDMA1_RLC6_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC6_RB_AQL_CNTL
#define regSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC6_MINOR_PTR_UPDATE
#define regSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA0
#define regSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA1
#define regSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA2
#define regSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA3
#define regSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA4
#define regSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA5
#define regSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA6
#define regSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA7
#define regSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA8
#define regSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA9
#define regSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_DATA10
#define regSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC6_MIDCMD_CNTL
#define regSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX
#define regSDMA1_RLC7_RB_CNTL
#define regSDMA1_RLC7_RB_CNTL_BASE_IDX
#define regSDMA1_RLC7_RB_BASE
#define regSDMA1_RLC7_RB_BASE_BASE_IDX
#define regSDMA1_RLC7_RB_BASE_HI
#define regSDMA1_RLC7_RB_BASE_HI_BASE_IDX
#define regSDMA1_RLC7_RB_RPTR
#define regSDMA1_RLC7_RB_RPTR_BASE_IDX
#define regSDMA1_RLC7_RB_RPTR_HI
#define regSDMA1_RLC7_RB_RPTR_HI_BASE_IDX
#define regSDMA1_RLC7_RB_WPTR
#define regSDMA1_RLC7_RB_WPTR_BASE_IDX
#define regSDMA1_RLC7_RB_WPTR_HI
#define regSDMA1_RLC7_RB_WPTR_HI_BASE_IDX
#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL
#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA1_RLC7_RB_RPTR_ADDR_HI
#define regSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA1_RLC7_RB_RPTR_ADDR_LO
#define regSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA1_RLC7_IB_CNTL
#define regSDMA1_RLC7_IB_CNTL_BASE_IDX
#define regSDMA1_RLC7_IB_RPTR
#define regSDMA1_RLC7_IB_RPTR_BASE_IDX
#define regSDMA1_RLC7_IB_OFFSET
#define regSDMA1_RLC7_IB_OFFSET_BASE_IDX
#define regSDMA1_RLC7_IB_BASE_LO
#define regSDMA1_RLC7_IB_BASE_LO_BASE_IDX
#define regSDMA1_RLC7_IB_BASE_HI
#define regSDMA1_RLC7_IB_BASE_HI_BASE_IDX
#define regSDMA1_RLC7_IB_SIZE
#define regSDMA1_RLC7_IB_SIZE_BASE_IDX
#define regSDMA1_RLC7_SKIP_CNTL
#define regSDMA1_RLC7_SKIP_CNTL_BASE_IDX
#define regSDMA1_RLC7_CONTEXT_STATUS
#define regSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX
#define regSDMA1_RLC7_DOORBELL
#define regSDMA1_RLC7_DOORBELL_BASE_IDX
#define regSDMA1_RLC7_STATUS
#define regSDMA1_RLC7_STATUS_BASE_IDX
#define regSDMA1_RLC7_DOORBELL_LOG
#define regSDMA1_RLC7_DOORBELL_LOG_BASE_IDX
#define regSDMA1_RLC7_WATERMARK
#define regSDMA1_RLC7_WATERMARK_BASE_IDX
#define regSDMA1_RLC7_DOORBELL_OFFSET
#define regSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX
#define regSDMA1_RLC7_CSA_ADDR_LO
#define regSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX
#define regSDMA1_RLC7_CSA_ADDR_HI
#define regSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX
#define regSDMA1_RLC7_IB_SUB_REMAIN
#define regSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX
#define regSDMA1_RLC7_PREEMPT
#define regSDMA1_RLC7_PREEMPT_BASE_IDX
#define regSDMA1_RLC7_DUMMY_REG
#define regSDMA1_RLC7_DUMMY_REG_BASE_IDX
#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA1_RLC7_RB_AQL_CNTL
#define regSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX
#define regSDMA1_RLC7_MINOR_PTR_UPDATE
#define regSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA0
#define regSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA1
#define regSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA2
#define regSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA3
#define regSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA4
#define regSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA5
#define regSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA6
#define regSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA7
#define regSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA8
#define regSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA9
#define regSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_DATA10
#define regSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX
#define regSDMA1_RLC7_MIDCMD_CNTL
#define regSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX


// addressBlock: sdma0_sdma2dec
// base address: 0x78000
#define regSDMA2_UCODE_ADDR
#define regSDMA2_UCODE_ADDR_BASE_IDX
#define regSDMA2_UCODE_DATA
#define regSDMA2_UCODE_DATA_BASE_IDX
#define regSDMA2_VF_ENABLE
#define regSDMA2_VF_ENABLE_BASE_IDX
#define regSDMA2_CONTEXT_GROUP_BOUNDARY
#define regSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define regSDMA2_POWER_CNTL
#define regSDMA2_POWER_CNTL_BASE_IDX
#define regSDMA2_CLK_CTRL
#define regSDMA2_CLK_CTRL_BASE_IDX
#define regSDMA2_CNTL
#define regSDMA2_CNTL_BASE_IDX
#define regSDMA2_CHICKEN_BITS
#define regSDMA2_CHICKEN_BITS_BASE_IDX
#define regSDMA2_GB_ADDR_CONFIG
#define regSDMA2_GB_ADDR_CONFIG_BASE_IDX
#define regSDMA2_GB_ADDR_CONFIG_READ
#define regSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX
#define regSDMA2_RB_RPTR_FETCH_HI
#define regSDMA2_RB_RPTR_FETCH_HI_BASE_IDX
#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL
#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define regSDMA2_RB_RPTR_FETCH
#define regSDMA2_RB_RPTR_FETCH_BASE_IDX
#define regSDMA2_IB_OFFSET_FETCH
#define regSDMA2_IB_OFFSET_FETCH_BASE_IDX
#define regSDMA2_PROGRAM
#define regSDMA2_PROGRAM_BASE_IDX
#define regSDMA2_STATUS_REG
#define regSDMA2_STATUS_REG_BASE_IDX
#define regSDMA2_STATUS1_REG
#define regSDMA2_STATUS1_REG_BASE_IDX
#define regSDMA2_RD_BURST_CNTL
#define regSDMA2_RD_BURST_CNTL_BASE_IDX
#define regSDMA2_HBM_PAGE_CONFIG
#define regSDMA2_HBM_PAGE_CONFIG_BASE_IDX
#define regSDMA2_UCODE_CHECKSUM
#define regSDMA2_UCODE_CHECKSUM_BASE_IDX
#define regSDMA2_F32_CNTL
#define regSDMA2_F32_CNTL_BASE_IDX
#define regSDMA2_FREEZE
#define regSDMA2_FREEZE_BASE_IDX
#define regSDMA2_PHASE0_QUANTUM
#define regSDMA2_PHASE0_QUANTUM_BASE_IDX
#define regSDMA2_PHASE1_QUANTUM
#define regSDMA2_PHASE1_QUANTUM_BASE_IDX
#define regCC_SDMA2_EDC_CONFIG
#define regCC_SDMA2_EDC_CONFIG_BASE_IDX
#define regSDMA2_BA_THRESHOLD
#define regSDMA2_BA_THRESHOLD_BASE_IDX
#define regSDMA2_ID
#define regSDMA2_ID_BASE_IDX
#define regSDMA2_VERSION
#define regSDMA2_VERSION_BASE_IDX
#define regSDMA2_EDC_COUNTER
#define regSDMA2_EDC_COUNTER_BASE_IDX
#define regSDMA2_EDC_COUNTER2
#define regSDMA2_EDC_COUNTER2_BASE_IDX
#define regSDMA2_STATUS2_REG
#define regSDMA2_STATUS2_REG_BASE_IDX
#define regSDMA2_ATOMIC_CNTL
#define regSDMA2_ATOMIC_CNTL_BASE_IDX
#define regSDMA2_ATOMIC_PREOP_LO
#define regSDMA2_ATOMIC_PREOP_LO_BASE_IDX
#define regSDMA2_ATOMIC_PREOP_HI
#define regSDMA2_ATOMIC_PREOP_HI_BASE_IDX
#define regSDMA2_UTCL1_CNTL
#define regSDMA2_UTCL1_CNTL_BASE_IDX
#define regSDMA2_UTCL1_WATERMK
#define regSDMA2_UTCL1_WATERMK_BASE_IDX
#define regSDMA2_UTCL1_RD_STATUS
#define regSDMA2_UTCL1_RD_STATUS_BASE_IDX
#define regSDMA2_UTCL1_WR_STATUS
#define regSDMA2_UTCL1_WR_STATUS_BASE_IDX
#define regSDMA2_UTCL1_INV0
#define regSDMA2_UTCL1_INV0_BASE_IDX
#define regSDMA2_UTCL1_INV1
#define regSDMA2_UTCL1_INV1_BASE_IDX
#define regSDMA2_UTCL1_INV2
#define regSDMA2_UTCL1_INV2_BASE_IDX
#define regSDMA2_UTCL1_RD_XNACK0
#define regSDMA2_UTCL1_RD_XNACK0_BASE_IDX
#define regSDMA2_UTCL1_RD_XNACK1
#define regSDMA2_UTCL1_RD_XNACK1_BASE_IDX
#define regSDMA2_UTCL1_WR_XNACK0
#define regSDMA2_UTCL1_WR_XNACK0_BASE_IDX
#define regSDMA2_UTCL1_WR_XNACK1
#define regSDMA2_UTCL1_WR_XNACK1_BASE_IDX
#define regSDMA2_UTCL1_TIMEOUT
#define regSDMA2_UTCL1_TIMEOUT_BASE_IDX
#define regSDMA2_UTCL1_PAGE
#define regSDMA2_UTCL1_PAGE_BASE_IDX
#define regSDMA2_POWER_CNTL_IDLE
#define regSDMA2_POWER_CNTL_IDLE_BASE_IDX
#define regSDMA2_RELAX_ORDERING_LUT
#define regSDMA2_RELAX_ORDERING_LUT_BASE_IDX
#define regSDMA2_CHICKEN_BITS_2
#define regSDMA2_CHICKEN_BITS_2_BASE_IDX
#define regSDMA2_STATUS3_REG
#define regSDMA2_STATUS3_REG_BASE_IDX
#define regSDMA2_PHYSICAL_ADDR_LO
#define regSDMA2_PHYSICAL_ADDR_LO_BASE_IDX
#define regSDMA2_PHYSICAL_ADDR_HI
#define regSDMA2_PHYSICAL_ADDR_HI_BASE_IDX
#define regSDMA2_PHASE2_QUANTUM
#define regSDMA2_PHASE2_QUANTUM_BASE_IDX
#define regSDMA2_ERROR_LOG
#define regSDMA2_ERROR_LOG_BASE_IDX
#define regSDMA2_PUB_DUMMY_REG0
#define regSDMA2_PUB_DUMMY_REG0_BASE_IDX
#define regSDMA2_PUB_DUMMY_REG1
#define regSDMA2_PUB_DUMMY_REG1_BASE_IDX
#define regSDMA2_PUB_DUMMY_REG2
#define regSDMA2_PUB_DUMMY_REG2_BASE_IDX
#define regSDMA2_PUB_DUMMY_REG3
#define regSDMA2_PUB_DUMMY_REG3_BASE_IDX
#define regSDMA2_F32_COUNTER
#define regSDMA2_F32_COUNTER_BASE_IDX
#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG
#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX
#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG
#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX
#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX
#define regSDMA2_PERFCNT_MISC_CNTL
#define regSDMA2_PERFCNT_MISC_CNTL_BASE_IDX
#define regSDMA2_PERFCNT_PERFCOUNTER_LO
#define regSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX
#define regSDMA2_PERFCNT_PERFCOUNTER_HI
#define regSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX
#define regSDMA2_CRD_CNTL
#define regSDMA2_CRD_CNTL_BASE_IDX
#define regSDMA2_ULV_CNTL
#define regSDMA2_ULV_CNTL_BASE_IDX
#define regSDMA2_EA_DBIT_ADDR_DATA
#define regSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX
#define regSDMA2_EA_DBIT_ADDR_INDEX
#define regSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX
#define regSDMA2_STATUS4_REG
#define regSDMA2_STATUS4_REG_BASE_IDX
#define regSDMA2_SCRATCH_RAM_DATA
#define regSDMA2_SCRATCH_RAM_DATA_BASE_IDX
#define regSDMA2_SCRATCH_RAM_ADDR
#define regSDMA2_SCRATCH_RAM_ADDR_BASE_IDX
#define regSDMA2_CE_CTRL
#define regSDMA2_CE_CTRL_BASE_IDX
#define regSDMA2_RAS_STATUS
#define regSDMA2_RAS_STATUS_BASE_IDX
#define regSDMA2_CLK_STATUS
#define regSDMA2_CLK_STATUS_BASE_IDX
#define regSDMA2_GFX_RB_CNTL
#define regSDMA2_GFX_RB_CNTL_BASE_IDX
#define regSDMA2_GFX_RB_BASE
#define regSDMA2_GFX_RB_BASE_BASE_IDX
#define regSDMA2_GFX_RB_BASE_HI
#define regSDMA2_GFX_RB_BASE_HI_BASE_IDX
#define regSDMA2_GFX_RB_RPTR
#define regSDMA2_GFX_RB_RPTR_BASE_IDX
#define regSDMA2_GFX_RB_RPTR_HI
#define regSDMA2_GFX_RB_RPTR_HI_BASE_IDX
#define regSDMA2_GFX_RB_WPTR
#define regSDMA2_GFX_RB_WPTR_BASE_IDX
#define regSDMA2_GFX_RB_WPTR_HI
#define regSDMA2_GFX_RB_WPTR_HI_BASE_IDX
#define regSDMA2_GFX_RB_WPTR_POLL_CNTL
#define regSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_GFX_RB_RPTR_ADDR_HI
#define regSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_GFX_RB_RPTR_ADDR_LO
#define regSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_GFX_IB_CNTL
#define regSDMA2_GFX_IB_CNTL_BASE_IDX
#define regSDMA2_GFX_IB_RPTR
#define regSDMA2_GFX_IB_RPTR_BASE_IDX
#define regSDMA2_GFX_IB_OFFSET
#define regSDMA2_GFX_IB_OFFSET_BASE_IDX
#define regSDMA2_GFX_IB_BASE_LO
#define regSDMA2_GFX_IB_BASE_LO_BASE_IDX
#define regSDMA2_GFX_IB_BASE_HI
#define regSDMA2_GFX_IB_BASE_HI_BASE_IDX
#define regSDMA2_GFX_IB_SIZE
#define regSDMA2_GFX_IB_SIZE_BASE_IDX
#define regSDMA2_GFX_SKIP_CNTL
#define regSDMA2_GFX_SKIP_CNTL_BASE_IDX
#define regSDMA2_GFX_CONTEXT_STATUS
#define regSDMA2_GFX_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_GFX_DOORBELL
#define regSDMA2_GFX_DOORBELL_BASE_IDX
#define regSDMA2_GFX_CONTEXT_CNTL
#define regSDMA2_GFX_CONTEXT_CNTL_BASE_IDX
#define regSDMA2_GFX_STATUS
#define regSDMA2_GFX_STATUS_BASE_IDX
#define regSDMA2_GFX_DOORBELL_LOG
#define regSDMA2_GFX_DOORBELL_LOG_BASE_IDX
#define regSDMA2_GFX_WATERMARK
#define regSDMA2_GFX_WATERMARK_BASE_IDX
#define regSDMA2_GFX_DOORBELL_OFFSET
#define regSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_GFX_CSA_ADDR_LO
#define regSDMA2_GFX_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_GFX_CSA_ADDR_HI
#define regSDMA2_GFX_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_GFX_IB_SUB_REMAIN
#define regSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_GFX_PREEMPT
#define regSDMA2_GFX_PREEMPT_BASE_IDX
#define regSDMA2_GFX_DUMMY_REG
#define regSDMA2_GFX_DUMMY_REG_BASE_IDX
#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_GFX_RB_AQL_CNTL
#define regSDMA2_GFX_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_GFX_MINOR_PTR_UPDATE
#define regSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA0
#define regSDMA2_GFX_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA1
#define regSDMA2_GFX_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA2
#define regSDMA2_GFX_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA3
#define regSDMA2_GFX_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA4
#define regSDMA2_GFX_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA5
#define regSDMA2_GFX_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA6
#define regSDMA2_GFX_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA7
#define regSDMA2_GFX_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA8
#define regSDMA2_GFX_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA9
#define regSDMA2_GFX_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_GFX_MIDCMD_DATA10
#define regSDMA2_GFX_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_GFX_MIDCMD_CNTL
#define regSDMA2_GFX_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_PAGE_RB_CNTL
#define regSDMA2_PAGE_RB_CNTL_BASE_IDX
#define regSDMA2_PAGE_RB_BASE
#define regSDMA2_PAGE_RB_BASE_BASE_IDX
#define regSDMA2_PAGE_RB_BASE_HI
#define regSDMA2_PAGE_RB_BASE_HI_BASE_IDX
#define regSDMA2_PAGE_RB_RPTR
#define regSDMA2_PAGE_RB_RPTR_BASE_IDX
#define regSDMA2_PAGE_RB_RPTR_HI
#define regSDMA2_PAGE_RB_RPTR_HI_BASE_IDX
#define regSDMA2_PAGE_RB_WPTR
#define regSDMA2_PAGE_RB_WPTR_BASE_IDX
#define regSDMA2_PAGE_RB_WPTR_HI
#define regSDMA2_PAGE_RB_WPTR_HI_BASE_IDX
#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL
#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_PAGE_RB_RPTR_ADDR_HI
#define regSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_PAGE_RB_RPTR_ADDR_LO
#define regSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_PAGE_IB_CNTL
#define regSDMA2_PAGE_IB_CNTL_BASE_IDX
#define regSDMA2_PAGE_IB_RPTR
#define regSDMA2_PAGE_IB_RPTR_BASE_IDX
#define regSDMA2_PAGE_IB_OFFSET
#define regSDMA2_PAGE_IB_OFFSET_BASE_IDX
#define regSDMA2_PAGE_IB_BASE_LO
#define regSDMA2_PAGE_IB_BASE_LO_BASE_IDX
#define regSDMA2_PAGE_IB_BASE_HI
#define regSDMA2_PAGE_IB_BASE_HI_BASE_IDX
#define regSDMA2_PAGE_IB_SIZE
#define regSDMA2_PAGE_IB_SIZE_BASE_IDX
#define regSDMA2_PAGE_SKIP_CNTL
#define regSDMA2_PAGE_SKIP_CNTL_BASE_IDX
#define regSDMA2_PAGE_CONTEXT_STATUS
#define regSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_PAGE_DOORBELL
#define regSDMA2_PAGE_DOORBELL_BASE_IDX
#define regSDMA2_PAGE_STATUS
#define regSDMA2_PAGE_STATUS_BASE_IDX
#define regSDMA2_PAGE_DOORBELL_LOG
#define regSDMA2_PAGE_DOORBELL_LOG_BASE_IDX
#define regSDMA2_PAGE_WATERMARK
#define regSDMA2_PAGE_WATERMARK_BASE_IDX
#define regSDMA2_PAGE_DOORBELL_OFFSET
#define regSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_PAGE_CSA_ADDR_LO
#define regSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_PAGE_CSA_ADDR_HI
#define regSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_PAGE_IB_SUB_REMAIN
#define regSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_PAGE_PREEMPT
#define regSDMA2_PAGE_PREEMPT_BASE_IDX
#define regSDMA2_PAGE_DUMMY_REG
#define regSDMA2_PAGE_DUMMY_REG_BASE_IDX
#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_PAGE_RB_AQL_CNTL
#define regSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_PAGE_MINOR_PTR_UPDATE
#define regSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA0
#define regSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA1
#define regSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA2
#define regSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA3
#define regSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA4
#define regSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA5
#define regSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA6
#define regSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA7
#define regSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA8
#define regSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA9
#define regSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_DATA10
#define regSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_PAGE_MIDCMD_CNTL
#define regSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC0_RB_CNTL
#define regSDMA2_RLC0_RB_CNTL_BASE_IDX
#define regSDMA2_RLC0_RB_BASE
#define regSDMA2_RLC0_RB_BASE_BASE_IDX
#define regSDMA2_RLC0_RB_BASE_HI
#define regSDMA2_RLC0_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC0_RB_RPTR
#define regSDMA2_RLC0_RB_RPTR_BASE_IDX
#define regSDMA2_RLC0_RB_RPTR_HI
#define regSDMA2_RLC0_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC0_RB_WPTR
#define regSDMA2_RLC0_RB_WPTR_BASE_IDX
#define regSDMA2_RLC0_RB_WPTR_HI
#define regSDMA2_RLC0_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC0_RB_RPTR_ADDR_HI
#define regSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC0_RB_RPTR_ADDR_LO
#define regSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC0_IB_CNTL
#define regSDMA2_RLC0_IB_CNTL_BASE_IDX
#define regSDMA2_RLC0_IB_RPTR
#define regSDMA2_RLC0_IB_RPTR_BASE_IDX
#define regSDMA2_RLC0_IB_OFFSET
#define regSDMA2_RLC0_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC0_IB_BASE_LO
#define regSDMA2_RLC0_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC0_IB_BASE_HI
#define regSDMA2_RLC0_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC0_IB_SIZE
#define regSDMA2_RLC0_IB_SIZE_BASE_IDX
#define regSDMA2_RLC0_SKIP_CNTL
#define regSDMA2_RLC0_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC0_CONTEXT_STATUS
#define regSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC0_DOORBELL
#define regSDMA2_RLC0_DOORBELL_BASE_IDX
#define regSDMA2_RLC0_STATUS
#define regSDMA2_RLC0_STATUS_BASE_IDX
#define regSDMA2_RLC0_DOORBELL_LOG
#define regSDMA2_RLC0_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC0_WATERMARK
#define regSDMA2_RLC0_WATERMARK_BASE_IDX
#define regSDMA2_RLC0_DOORBELL_OFFSET
#define regSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC0_CSA_ADDR_LO
#define regSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC0_CSA_ADDR_HI
#define regSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC0_IB_SUB_REMAIN
#define regSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC0_PREEMPT
#define regSDMA2_RLC0_PREEMPT_BASE_IDX
#define regSDMA2_RLC0_DUMMY_REG
#define regSDMA2_RLC0_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC0_RB_AQL_CNTL
#define regSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC0_MINOR_PTR_UPDATE
#define regSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA0
#define regSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA1
#define regSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA2
#define regSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA3
#define regSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA4
#define regSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA5
#define regSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA6
#define regSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA7
#define regSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA8
#define regSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA9
#define regSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_DATA10
#define regSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC0_MIDCMD_CNTL
#define regSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC1_RB_CNTL
#define regSDMA2_RLC1_RB_CNTL_BASE_IDX
#define regSDMA2_RLC1_RB_BASE
#define regSDMA2_RLC1_RB_BASE_BASE_IDX
#define regSDMA2_RLC1_RB_BASE_HI
#define regSDMA2_RLC1_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC1_RB_RPTR
#define regSDMA2_RLC1_RB_RPTR_BASE_IDX
#define regSDMA2_RLC1_RB_RPTR_HI
#define regSDMA2_RLC1_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC1_RB_WPTR
#define regSDMA2_RLC1_RB_WPTR_BASE_IDX
#define regSDMA2_RLC1_RB_WPTR_HI
#define regSDMA2_RLC1_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC1_RB_RPTR_ADDR_HI
#define regSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC1_RB_RPTR_ADDR_LO
#define regSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC1_IB_CNTL
#define regSDMA2_RLC1_IB_CNTL_BASE_IDX
#define regSDMA2_RLC1_IB_RPTR
#define regSDMA2_RLC1_IB_RPTR_BASE_IDX
#define regSDMA2_RLC1_IB_OFFSET
#define regSDMA2_RLC1_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC1_IB_BASE_LO
#define regSDMA2_RLC1_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC1_IB_BASE_HI
#define regSDMA2_RLC1_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC1_IB_SIZE
#define regSDMA2_RLC1_IB_SIZE_BASE_IDX
#define regSDMA2_RLC1_SKIP_CNTL
#define regSDMA2_RLC1_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC1_CONTEXT_STATUS
#define regSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC1_DOORBELL
#define regSDMA2_RLC1_DOORBELL_BASE_IDX
#define regSDMA2_RLC1_STATUS
#define regSDMA2_RLC1_STATUS_BASE_IDX
#define regSDMA2_RLC1_DOORBELL_LOG
#define regSDMA2_RLC1_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC1_WATERMARK
#define regSDMA2_RLC1_WATERMARK_BASE_IDX
#define regSDMA2_RLC1_DOORBELL_OFFSET
#define regSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC1_CSA_ADDR_LO
#define regSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC1_CSA_ADDR_HI
#define regSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC1_IB_SUB_REMAIN
#define regSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC1_PREEMPT
#define regSDMA2_RLC1_PREEMPT_BASE_IDX
#define regSDMA2_RLC1_DUMMY_REG
#define regSDMA2_RLC1_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC1_RB_AQL_CNTL
#define regSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC1_MINOR_PTR_UPDATE
#define regSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA0
#define regSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA1
#define regSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA2
#define regSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA3
#define regSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA4
#define regSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA5
#define regSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA6
#define regSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA7
#define regSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA8
#define regSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA9
#define regSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_DATA10
#define regSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC1_MIDCMD_CNTL
#define regSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC2_RB_CNTL
#define regSDMA2_RLC2_RB_CNTL_BASE_IDX
#define regSDMA2_RLC2_RB_BASE
#define regSDMA2_RLC2_RB_BASE_BASE_IDX
#define regSDMA2_RLC2_RB_BASE_HI
#define regSDMA2_RLC2_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC2_RB_RPTR
#define regSDMA2_RLC2_RB_RPTR_BASE_IDX
#define regSDMA2_RLC2_RB_RPTR_HI
#define regSDMA2_RLC2_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC2_RB_WPTR
#define regSDMA2_RLC2_RB_WPTR_BASE_IDX
#define regSDMA2_RLC2_RB_WPTR_HI
#define regSDMA2_RLC2_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC2_RB_RPTR_ADDR_HI
#define regSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC2_RB_RPTR_ADDR_LO
#define regSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC2_IB_CNTL
#define regSDMA2_RLC2_IB_CNTL_BASE_IDX
#define regSDMA2_RLC2_IB_RPTR
#define regSDMA2_RLC2_IB_RPTR_BASE_IDX
#define regSDMA2_RLC2_IB_OFFSET
#define regSDMA2_RLC2_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC2_IB_BASE_LO
#define regSDMA2_RLC2_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC2_IB_BASE_HI
#define regSDMA2_RLC2_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC2_IB_SIZE
#define regSDMA2_RLC2_IB_SIZE_BASE_IDX
#define regSDMA2_RLC2_SKIP_CNTL
#define regSDMA2_RLC2_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC2_CONTEXT_STATUS
#define regSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC2_DOORBELL
#define regSDMA2_RLC2_DOORBELL_BASE_IDX
#define regSDMA2_RLC2_STATUS
#define regSDMA2_RLC2_STATUS_BASE_IDX
#define regSDMA2_RLC2_DOORBELL_LOG
#define regSDMA2_RLC2_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC2_WATERMARK
#define regSDMA2_RLC2_WATERMARK_BASE_IDX
#define regSDMA2_RLC2_DOORBELL_OFFSET
#define regSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC2_CSA_ADDR_LO
#define regSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC2_CSA_ADDR_HI
#define regSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC2_IB_SUB_REMAIN
#define regSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC2_PREEMPT
#define regSDMA2_RLC2_PREEMPT_BASE_IDX
#define regSDMA2_RLC2_DUMMY_REG
#define regSDMA2_RLC2_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC2_RB_AQL_CNTL
#define regSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC2_MINOR_PTR_UPDATE
#define regSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA0
#define regSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA1
#define regSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA2
#define regSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA3
#define regSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA4
#define regSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA5
#define regSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA6
#define regSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA7
#define regSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA8
#define regSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA9
#define regSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_DATA10
#define regSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC2_MIDCMD_CNTL
#define regSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC3_RB_CNTL
#define regSDMA2_RLC3_RB_CNTL_BASE_IDX
#define regSDMA2_RLC3_RB_BASE
#define regSDMA2_RLC3_RB_BASE_BASE_IDX
#define regSDMA2_RLC3_RB_BASE_HI
#define regSDMA2_RLC3_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC3_RB_RPTR
#define regSDMA2_RLC3_RB_RPTR_BASE_IDX
#define regSDMA2_RLC3_RB_RPTR_HI
#define regSDMA2_RLC3_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC3_RB_WPTR
#define regSDMA2_RLC3_RB_WPTR_BASE_IDX
#define regSDMA2_RLC3_RB_WPTR_HI
#define regSDMA2_RLC3_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC3_RB_RPTR_ADDR_HI
#define regSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC3_RB_RPTR_ADDR_LO
#define regSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC3_IB_CNTL
#define regSDMA2_RLC3_IB_CNTL_BASE_IDX
#define regSDMA2_RLC3_IB_RPTR
#define regSDMA2_RLC3_IB_RPTR_BASE_IDX
#define regSDMA2_RLC3_IB_OFFSET
#define regSDMA2_RLC3_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC3_IB_BASE_LO
#define regSDMA2_RLC3_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC3_IB_BASE_HI
#define regSDMA2_RLC3_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC3_IB_SIZE
#define regSDMA2_RLC3_IB_SIZE_BASE_IDX
#define regSDMA2_RLC3_SKIP_CNTL
#define regSDMA2_RLC3_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC3_CONTEXT_STATUS
#define regSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC3_DOORBELL
#define regSDMA2_RLC3_DOORBELL_BASE_IDX
#define regSDMA2_RLC3_STATUS
#define regSDMA2_RLC3_STATUS_BASE_IDX
#define regSDMA2_RLC3_DOORBELL_LOG
#define regSDMA2_RLC3_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC3_WATERMARK
#define regSDMA2_RLC3_WATERMARK_BASE_IDX
#define regSDMA2_RLC3_DOORBELL_OFFSET
#define regSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC3_CSA_ADDR_LO
#define regSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC3_CSA_ADDR_HI
#define regSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC3_IB_SUB_REMAIN
#define regSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC3_PREEMPT
#define regSDMA2_RLC3_PREEMPT_BASE_IDX
#define regSDMA2_RLC3_DUMMY_REG
#define regSDMA2_RLC3_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC3_RB_AQL_CNTL
#define regSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC3_MINOR_PTR_UPDATE
#define regSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA0
#define regSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA1
#define regSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA2
#define regSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA3
#define regSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA4
#define regSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA5
#define regSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA6
#define regSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA7
#define regSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA8
#define regSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA9
#define regSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_DATA10
#define regSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC3_MIDCMD_CNTL
#define regSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC4_RB_CNTL
#define regSDMA2_RLC4_RB_CNTL_BASE_IDX
#define regSDMA2_RLC4_RB_BASE
#define regSDMA2_RLC4_RB_BASE_BASE_IDX
#define regSDMA2_RLC4_RB_BASE_HI
#define regSDMA2_RLC4_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC4_RB_RPTR
#define regSDMA2_RLC4_RB_RPTR_BASE_IDX
#define regSDMA2_RLC4_RB_RPTR_HI
#define regSDMA2_RLC4_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC4_RB_WPTR
#define regSDMA2_RLC4_RB_WPTR_BASE_IDX
#define regSDMA2_RLC4_RB_WPTR_HI
#define regSDMA2_RLC4_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC4_RB_RPTR_ADDR_HI
#define regSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC4_RB_RPTR_ADDR_LO
#define regSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC4_IB_CNTL
#define regSDMA2_RLC4_IB_CNTL_BASE_IDX
#define regSDMA2_RLC4_IB_RPTR
#define regSDMA2_RLC4_IB_RPTR_BASE_IDX
#define regSDMA2_RLC4_IB_OFFSET
#define regSDMA2_RLC4_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC4_IB_BASE_LO
#define regSDMA2_RLC4_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC4_IB_BASE_HI
#define regSDMA2_RLC4_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC4_IB_SIZE
#define regSDMA2_RLC4_IB_SIZE_BASE_IDX
#define regSDMA2_RLC4_SKIP_CNTL
#define regSDMA2_RLC4_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC4_CONTEXT_STATUS
#define regSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC4_DOORBELL
#define regSDMA2_RLC4_DOORBELL_BASE_IDX
#define regSDMA2_RLC4_STATUS
#define regSDMA2_RLC4_STATUS_BASE_IDX
#define regSDMA2_RLC4_DOORBELL_LOG
#define regSDMA2_RLC4_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC4_WATERMARK
#define regSDMA2_RLC4_WATERMARK_BASE_IDX
#define regSDMA2_RLC4_DOORBELL_OFFSET
#define regSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC4_CSA_ADDR_LO
#define regSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC4_CSA_ADDR_HI
#define regSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC4_IB_SUB_REMAIN
#define regSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC4_PREEMPT
#define regSDMA2_RLC4_PREEMPT_BASE_IDX
#define regSDMA2_RLC4_DUMMY_REG
#define regSDMA2_RLC4_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC4_RB_AQL_CNTL
#define regSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC4_MINOR_PTR_UPDATE
#define regSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA0
#define regSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA1
#define regSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA2
#define regSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA3
#define regSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA4
#define regSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA5
#define regSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA6
#define regSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA7
#define regSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA8
#define regSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA9
#define regSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_DATA10
#define regSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC4_MIDCMD_CNTL
#define regSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC5_RB_CNTL
#define regSDMA2_RLC5_RB_CNTL_BASE_IDX
#define regSDMA2_RLC5_RB_BASE
#define regSDMA2_RLC5_RB_BASE_BASE_IDX
#define regSDMA2_RLC5_RB_BASE_HI
#define regSDMA2_RLC5_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC5_RB_RPTR
#define regSDMA2_RLC5_RB_RPTR_BASE_IDX
#define regSDMA2_RLC5_RB_RPTR_HI
#define regSDMA2_RLC5_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC5_RB_WPTR
#define regSDMA2_RLC5_RB_WPTR_BASE_IDX
#define regSDMA2_RLC5_RB_WPTR_HI
#define regSDMA2_RLC5_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC5_RB_RPTR_ADDR_HI
#define regSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC5_RB_RPTR_ADDR_LO
#define regSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC5_IB_CNTL
#define regSDMA2_RLC5_IB_CNTL_BASE_IDX
#define regSDMA2_RLC5_IB_RPTR
#define regSDMA2_RLC5_IB_RPTR_BASE_IDX
#define regSDMA2_RLC5_IB_OFFSET
#define regSDMA2_RLC5_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC5_IB_BASE_LO
#define regSDMA2_RLC5_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC5_IB_BASE_HI
#define regSDMA2_RLC5_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC5_IB_SIZE
#define regSDMA2_RLC5_IB_SIZE_BASE_IDX
#define regSDMA2_RLC5_SKIP_CNTL
#define regSDMA2_RLC5_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC5_CONTEXT_STATUS
#define regSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC5_DOORBELL
#define regSDMA2_RLC5_DOORBELL_BASE_IDX
#define regSDMA2_RLC5_STATUS
#define regSDMA2_RLC5_STATUS_BASE_IDX
#define regSDMA2_RLC5_DOORBELL_LOG
#define regSDMA2_RLC5_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC5_WATERMARK
#define regSDMA2_RLC5_WATERMARK_BASE_IDX
#define regSDMA2_RLC5_DOORBELL_OFFSET
#define regSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC5_CSA_ADDR_LO
#define regSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC5_CSA_ADDR_HI
#define regSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC5_IB_SUB_REMAIN
#define regSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC5_PREEMPT
#define regSDMA2_RLC5_PREEMPT_BASE_IDX
#define regSDMA2_RLC5_DUMMY_REG
#define regSDMA2_RLC5_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC5_RB_AQL_CNTL
#define regSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC5_MINOR_PTR_UPDATE
#define regSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA0
#define regSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA1
#define regSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA2
#define regSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA3
#define regSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA4
#define regSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA5
#define regSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA6
#define regSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA7
#define regSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA8
#define regSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA9
#define regSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_DATA10
#define regSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC5_MIDCMD_CNTL
#define regSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC6_RB_CNTL
#define regSDMA2_RLC6_RB_CNTL_BASE_IDX
#define regSDMA2_RLC6_RB_BASE
#define regSDMA2_RLC6_RB_BASE_BASE_IDX
#define regSDMA2_RLC6_RB_BASE_HI
#define regSDMA2_RLC6_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC6_RB_RPTR
#define regSDMA2_RLC6_RB_RPTR_BASE_IDX
#define regSDMA2_RLC6_RB_RPTR_HI
#define regSDMA2_RLC6_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC6_RB_WPTR
#define regSDMA2_RLC6_RB_WPTR_BASE_IDX
#define regSDMA2_RLC6_RB_WPTR_HI
#define regSDMA2_RLC6_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC6_RB_RPTR_ADDR_HI
#define regSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC6_RB_RPTR_ADDR_LO
#define regSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC6_IB_CNTL
#define regSDMA2_RLC6_IB_CNTL_BASE_IDX
#define regSDMA2_RLC6_IB_RPTR
#define regSDMA2_RLC6_IB_RPTR_BASE_IDX
#define regSDMA2_RLC6_IB_OFFSET
#define regSDMA2_RLC6_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC6_IB_BASE_LO
#define regSDMA2_RLC6_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC6_IB_BASE_HI
#define regSDMA2_RLC6_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC6_IB_SIZE
#define regSDMA2_RLC6_IB_SIZE_BASE_IDX
#define regSDMA2_RLC6_SKIP_CNTL
#define regSDMA2_RLC6_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC6_CONTEXT_STATUS
#define regSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC6_DOORBELL
#define regSDMA2_RLC6_DOORBELL_BASE_IDX
#define regSDMA2_RLC6_STATUS
#define regSDMA2_RLC6_STATUS_BASE_IDX
#define regSDMA2_RLC6_DOORBELL_LOG
#define regSDMA2_RLC6_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC6_WATERMARK
#define regSDMA2_RLC6_WATERMARK_BASE_IDX
#define regSDMA2_RLC6_DOORBELL_OFFSET
#define regSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC6_CSA_ADDR_LO
#define regSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC6_CSA_ADDR_HI
#define regSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC6_IB_SUB_REMAIN
#define regSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC6_PREEMPT
#define regSDMA2_RLC6_PREEMPT_BASE_IDX
#define regSDMA2_RLC6_DUMMY_REG
#define regSDMA2_RLC6_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC6_RB_AQL_CNTL
#define regSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC6_MINOR_PTR_UPDATE
#define regSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA0
#define regSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA1
#define regSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA2
#define regSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA3
#define regSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA4
#define regSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA5
#define regSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA6
#define regSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA7
#define regSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA8
#define regSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA9
#define regSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_DATA10
#define regSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC6_MIDCMD_CNTL
#define regSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX
#define regSDMA2_RLC7_RB_CNTL
#define regSDMA2_RLC7_RB_CNTL_BASE_IDX
#define regSDMA2_RLC7_RB_BASE
#define regSDMA2_RLC7_RB_BASE_BASE_IDX
#define regSDMA2_RLC7_RB_BASE_HI
#define regSDMA2_RLC7_RB_BASE_HI_BASE_IDX
#define regSDMA2_RLC7_RB_RPTR
#define regSDMA2_RLC7_RB_RPTR_BASE_IDX
#define regSDMA2_RLC7_RB_RPTR_HI
#define regSDMA2_RLC7_RB_RPTR_HI_BASE_IDX
#define regSDMA2_RLC7_RB_WPTR
#define regSDMA2_RLC7_RB_WPTR_BASE_IDX
#define regSDMA2_RLC7_RB_WPTR_HI
#define regSDMA2_RLC7_RB_WPTR_HI_BASE_IDX
#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL
#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA2_RLC7_RB_RPTR_ADDR_HI
#define regSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA2_RLC7_RB_RPTR_ADDR_LO
#define regSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA2_RLC7_IB_CNTL
#define regSDMA2_RLC7_IB_CNTL_BASE_IDX
#define regSDMA2_RLC7_IB_RPTR
#define regSDMA2_RLC7_IB_RPTR_BASE_IDX
#define regSDMA2_RLC7_IB_OFFSET
#define regSDMA2_RLC7_IB_OFFSET_BASE_IDX
#define regSDMA2_RLC7_IB_BASE_LO
#define regSDMA2_RLC7_IB_BASE_LO_BASE_IDX
#define regSDMA2_RLC7_IB_BASE_HI
#define regSDMA2_RLC7_IB_BASE_HI_BASE_IDX
#define regSDMA2_RLC7_IB_SIZE
#define regSDMA2_RLC7_IB_SIZE_BASE_IDX
#define regSDMA2_RLC7_SKIP_CNTL
#define regSDMA2_RLC7_SKIP_CNTL_BASE_IDX
#define regSDMA2_RLC7_CONTEXT_STATUS
#define regSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX
#define regSDMA2_RLC7_DOORBELL
#define regSDMA2_RLC7_DOORBELL_BASE_IDX
#define regSDMA2_RLC7_STATUS
#define regSDMA2_RLC7_STATUS_BASE_IDX
#define regSDMA2_RLC7_DOORBELL_LOG
#define regSDMA2_RLC7_DOORBELL_LOG_BASE_IDX
#define regSDMA2_RLC7_WATERMARK
#define regSDMA2_RLC7_WATERMARK_BASE_IDX
#define regSDMA2_RLC7_DOORBELL_OFFSET
#define regSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX
#define regSDMA2_RLC7_CSA_ADDR_LO
#define regSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX
#define regSDMA2_RLC7_CSA_ADDR_HI
#define regSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX
#define regSDMA2_RLC7_IB_SUB_REMAIN
#define regSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX
#define regSDMA2_RLC7_PREEMPT
#define regSDMA2_RLC7_PREEMPT_BASE_IDX
#define regSDMA2_RLC7_DUMMY_REG
#define regSDMA2_RLC7_DUMMY_REG_BASE_IDX
#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI
#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO
#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA2_RLC7_RB_AQL_CNTL
#define regSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX
#define regSDMA2_RLC7_MINOR_PTR_UPDATE
#define regSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA0
#define regSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA1
#define regSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA2
#define regSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA3
#define regSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA4
#define regSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA5
#define regSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA6
#define regSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA7
#define regSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA8
#define regSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA9
#define regSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_DATA10
#define regSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX
#define regSDMA2_RLC7_MIDCMD_CNTL
#define regSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX


// addressBlock: sdma0_sdma3dec
// base address: 0x79000
#define regSDMA3_UCODE_ADDR
#define regSDMA3_UCODE_ADDR_BASE_IDX
#define regSDMA3_UCODE_DATA
#define regSDMA3_UCODE_DATA_BASE_IDX
#define regSDMA3_VF_ENABLE
#define regSDMA3_VF_ENABLE_BASE_IDX
#define regSDMA3_CONTEXT_GROUP_BOUNDARY
#define regSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define regSDMA3_POWER_CNTL
#define regSDMA3_POWER_CNTL_BASE_IDX
#define regSDMA3_CLK_CTRL
#define regSDMA3_CLK_CTRL_BASE_IDX
#define regSDMA3_CNTL
#define regSDMA3_CNTL_BASE_IDX
#define regSDMA3_CHICKEN_BITS
#define regSDMA3_CHICKEN_BITS_BASE_IDX
#define regSDMA3_GB_ADDR_CONFIG
#define regSDMA3_GB_ADDR_CONFIG_BASE_IDX
#define regSDMA3_GB_ADDR_CONFIG_READ
#define regSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX
#define regSDMA3_RB_RPTR_FETCH_HI
#define regSDMA3_RB_RPTR_FETCH_HI_BASE_IDX
#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL
#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define regSDMA3_RB_RPTR_FETCH
#define regSDMA3_RB_RPTR_FETCH_BASE_IDX
#define regSDMA3_IB_OFFSET_FETCH
#define regSDMA3_IB_OFFSET_FETCH_BASE_IDX
#define regSDMA3_PROGRAM
#define regSDMA3_PROGRAM_BASE_IDX
#define regSDMA3_STATUS_REG
#define regSDMA3_STATUS_REG_BASE_IDX
#define regSDMA3_STATUS1_REG
#define regSDMA3_STATUS1_REG_BASE_IDX
#define regSDMA3_RD_BURST_CNTL
#define regSDMA3_RD_BURST_CNTL_BASE_IDX
#define regSDMA3_HBM_PAGE_CONFIG
#define regSDMA3_HBM_PAGE_CONFIG_BASE_IDX
#define regSDMA3_UCODE_CHECKSUM
#define regSDMA3_UCODE_CHECKSUM_BASE_IDX
#define regSDMA3_F32_CNTL
#define regSDMA3_F32_CNTL_BASE_IDX
#define regSDMA3_FREEZE
#define regSDMA3_FREEZE_BASE_IDX
#define regSDMA3_PHASE0_QUANTUM
#define regSDMA3_PHASE0_QUANTUM_BASE_IDX
#define regSDMA3_PHASE1_QUANTUM
#define regSDMA3_PHASE1_QUANTUM_BASE_IDX
#define regCC_SDMA3_EDC_CONFIG
#define regCC_SDMA3_EDC_CONFIG_BASE_IDX
#define regSDMA3_BA_THRESHOLD
#define regSDMA3_BA_THRESHOLD_BASE_IDX
#define regSDMA3_ID
#define regSDMA3_ID_BASE_IDX
#define regSDMA3_VERSION
#define regSDMA3_VERSION_BASE_IDX
#define regSDMA3_EDC_COUNTER
#define regSDMA3_EDC_COUNTER_BASE_IDX
#define regSDMA3_EDC_COUNTER2
#define regSDMA3_EDC_COUNTER2_BASE_IDX
#define regSDMA3_STATUS2_REG
#define regSDMA3_STATUS2_REG_BASE_IDX
#define regSDMA3_ATOMIC_CNTL
#define regSDMA3_ATOMIC_CNTL_BASE_IDX
#define regSDMA3_ATOMIC_PREOP_LO
#define regSDMA3_ATOMIC_PREOP_LO_BASE_IDX
#define regSDMA3_ATOMIC_PREOP_HI
#define regSDMA3_ATOMIC_PREOP_HI_BASE_IDX
#define regSDMA3_UTCL1_CNTL
#define regSDMA3_UTCL1_CNTL_BASE_IDX
#define regSDMA3_UTCL1_WATERMK
#define regSDMA3_UTCL1_WATERMK_BASE_IDX
#define regSDMA3_UTCL1_RD_STATUS
#define regSDMA3_UTCL1_RD_STATUS_BASE_IDX
#define regSDMA3_UTCL1_WR_STATUS
#define regSDMA3_UTCL1_WR_STATUS_BASE_IDX
#define regSDMA3_UTCL1_INV0
#define regSDMA3_UTCL1_INV0_BASE_IDX
#define regSDMA3_UTCL1_INV1
#define regSDMA3_UTCL1_INV1_BASE_IDX
#define regSDMA3_UTCL1_INV2
#define regSDMA3_UTCL1_INV2_BASE_IDX
#define regSDMA3_UTCL1_RD_XNACK0
#define regSDMA3_UTCL1_RD_XNACK0_BASE_IDX
#define regSDMA3_UTCL1_RD_XNACK1
#define regSDMA3_UTCL1_RD_XNACK1_BASE_IDX
#define regSDMA3_UTCL1_WR_XNACK0
#define regSDMA3_UTCL1_WR_XNACK0_BASE_IDX
#define regSDMA3_UTCL1_WR_XNACK1
#define regSDMA3_UTCL1_WR_XNACK1_BASE_IDX
#define regSDMA3_UTCL1_TIMEOUT
#define regSDMA3_UTCL1_TIMEOUT_BASE_IDX
#define regSDMA3_UTCL1_PAGE
#define regSDMA3_UTCL1_PAGE_BASE_IDX
#define regSDMA3_POWER_CNTL_IDLE
#define regSDMA3_POWER_CNTL_IDLE_BASE_IDX
#define regSDMA3_RELAX_ORDERING_LUT
#define regSDMA3_RELAX_ORDERING_LUT_BASE_IDX
#define regSDMA3_CHICKEN_BITS_2
#define regSDMA3_CHICKEN_BITS_2_BASE_IDX
#define regSDMA3_STATUS3_REG
#define regSDMA3_STATUS3_REG_BASE_IDX
#define regSDMA3_PHYSICAL_ADDR_LO
#define regSDMA3_PHYSICAL_ADDR_LO_BASE_IDX
#define regSDMA3_PHYSICAL_ADDR_HI
#define regSDMA3_PHYSICAL_ADDR_HI_BASE_IDX
#define regSDMA3_PHASE2_QUANTUM
#define regSDMA3_PHASE2_QUANTUM_BASE_IDX
#define regSDMA3_ERROR_LOG
#define regSDMA3_ERROR_LOG_BASE_IDX
#define regSDMA3_PUB_DUMMY_REG0
#define regSDMA3_PUB_DUMMY_REG0_BASE_IDX
#define regSDMA3_PUB_DUMMY_REG1
#define regSDMA3_PUB_DUMMY_REG1_BASE_IDX
#define regSDMA3_PUB_DUMMY_REG2
#define regSDMA3_PUB_DUMMY_REG2_BASE_IDX
#define regSDMA3_PUB_DUMMY_REG3
#define regSDMA3_PUB_DUMMY_REG3_BASE_IDX
#define regSDMA3_F32_COUNTER
#define regSDMA3_F32_COUNTER_BASE_IDX
#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG
#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX
#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG
#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX
#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX
#define regSDMA3_PERFCNT_MISC_CNTL
#define regSDMA3_PERFCNT_MISC_CNTL_BASE_IDX
#define regSDMA3_PERFCNT_PERFCOUNTER_LO
#define regSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX
#define regSDMA3_PERFCNT_PERFCOUNTER_HI
#define regSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX
#define regSDMA3_CRD_CNTL
#define regSDMA3_CRD_CNTL_BASE_IDX
#define regSDMA3_ULV_CNTL
#define regSDMA3_ULV_CNTL_BASE_IDX
#define regSDMA3_EA_DBIT_ADDR_DATA
#define regSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX
#define regSDMA3_EA_DBIT_ADDR_INDEX
#define regSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX
#define regSDMA3_STATUS4_REG
#define regSDMA3_STATUS4_REG_BASE_IDX
#define regSDMA3_SCRATCH_RAM_DATA
#define regSDMA3_SCRATCH_RAM_DATA_BASE_IDX
#define regSDMA3_SCRATCH_RAM_ADDR
#define regSDMA3_SCRATCH_RAM_ADDR_BASE_IDX
#define regSDMA3_CE_CTRL
#define regSDMA3_CE_CTRL_BASE_IDX
#define regSDMA3_RAS_STATUS
#define regSDMA3_RAS_STATUS_BASE_IDX
#define regSDMA3_CLK_STATUS
#define regSDMA3_CLK_STATUS_BASE_IDX
#define regSDMA3_GFX_RB_CNTL
#define regSDMA3_GFX_RB_CNTL_BASE_IDX
#define regSDMA3_GFX_RB_BASE
#define regSDMA3_GFX_RB_BASE_BASE_IDX
#define regSDMA3_GFX_RB_BASE_HI
#define regSDMA3_GFX_RB_BASE_HI_BASE_IDX
#define regSDMA3_GFX_RB_RPTR
#define regSDMA3_GFX_RB_RPTR_BASE_IDX
#define regSDMA3_GFX_RB_RPTR_HI
#define regSDMA3_GFX_RB_RPTR_HI_BASE_IDX
#define regSDMA3_GFX_RB_WPTR
#define regSDMA3_GFX_RB_WPTR_BASE_IDX
#define regSDMA3_GFX_RB_WPTR_HI
#define regSDMA3_GFX_RB_WPTR_HI_BASE_IDX
#define regSDMA3_GFX_RB_WPTR_POLL_CNTL
#define regSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_GFX_RB_RPTR_ADDR_HI
#define regSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_GFX_RB_RPTR_ADDR_LO
#define regSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_GFX_IB_CNTL
#define regSDMA3_GFX_IB_CNTL_BASE_IDX
#define regSDMA3_GFX_IB_RPTR
#define regSDMA3_GFX_IB_RPTR_BASE_IDX
#define regSDMA3_GFX_IB_OFFSET
#define regSDMA3_GFX_IB_OFFSET_BASE_IDX
#define regSDMA3_GFX_IB_BASE_LO
#define regSDMA3_GFX_IB_BASE_LO_BASE_IDX
#define regSDMA3_GFX_IB_BASE_HI
#define regSDMA3_GFX_IB_BASE_HI_BASE_IDX
#define regSDMA3_GFX_IB_SIZE
#define regSDMA3_GFX_IB_SIZE_BASE_IDX
#define regSDMA3_GFX_SKIP_CNTL
#define regSDMA3_GFX_SKIP_CNTL_BASE_IDX
#define regSDMA3_GFX_CONTEXT_STATUS
#define regSDMA3_GFX_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_GFX_DOORBELL
#define regSDMA3_GFX_DOORBELL_BASE_IDX
#define regSDMA3_GFX_CONTEXT_CNTL
#define regSDMA3_GFX_CONTEXT_CNTL_BASE_IDX
#define regSDMA3_GFX_STATUS
#define regSDMA3_GFX_STATUS_BASE_IDX
#define regSDMA3_GFX_DOORBELL_LOG
#define regSDMA3_GFX_DOORBELL_LOG_BASE_IDX
#define regSDMA3_GFX_WATERMARK
#define regSDMA3_GFX_WATERMARK_BASE_IDX
#define regSDMA3_GFX_DOORBELL_OFFSET
#define regSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_GFX_CSA_ADDR_LO
#define regSDMA3_GFX_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_GFX_CSA_ADDR_HI
#define regSDMA3_GFX_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_GFX_IB_SUB_REMAIN
#define regSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_GFX_PREEMPT
#define regSDMA3_GFX_PREEMPT_BASE_IDX
#define regSDMA3_GFX_DUMMY_REG
#define regSDMA3_GFX_DUMMY_REG_BASE_IDX
#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_GFX_RB_AQL_CNTL
#define regSDMA3_GFX_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_GFX_MINOR_PTR_UPDATE
#define regSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA0
#define regSDMA3_GFX_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA1
#define regSDMA3_GFX_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA2
#define regSDMA3_GFX_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA3
#define regSDMA3_GFX_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA4
#define regSDMA3_GFX_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA5
#define regSDMA3_GFX_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA6
#define regSDMA3_GFX_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA7
#define regSDMA3_GFX_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA8
#define regSDMA3_GFX_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA9
#define regSDMA3_GFX_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_GFX_MIDCMD_DATA10
#define regSDMA3_GFX_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_GFX_MIDCMD_CNTL
#define regSDMA3_GFX_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_PAGE_RB_CNTL
#define regSDMA3_PAGE_RB_CNTL_BASE_IDX
#define regSDMA3_PAGE_RB_BASE
#define regSDMA3_PAGE_RB_BASE_BASE_IDX
#define regSDMA3_PAGE_RB_BASE_HI
#define regSDMA3_PAGE_RB_BASE_HI_BASE_IDX
#define regSDMA3_PAGE_RB_RPTR
#define regSDMA3_PAGE_RB_RPTR_BASE_IDX
#define regSDMA3_PAGE_RB_RPTR_HI
#define regSDMA3_PAGE_RB_RPTR_HI_BASE_IDX
#define regSDMA3_PAGE_RB_WPTR
#define regSDMA3_PAGE_RB_WPTR_BASE_IDX
#define regSDMA3_PAGE_RB_WPTR_HI
#define regSDMA3_PAGE_RB_WPTR_HI_BASE_IDX
#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL
#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_PAGE_RB_RPTR_ADDR_HI
#define regSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_PAGE_RB_RPTR_ADDR_LO
#define regSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_PAGE_IB_CNTL
#define regSDMA3_PAGE_IB_CNTL_BASE_IDX
#define regSDMA3_PAGE_IB_RPTR
#define regSDMA3_PAGE_IB_RPTR_BASE_IDX
#define regSDMA3_PAGE_IB_OFFSET
#define regSDMA3_PAGE_IB_OFFSET_BASE_IDX
#define regSDMA3_PAGE_IB_BASE_LO
#define regSDMA3_PAGE_IB_BASE_LO_BASE_IDX
#define regSDMA3_PAGE_IB_BASE_HI
#define regSDMA3_PAGE_IB_BASE_HI_BASE_IDX
#define regSDMA3_PAGE_IB_SIZE
#define regSDMA3_PAGE_IB_SIZE_BASE_IDX
#define regSDMA3_PAGE_SKIP_CNTL
#define regSDMA3_PAGE_SKIP_CNTL_BASE_IDX
#define regSDMA3_PAGE_CONTEXT_STATUS
#define regSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_PAGE_DOORBELL
#define regSDMA3_PAGE_DOORBELL_BASE_IDX
#define regSDMA3_PAGE_STATUS
#define regSDMA3_PAGE_STATUS_BASE_IDX
#define regSDMA3_PAGE_DOORBELL_LOG
#define regSDMA3_PAGE_DOORBELL_LOG_BASE_IDX
#define regSDMA3_PAGE_WATERMARK
#define regSDMA3_PAGE_WATERMARK_BASE_IDX
#define regSDMA3_PAGE_DOORBELL_OFFSET
#define regSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_PAGE_CSA_ADDR_LO
#define regSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_PAGE_CSA_ADDR_HI
#define regSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_PAGE_IB_SUB_REMAIN
#define regSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_PAGE_PREEMPT
#define regSDMA3_PAGE_PREEMPT_BASE_IDX
#define regSDMA3_PAGE_DUMMY_REG
#define regSDMA3_PAGE_DUMMY_REG_BASE_IDX
#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_PAGE_RB_AQL_CNTL
#define regSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_PAGE_MINOR_PTR_UPDATE
#define regSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA0
#define regSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA1
#define regSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA2
#define regSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA3
#define regSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA4
#define regSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA5
#define regSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA6
#define regSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA7
#define regSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA8
#define regSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA9
#define regSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_DATA10
#define regSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_PAGE_MIDCMD_CNTL
#define regSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC0_RB_CNTL
#define regSDMA3_RLC0_RB_CNTL_BASE_IDX
#define regSDMA3_RLC0_RB_BASE
#define regSDMA3_RLC0_RB_BASE_BASE_IDX
#define regSDMA3_RLC0_RB_BASE_HI
#define regSDMA3_RLC0_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC0_RB_RPTR
#define regSDMA3_RLC0_RB_RPTR_BASE_IDX
#define regSDMA3_RLC0_RB_RPTR_HI
#define regSDMA3_RLC0_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC0_RB_WPTR
#define regSDMA3_RLC0_RB_WPTR_BASE_IDX
#define regSDMA3_RLC0_RB_WPTR_HI
#define regSDMA3_RLC0_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC0_RB_RPTR_ADDR_HI
#define regSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC0_RB_RPTR_ADDR_LO
#define regSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC0_IB_CNTL
#define regSDMA3_RLC0_IB_CNTL_BASE_IDX
#define regSDMA3_RLC0_IB_RPTR
#define regSDMA3_RLC0_IB_RPTR_BASE_IDX
#define regSDMA3_RLC0_IB_OFFSET
#define regSDMA3_RLC0_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC0_IB_BASE_LO
#define regSDMA3_RLC0_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC0_IB_BASE_HI
#define regSDMA3_RLC0_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC0_IB_SIZE
#define regSDMA3_RLC0_IB_SIZE_BASE_IDX
#define regSDMA3_RLC0_SKIP_CNTL
#define regSDMA3_RLC0_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC0_CONTEXT_STATUS
#define regSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC0_DOORBELL
#define regSDMA3_RLC0_DOORBELL_BASE_IDX
#define regSDMA3_RLC0_STATUS
#define regSDMA3_RLC0_STATUS_BASE_IDX
#define regSDMA3_RLC0_DOORBELL_LOG
#define regSDMA3_RLC0_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC0_WATERMARK
#define regSDMA3_RLC0_WATERMARK_BASE_IDX
#define regSDMA3_RLC0_DOORBELL_OFFSET
#define regSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC0_CSA_ADDR_LO
#define regSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC0_CSA_ADDR_HI
#define regSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC0_IB_SUB_REMAIN
#define regSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC0_PREEMPT
#define regSDMA3_RLC0_PREEMPT_BASE_IDX
#define regSDMA3_RLC0_DUMMY_REG
#define regSDMA3_RLC0_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC0_RB_AQL_CNTL
#define regSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC0_MINOR_PTR_UPDATE
#define regSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA0
#define regSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA1
#define regSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA2
#define regSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA3
#define regSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA4
#define regSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA5
#define regSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA6
#define regSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA7
#define regSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA8
#define regSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA9
#define regSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_DATA10
#define regSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC0_MIDCMD_CNTL
#define regSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC1_RB_CNTL
#define regSDMA3_RLC1_RB_CNTL_BASE_IDX
#define regSDMA3_RLC1_RB_BASE
#define regSDMA3_RLC1_RB_BASE_BASE_IDX
#define regSDMA3_RLC1_RB_BASE_HI
#define regSDMA3_RLC1_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC1_RB_RPTR
#define regSDMA3_RLC1_RB_RPTR_BASE_IDX
#define regSDMA3_RLC1_RB_RPTR_HI
#define regSDMA3_RLC1_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC1_RB_WPTR
#define regSDMA3_RLC1_RB_WPTR_BASE_IDX
#define regSDMA3_RLC1_RB_WPTR_HI
#define regSDMA3_RLC1_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC1_RB_RPTR_ADDR_HI
#define regSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC1_RB_RPTR_ADDR_LO
#define regSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC1_IB_CNTL
#define regSDMA3_RLC1_IB_CNTL_BASE_IDX
#define regSDMA3_RLC1_IB_RPTR
#define regSDMA3_RLC1_IB_RPTR_BASE_IDX
#define regSDMA3_RLC1_IB_OFFSET
#define regSDMA3_RLC1_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC1_IB_BASE_LO
#define regSDMA3_RLC1_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC1_IB_BASE_HI
#define regSDMA3_RLC1_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC1_IB_SIZE
#define regSDMA3_RLC1_IB_SIZE_BASE_IDX
#define regSDMA3_RLC1_SKIP_CNTL
#define regSDMA3_RLC1_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC1_CONTEXT_STATUS
#define regSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC1_DOORBELL
#define regSDMA3_RLC1_DOORBELL_BASE_IDX
#define regSDMA3_RLC1_STATUS
#define regSDMA3_RLC1_STATUS_BASE_IDX
#define regSDMA3_RLC1_DOORBELL_LOG
#define regSDMA3_RLC1_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC1_WATERMARK
#define regSDMA3_RLC1_WATERMARK_BASE_IDX
#define regSDMA3_RLC1_DOORBELL_OFFSET
#define regSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC1_CSA_ADDR_LO
#define regSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC1_CSA_ADDR_HI
#define regSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC1_IB_SUB_REMAIN
#define regSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC1_PREEMPT
#define regSDMA3_RLC1_PREEMPT_BASE_IDX
#define regSDMA3_RLC1_DUMMY_REG
#define regSDMA3_RLC1_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC1_RB_AQL_CNTL
#define regSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC1_MINOR_PTR_UPDATE
#define regSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA0
#define regSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA1
#define regSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA2
#define regSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA3
#define regSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA4
#define regSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA5
#define regSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA6
#define regSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA7
#define regSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA8
#define regSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA9
#define regSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_DATA10
#define regSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC1_MIDCMD_CNTL
#define regSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC2_RB_CNTL
#define regSDMA3_RLC2_RB_CNTL_BASE_IDX
#define regSDMA3_RLC2_RB_BASE
#define regSDMA3_RLC2_RB_BASE_BASE_IDX
#define regSDMA3_RLC2_RB_BASE_HI
#define regSDMA3_RLC2_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC2_RB_RPTR
#define regSDMA3_RLC2_RB_RPTR_BASE_IDX
#define regSDMA3_RLC2_RB_RPTR_HI
#define regSDMA3_RLC2_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC2_RB_WPTR
#define regSDMA3_RLC2_RB_WPTR_BASE_IDX
#define regSDMA3_RLC2_RB_WPTR_HI
#define regSDMA3_RLC2_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC2_RB_RPTR_ADDR_HI
#define regSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC2_RB_RPTR_ADDR_LO
#define regSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC2_IB_CNTL
#define regSDMA3_RLC2_IB_CNTL_BASE_IDX
#define regSDMA3_RLC2_IB_RPTR
#define regSDMA3_RLC2_IB_RPTR_BASE_IDX
#define regSDMA3_RLC2_IB_OFFSET
#define regSDMA3_RLC2_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC2_IB_BASE_LO
#define regSDMA3_RLC2_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC2_IB_BASE_HI
#define regSDMA3_RLC2_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC2_IB_SIZE
#define regSDMA3_RLC2_IB_SIZE_BASE_IDX
#define regSDMA3_RLC2_SKIP_CNTL
#define regSDMA3_RLC2_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC2_CONTEXT_STATUS
#define regSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC2_DOORBELL
#define regSDMA3_RLC2_DOORBELL_BASE_IDX
#define regSDMA3_RLC2_STATUS
#define regSDMA3_RLC2_STATUS_BASE_IDX
#define regSDMA3_RLC2_DOORBELL_LOG
#define regSDMA3_RLC2_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC2_WATERMARK
#define regSDMA3_RLC2_WATERMARK_BASE_IDX
#define regSDMA3_RLC2_DOORBELL_OFFSET
#define regSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC2_CSA_ADDR_LO
#define regSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC2_CSA_ADDR_HI
#define regSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC2_IB_SUB_REMAIN
#define regSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC2_PREEMPT
#define regSDMA3_RLC2_PREEMPT_BASE_IDX
#define regSDMA3_RLC2_DUMMY_REG
#define regSDMA3_RLC2_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC2_RB_AQL_CNTL
#define regSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC2_MINOR_PTR_UPDATE
#define regSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA0
#define regSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA1
#define regSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA2
#define regSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA3
#define regSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA4
#define regSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA5
#define regSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA6
#define regSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA7
#define regSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA8
#define regSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA9
#define regSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_DATA10
#define regSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC2_MIDCMD_CNTL
#define regSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC3_RB_CNTL
#define regSDMA3_RLC3_RB_CNTL_BASE_IDX
#define regSDMA3_RLC3_RB_BASE
#define regSDMA3_RLC3_RB_BASE_BASE_IDX
#define regSDMA3_RLC3_RB_BASE_HI
#define regSDMA3_RLC3_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC3_RB_RPTR
#define regSDMA3_RLC3_RB_RPTR_BASE_IDX
#define regSDMA3_RLC3_RB_RPTR_HI
#define regSDMA3_RLC3_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC3_RB_WPTR
#define regSDMA3_RLC3_RB_WPTR_BASE_IDX
#define regSDMA3_RLC3_RB_WPTR_HI
#define regSDMA3_RLC3_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC3_RB_RPTR_ADDR_HI
#define regSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC3_RB_RPTR_ADDR_LO
#define regSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC3_IB_CNTL
#define regSDMA3_RLC3_IB_CNTL_BASE_IDX
#define regSDMA3_RLC3_IB_RPTR
#define regSDMA3_RLC3_IB_RPTR_BASE_IDX
#define regSDMA3_RLC3_IB_OFFSET
#define regSDMA3_RLC3_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC3_IB_BASE_LO
#define regSDMA3_RLC3_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC3_IB_BASE_HI
#define regSDMA3_RLC3_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC3_IB_SIZE
#define regSDMA3_RLC3_IB_SIZE_BASE_IDX
#define regSDMA3_RLC3_SKIP_CNTL
#define regSDMA3_RLC3_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC3_CONTEXT_STATUS
#define regSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC3_DOORBELL
#define regSDMA3_RLC3_DOORBELL_BASE_IDX
#define regSDMA3_RLC3_STATUS
#define regSDMA3_RLC3_STATUS_BASE_IDX
#define regSDMA3_RLC3_DOORBELL_LOG
#define regSDMA3_RLC3_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC3_WATERMARK
#define regSDMA3_RLC3_WATERMARK_BASE_IDX
#define regSDMA3_RLC3_DOORBELL_OFFSET
#define regSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC3_CSA_ADDR_LO
#define regSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC3_CSA_ADDR_HI
#define regSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC3_IB_SUB_REMAIN
#define regSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC3_PREEMPT
#define regSDMA3_RLC3_PREEMPT_BASE_IDX
#define regSDMA3_RLC3_DUMMY_REG
#define regSDMA3_RLC3_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC3_RB_AQL_CNTL
#define regSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC3_MINOR_PTR_UPDATE
#define regSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA0
#define regSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA1
#define regSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA2
#define regSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA3
#define regSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA4
#define regSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA5
#define regSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA6
#define regSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA7
#define regSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA8
#define regSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA9
#define regSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_DATA10
#define regSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC3_MIDCMD_CNTL
#define regSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC4_RB_CNTL
#define regSDMA3_RLC4_RB_CNTL_BASE_IDX
#define regSDMA3_RLC4_RB_BASE
#define regSDMA3_RLC4_RB_BASE_BASE_IDX
#define regSDMA3_RLC4_RB_BASE_HI
#define regSDMA3_RLC4_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC4_RB_RPTR
#define regSDMA3_RLC4_RB_RPTR_BASE_IDX
#define regSDMA3_RLC4_RB_RPTR_HI
#define regSDMA3_RLC4_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC4_RB_WPTR
#define regSDMA3_RLC4_RB_WPTR_BASE_IDX
#define regSDMA3_RLC4_RB_WPTR_HI
#define regSDMA3_RLC4_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC4_RB_RPTR_ADDR_HI
#define regSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC4_RB_RPTR_ADDR_LO
#define regSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC4_IB_CNTL
#define regSDMA3_RLC4_IB_CNTL_BASE_IDX
#define regSDMA3_RLC4_IB_RPTR
#define regSDMA3_RLC4_IB_RPTR_BASE_IDX
#define regSDMA3_RLC4_IB_OFFSET
#define regSDMA3_RLC4_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC4_IB_BASE_LO
#define regSDMA3_RLC4_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC4_IB_BASE_HI
#define regSDMA3_RLC4_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC4_IB_SIZE
#define regSDMA3_RLC4_IB_SIZE_BASE_IDX
#define regSDMA3_RLC4_SKIP_CNTL
#define regSDMA3_RLC4_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC4_CONTEXT_STATUS
#define regSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC4_DOORBELL
#define regSDMA3_RLC4_DOORBELL_BASE_IDX
#define regSDMA3_RLC4_STATUS
#define regSDMA3_RLC4_STATUS_BASE_IDX
#define regSDMA3_RLC4_DOORBELL_LOG
#define regSDMA3_RLC4_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC4_WATERMARK
#define regSDMA3_RLC4_WATERMARK_BASE_IDX
#define regSDMA3_RLC4_DOORBELL_OFFSET
#define regSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC4_CSA_ADDR_LO
#define regSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC4_CSA_ADDR_HI
#define regSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC4_IB_SUB_REMAIN
#define regSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC4_PREEMPT
#define regSDMA3_RLC4_PREEMPT_BASE_IDX
#define regSDMA3_RLC4_DUMMY_REG
#define regSDMA3_RLC4_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC4_RB_AQL_CNTL
#define regSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC4_MINOR_PTR_UPDATE
#define regSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA0
#define regSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA1
#define regSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA2
#define regSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA3
#define regSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA4
#define regSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA5
#define regSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA6
#define regSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA7
#define regSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA8
#define regSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA9
#define regSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_DATA10
#define regSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC4_MIDCMD_CNTL
#define regSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC5_RB_CNTL
#define regSDMA3_RLC5_RB_CNTL_BASE_IDX
#define regSDMA3_RLC5_RB_BASE
#define regSDMA3_RLC5_RB_BASE_BASE_IDX
#define regSDMA3_RLC5_RB_BASE_HI
#define regSDMA3_RLC5_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC5_RB_RPTR
#define regSDMA3_RLC5_RB_RPTR_BASE_IDX
#define regSDMA3_RLC5_RB_RPTR_HI
#define regSDMA3_RLC5_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC5_RB_WPTR
#define regSDMA3_RLC5_RB_WPTR_BASE_IDX
#define regSDMA3_RLC5_RB_WPTR_HI
#define regSDMA3_RLC5_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC5_RB_RPTR_ADDR_HI
#define regSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC5_RB_RPTR_ADDR_LO
#define regSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC5_IB_CNTL
#define regSDMA3_RLC5_IB_CNTL_BASE_IDX
#define regSDMA3_RLC5_IB_RPTR
#define regSDMA3_RLC5_IB_RPTR_BASE_IDX
#define regSDMA3_RLC5_IB_OFFSET
#define regSDMA3_RLC5_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC5_IB_BASE_LO
#define regSDMA3_RLC5_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC5_IB_BASE_HI
#define regSDMA3_RLC5_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC5_IB_SIZE
#define regSDMA3_RLC5_IB_SIZE_BASE_IDX
#define regSDMA3_RLC5_SKIP_CNTL
#define regSDMA3_RLC5_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC5_CONTEXT_STATUS
#define regSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC5_DOORBELL
#define regSDMA3_RLC5_DOORBELL_BASE_IDX
#define regSDMA3_RLC5_STATUS
#define regSDMA3_RLC5_STATUS_BASE_IDX
#define regSDMA3_RLC5_DOORBELL_LOG
#define regSDMA3_RLC5_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC5_WATERMARK
#define regSDMA3_RLC5_WATERMARK_BASE_IDX
#define regSDMA3_RLC5_DOORBELL_OFFSET
#define regSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC5_CSA_ADDR_LO
#define regSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC5_CSA_ADDR_HI
#define regSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC5_IB_SUB_REMAIN
#define regSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC5_PREEMPT
#define regSDMA3_RLC5_PREEMPT_BASE_IDX
#define regSDMA3_RLC5_DUMMY_REG
#define regSDMA3_RLC5_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC5_RB_AQL_CNTL
#define regSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC5_MINOR_PTR_UPDATE
#define regSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA0
#define regSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA1
#define regSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA2
#define regSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA3
#define regSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA4
#define regSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA5
#define regSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA6
#define regSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA7
#define regSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA8
#define regSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA9
#define regSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_DATA10
#define regSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC5_MIDCMD_CNTL
#define regSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC6_RB_CNTL
#define regSDMA3_RLC6_RB_CNTL_BASE_IDX
#define regSDMA3_RLC6_RB_BASE
#define regSDMA3_RLC6_RB_BASE_BASE_IDX
#define regSDMA3_RLC6_RB_BASE_HI
#define regSDMA3_RLC6_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC6_RB_RPTR
#define regSDMA3_RLC6_RB_RPTR_BASE_IDX
#define regSDMA3_RLC6_RB_RPTR_HI
#define regSDMA3_RLC6_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC6_RB_WPTR
#define regSDMA3_RLC6_RB_WPTR_BASE_IDX
#define regSDMA3_RLC6_RB_WPTR_HI
#define regSDMA3_RLC6_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC6_RB_RPTR_ADDR_HI
#define regSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC6_RB_RPTR_ADDR_LO
#define regSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC6_IB_CNTL
#define regSDMA3_RLC6_IB_CNTL_BASE_IDX
#define regSDMA3_RLC6_IB_RPTR
#define regSDMA3_RLC6_IB_RPTR_BASE_IDX
#define regSDMA3_RLC6_IB_OFFSET
#define regSDMA3_RLC6_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC6_IB_BASE_LO
#define regSDMA3_RLC6_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC6_IB_BASE_HI
#define regSDMA3_RLC6_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC6_IB_SIZE
#define regSDMA3_RLC6_IB_SIZE_BASE_IDX
#define regSDMA3_RLC6_SKIP_CNTL
#define regSDMA3_RLC6_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC6_CONTEXT_STATUS
#define regSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC6_DOORBELL
#define regSDMA3_RLC6_DOORBELL_BASE_IDX
#define regSDMA3_RLC6_STATUS
#define regSDMA3_RLC6_STATUS_BASE_IDX
#define regSDMA3_RLC6_DOORBELL_LOG
#define regSDMA3_RLC6_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC6_WATERMARK
#define regSDMA3_RLC6_WATERMARK_BASE_IDX
#define regSDMA3_RLC6_DOORBELL_OFFSET
#define regSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC6_CSA_ADDR_LO
#define regSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC6_CSA_ADDR_HI
#define regSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC6_IB_SUB_REMAIN
#define regSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC6_PREEMPT
#define regSDMA3_RLC6_PREEMPT_BASE_IDX
#define regSDMA3_RLC6_DUMMY_REG
#define regSDMA3_RLC6_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC6_RB_AQL_CNTL
#define regSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC6_MINOR_PTR_UPDATE
#define regSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA0
#define regSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA1
#define regSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA2
#define regSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA3
#define regSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA4
#define regSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA5
#define regSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA6
#define regSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA7
#define regSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA8
#define regSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA9
#define regSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_DATA10
#define regSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC6_MIDCMD_CNTL
#define regSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX
#define regSDMA3_RLC7_RB_CNTL
#define regSDMA3_RLC7_RB_CNTL_BASE_IDX
#define regSDMA3_RLC7_RB_BASE
#define regSDMA3_RLC7_RB_BASE_BASE_IDX
#define regSDMA3_RLC7_RB_BASE_HI
#define regSDMA3_RLC7_RB_BASE_HI_BASE_IDX
#define regSDMA3_RLC7_RB_RPTR
#define regSDMA3_RLC7_RB_RPTR_BASE_IDX
#define regSDMA3_RLC7_RB_RPTR_HI
#define regSDMA3_RLC7_RB_RPTR_HI_BASE_IDX
#define regSDMA3_RLC7_RB_WPTR
#define regSDMA3_RLC7_RB_WPTR_BASE_IDX
#define regSDMA3_RLC7_RB_WPTR_HI
#define regSDMA3_RLC7_RB_WPTR_HI_BASE_IDX
#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL
#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA3_RLC7_RB_RPTR_ADDR_HI
#define regSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA3_RLC7_RB_RPTR_ADDR_LO
#define regSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA3_RLC7_IB_CNTL
#define regSDMA3_RLC7_IB_CNTL_BASE_IDX
#define regSDMA3_RLC7_IB_RPTR
#define regSDMA3_RLC7_IB_RPTR_BASE_IDX
#define regSDMA3_RLC7_IB_OFFSET
#define regSDMA3_RLC7_IB_OFFSET_BASE_IDX
#define regSDMA3_RLC7_IB_BASE_LO
#define regSDMA3_RLC7_IB_BASE_LO_BASE_IDX
#define regSDMA3_RLC7_IB_BASE_HI
#define regSDMA3_RLC7_IB_BASE_HI_BASE_IDX
#define regSDMA3_RLC7_IB_SIZE
#define regSDMA3_RLC7_IB_SIZE_BASE_IDX
#define regSDMA3_RLC7_SKIP_CNTL
#define regSDMA3_RLC7_SKIP_CNTL_BASE_IDX
#define regSDMA3_RLC7_CONTEXT_STATUS
#define regSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX
#define regSDMA3_RLC7_DOORBELL
#define regSDMA3_RLC7_DOORBELL_BASE_IDX
#define regSDMA3_RLC7_STATUS
#define regSDMA3_RLC7_STATUS_BASE_IDX
#define regSDMA3_RLC7_DOORBELL_LOG
#define regSDMA3_RLC7_DOORBELL_LOG_BASE_IDX
#define regSDMA3_RLC7_WATERMARK
#define regSDMA3_RLC7_WATERMARK_BASE_IDX
#define regSDMA3_RLC7_DOORBELL_OFFSET
#define regSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX
#define regSDMA3_RLC7_CSA_ADDR_LO
#define regSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX
#define regSDMA3_RLC7_CSA_ADDR_HI
#define regSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX
#define regSDMA3_RLC7_IB_SUB_REMAIN
#define regSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX
#define regSDMA3_RLC7_PREEMPT
#define regSDMA3_RLC7_PREEMPT_BASE_IDX
#define regSDMA3_RLC7_DUMMY_REG
#define regSDMA3_RLC7_DUMMY_REG_BASE_IDX
#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI
#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO
#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA3_RLC7_RB_AQL_CNTL
#define regSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX
#define regSDMA3_RLC7_MINOR_PTR_UPDATE
#define regSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA0
#define regSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA1
#define regSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA2
#define regSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA3
#define regSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA4
#define regSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA5
#define regSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA6
#define regSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA7
#define regSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA8
#define regSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA9
#define regSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_DATA10
#define regSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX
#define regSDMA3_RLC7_MIDCMD_CNTL
#define regSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX


// addressBlock: sdma0_sdma4dec
// base address: 0x7a000
#define regSDMA4_UCODE_ADDR
#define regSDMA4_UCODE_ADDR_BASE_IDX
#define regSDMA4_UCODE_DATA
#define regSDMA4_UCODE_DATA_BASE_IDX
#define regSDMA4_VF_ENABLE
#define regSDMA4_VF_ENABLE_BASE_IDX
#define regSDMA4_CONTEXT_GROUP_BOUNDARY
#define regSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX
#define regSDMA4_POWER_CNTL
#define regSDMA4_POWER_CNTL_BASE_IDX
#define regSDMA4_CLK_CTRL
#define regSDMA4_CLK_CTRL_BASE_IDX
#define regSDMA4_CNTL
#define regSDMA4_CNTL_BASE_IDX
#define regSDMA4_CHICKEN_BITS
#define regSDMA4_CHICKEN_BITS_BASE_IDX
#define regSDMA4_GB_ADDR_CONFIG
#define regSDMA4_GB_ADDR_CONFIG_BASE_IDX
#define regSDMA4_GB_ADDR_CONFIG_READ
#define regSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX
#define regSDMA4_RB_RPTR_FETCH_HI
#define regSDMA4_RB_RPTR_FETCH_HI_BASE_IDX
#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL
#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX
#define regSDMA4_RB_RPTR_FETCH
#define regSDMA4_RB_RPTR_FETCH_BASE_IDX
#define regSDMA4_IB_OFFSET_FETCH
#define regSDMA4_IB_OFFSET_FETCH_BASE_IDX
#define regSDMA4_PROGRAM
#define regSDMA4_PROGRAM_BASE_IDX
#define regSDMA4_STATUS_REG
#define regSDMA4_STATUS_REG_BASE_IDX
#define regSDMA4_STATUS1_REG
#define regSDMA4_STATUS1_REG_BASE_IDX
#define regSDMA4_RD_BURST_CNTL
#define regSDMA4_RD_BURST_CNTL_BASE_IDX
#define regSDMA4_HBM_PAGE_CONFIG
#define regSDMA4_HBM_PAGE_CONFIG_BASE_IDX
#define regSDMA4_UCODE_CHECKSUM
#define regSDMA4_UCODE_CHECKSUM_BASE_IDX
#define regSDMA4_F32_CNTL
#define regSDMA4_F32_CNTL_BASE_IDX
#define regSDMA4_FREEZE
#define regSDMA4_FREEZE_BASE_IDX
#define regSDMA4_PHASE0_QUANTUM
#define regSDMA4_PHASE0_QUANTUM_BASE_IDX
#define regSDMA4_PHASE1_QUANTUM
#define regSDMA4_PHASE1_QUANTUM_BASE_IDX
#define regCC_SDMA4_EDC_CONFIG
#define regCC_SDMA4_EDC_CONFIG_BASE_IDX
#define regSDMA4_BA_THRESHOLD
#define regSDMA4_BA_THRESHOLD_BASE_IDX
#define regSDMA4_ID
#define regSDMA4_ID_BASE_IDX
#define regSDMA4_VERSION
#define regSDMA4_VERSION_BASE_IDX
#define regSDMA4_EDC_COUNTER
#define regSDMA4_EDC_COUNTER_BASE_IDX
#define regSDMA4_EDC_COUNTER2
#define regSDMA4_EDC_COUNTER2_BASE_IDX
#define regSDMA4_STATUS2_REG
#define regSDMA4_STATUS2_REG_BASE_IDX
#define regSDMA4_ATOMIC_CNTL
#define regSDMA4_ATOMIC_CNTL_BASE_IDX
#define regSDMA4_ATOMIC_PREOP_LO
#define regSDMA4_ATOMIC_PREOP_LO_BASE_IDX
#define regSDMA4_ATOMIC_PREOP_HI
#define regSDMA4_ATOMIC_PREOP_HI_BASE_IDX
#define regSDMA4_UTCL1_CNTL
#define regSDMA4_UTCL1_CNTL_BASE_IDX
#define regSDMA4_UTCL1_WATERMK
#define regSDMA4_UTCL1_WATERMK_BASE_IDX
#define regSDMA4_UTCL1_RD_STATUS
#define regSDMA4_UTCL1_RD_STATUS_BASE_IDX
#define regSDMA4_UTCL1_WR_STATUS
#define regSDMA4_UTCL1_WR_STATUS_BASE_IDX
#define regSDMA4_UTCL1_INV0
#define regSDMA4_UTCL1_INV0_BASE_IDX
#define regSDMA4_UTCL1_INV1
#define regSDMA4_UTCL1_INV1_BASE_IDX
#define regSDMA4_UTCL1_INV2
#define regSDMA4_UTCL1_INV2_BASE_IDX
#define regSDMA4_UTCL1_RD_XNACK0
#define regSDMA4_UTCL1_RD_XNACK0_BASE_IDX
#define regSDMA4_UTCL1_RD_XNACK1
#define regSDMA4_UTCL1_RD_XNACK1_BASE_IDX
#define regSDMA4_UTCL1_WR_XNACK0
#define regSDMA4_UTCL1_WR_XNACK0_BASE_IDX
#define regSDMA4_UTCL1_WR_XNACK1
#define regSDMA4_UTCL1_WR_XNACK1_BASE_IDX
#define regSDMA4_UTCL1_TIMEOUT
#define regSDMA4_UTCL1_TIMEOUT_BASE_IDX
#define regSDMA4_UTCL1_PAGE
#define regSDMA4_UTCL1_PAGE_BASE_IDX
#define regSDMA4_POWER_CNTL_IDLE
#define regSDMA4_POWER_CNTL_IDLE_BASE_IDX
#define regSDMA4_RELAX_ORDERING_LUT
#define regSDMA4_RELAX_ORDERING_LUT_BASE_IDX
#define regSDMA4_CHICKEN_BITS_2
#define regSDMA4_CHICKEN_BITS_2_BASE_IDX
#define regSDMA4_STATUS3_REG
#define regSDMA4_STATUS3_REG_BASE_IDX
#define regSDMA4_PHYSICAL_ADDR_LO
#define regSDMA4_PHYSICAL_ADDR_LO_BASE_IDX
#define regSDMA4_PHYSICAL_ADDR_HI
#define regSDMA4_PHYSICAL_ADDR_HI_BASE_IDX
#define regSDMA4_PHASE2_QUANTUM
#define regSDMA4_PHASE2_QUANTUM_BASE_IDX
#define regSDMA4_ERROR_LOG
#define regSDMA4_ERROR_LOG_BASE_IDX
#define regSDMA4_PUB_DUMMY_REG0
#define regSDMA4_PUB_DUMMY_REG0_BASE_IDX
#define regSDMA4_PUB_DUMMY_REG1
#define regSDMA4_PUB_DUMMY_REG1_BASE_IDX
#define regSDMA4_PUB_DUMMY_REG2
#define regSDMA4_PUB_DUMMY_REG2_BASE_IDX
#define regSDMA4_PUB_DUMMY_REG3
#define regSDMA4_PUB_DUMMY_REG3_BASE_IDX
#define regSDMA4_F32_COUNTER
#define regSDMA4_F32_COUNTER_BASE_IDX
#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG
#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX
#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG
#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX
#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX
#define regSDMA4_PERFCNT_MISC_CNTL
#define regSDMA4_PERFCNT_MISC_CNTL_BASE_IDX
#define regSDMA4_PERFCNT_PERFCOUNTER_LO
#define regSDMA4_PERFCNT_PERFCOUNTER_LO_BASE_IDX
#define regSDMA4_PERFCNT_PERFCOUNTER_HI
#define regSDMA4_PERFCNT_PERFCOUNTER_HI_BASE_IDX
#define regSDMA4_CRD_CNTL
#define regSDMA4_CRD_CNTL_BASE_IDX
#define regSDMA4_ULV_CNTL
#define regSDMA4_ULV_CNTL_BASE_IDX
#define regSDMA4_EA_DBIT_ADDR_DATA
#define regSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX
#define regSDMA4_EA_DBIT_ADDR_INDEX
#define regSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX
#define regSDMA4_STATUS4_REG
#define regSDMA4_STATUS4_REG_BASE_IDX
#define regSDMA4_SCRATCH_RAM_DATA
#define regSDMA4_SCRATCH_RAM_DATA_BASE_IDX
#define regSDMA4_SCRATCH_RAM_ADDR
#define regSDMA4_SCRATCH_RAM_ADDR_BASE_IDX
#define regSDMA4_CE_CTRL
#define regSDMA4_CE_CTRL_BASE_IDX
#define regSDMA4_RAS_STATUS
#define regSDMA4_RAS_STATUS_BASE_IDX
#define regSDMA4_CLK_STATUS
#define regSDMA4_CLK_STATUS_BASE_IDX
#define regSDMA4_GFX_RB_CNTL
#define regSDMA4_GFX_RB_CNTL_BASE_IDX
#define regSDMA4_GFX_RB_BASE
#define regSDMA4_GFX_RB_BASE_BASE_IDX
#define regSDMA4_GFX_RB_BASE_HI
#define regSDMA4_GFX_RB_BASE_HI_BASE_IDX
#define regSDMA4_GFX_RB_RPTR
#define regSDMA4_GFX_RB_RPTR_BASE_IDX
#define regSDMA4_GFX_RB_RPTR_HI
#define regSDMA4_GFX_RB_RPTR_HI_BASE_IDX
#define regSDMA4_GFX_RB_WPTR
#define regSDMA4_GFX_RB_WPTR_BASE_IDX
#define regSDMA4_GFX_RB_WPTR_HI
#define regSDMA4_GFX_RB_WPTR_HI_BASE_IDX
#define regSDMA4_GFX_RB_WPTR_POLL_CNTL
#define regSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_GFX_RB_RPTR_ADDR_HI
#define regSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_GFX_RB_RPTR_ADDR_LO
#define regSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_GFX_IB_CNTL
#define regSDMA4_GFX_IB_CNTL_BASE_IDX
#define regSDMA4_GFX_IB_RPTR
#define regSDMA4_GFX_IB_RPTR_BASE_IDX
#define regSDMA4_GFX_IB_OFFSET
#define regSDMA4_GFX_IB_OFFSET_BASE_IDX
#define regSDMA4_GFX_IB_BASE_LO
#define regSDMA4_GFX_IB_BASE_LO_BASE_IDX
#define regSDMA4_GFX_IB_BASE_HI
#define regSDMA4_GFX_IB_BASE_HI_BASE_IDX
#define regSDMA4_GFX_IB_SIZE
#define regSDMA4_GFX_IB_SIZE_BASE_IDX
#define regSDMA4_GFX_SKIP_CNTL
#define regSDMA4_GFX_SKIP_CNTL_BASE_IDX
#define regSDMA4_GFX_CONTEXT_STATUS
#define regSDMA4_GFX_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_GFX_DOORBELL
#define regSDMA4_GFX_DOORBELL_BASE_IDX
#define regSDMA4_GFX_CONTEXT_CNTL
#define regSDMA4_GFX_CONTEXT_CNTL_BASE_IDX
#define regSDMA4_GFX_STATUS
#define regSDMA4_GFX_STATUS_BASE_IDX
#define regSDMA4_GFX_DOORBELL_LOG
#define regSDMA4_GFX_DOORBELL_LOG_BASE_IDX
#define regSDMA4_GFX_WATERMARK
#define regSDMA4_GFX_WATERMARK_BASE_IDX
#define regSDMA4_GFX_DOORBELL_OFFSET
#define regSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_GFX_CSA_ADDR_LO
#define regSDMA4_GFX_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_GFX_CSA_ADDR_HI
#define regSDMA4_GFX_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_GFX_IB_SUB_REMAIN
#define regSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_GFX_PREEMPT
#define regSDMA4_GFX_PREEMPT_BASE_IDX
#define regSDMA4_GFX_DUMMY_REG
#define regSDMA4_GFX_DUMMY_REG_BASE_IDX
#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_GFX_RB_AQL_CNTL
#define regSDMA4_GFX_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_GFX_MINOR_PTR_UPDATE
#define regSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA0
#define regSDMA4_GFX_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA1
#define regSDMA4_GFX_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA2
#define regSDMA4_GFX_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA3
#define regSDMA4_GFX_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA4
#define regSDMA4_GFX_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA5
#define regSDMA4_GFX_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA6
#define regSDMA4_GFX_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA7
#define regSDMA4_GFX_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA8
#define regSDMA4_GFX_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA9
#define regSDMA4_GFX_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_GFX_MIDCMD_DATA10
#define regSDMA4_GFX_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_GFX_MIDCMD_CNTL
#define regSDMA4_GFX_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_PAGE_RB_CNTL
#define regSDMA4_PAGE_RB_CNTL_BASE_IDX
#define regSDMA4_PAGE_RB_BASE
#define regSDMA4_PAGE_RB_BASE_BASE_IDX
#define regSDMA4_PAGE_RB_BASE_HI
#define regSDMA4_PAGE_RB_BASE_HI_BASE_IDX
#define regSDMA4_PAGE_RB_RPTR
#define regSDMA4_PAGE_RB_RPTR_BASE_IDX
#define regSDMA4_PAGE_RB_RPTR_HI
#define regSDMA4_PAGE_RB_RPTR_HI_BASE_IDX
#define regSDMA4_PAGE_RB_WPTR
#define regSDMA4_PAGE_RB_WPTR_BASE_IDX
#define regSDMA4_PAGE_RB_WPTR_HI
#define regSDMA4_PAGE_RB_WPTR_HI_BASE_IDX
#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL
#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_PAGE_RB_RPTR_ADDR_HI
#define regSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_PAGE_RB_RPTR_ADDR_LO
#define regSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_PAGE_IB_CNTL
#define regSDMA4_PAGE_IB_CNTL_BASE_IDX
#define regSDMA4_PAGE_IB_RPTR
#define regSDMA4_PAGE_IB_RPTR_BASE_IDX
#define regSDMA4_PAGE_IB_OFFSET
#define regSDMA4_PAGE_IB_OFFSET_BASE_IDX
#define regSDMA4_PAGE_IB_BASE_LO
#define regSDMA4_PAGE_IB_BASE_LO_BASE_IDX
#define regSDMA4_PAGE_IB_BASE_HI
#define regSDMA4_PAGE_IB_BASE_HI_BASE_IDX
#define regSDMA4_PAGE_IB_SIZE
#define regSDMA4_PAGE_IB_SIZE_BASE_IDX
#define regSDMA4_PAGE_SKIP_CNTL
#define regSDMA4_PAGE_SKIP_CNTL_BASE_IDX
#define regSDMA4_PAGE_CONTEXT_STATUS
#define regSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_PAGE_DOORBELL
#define regSDMA4_PAGE_DOORBELL_BASE_IDX
#define regSDMA4_PAGE_STATUS
#define regSDMA4_PAGE_STATUS_BASE_IDX
#define regSDMA4_PAGE_DOORBELL_LOG
#define regSDMA4_PAGE_DOORBELL_LOG_BASE_IDX
#define regSDMA4_PAGE_WATERMARK
#define regSDMA4_PAGE_WATERMARK_BASE_IDX
#define regSDMA4_PAGE_DOORBELL_OFFSET
#define regSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_PAGE_CSA_ADDR_LO
#define regSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_PAGE_CSA_ADDR_HI
#define regSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_PAGE_IB_SUB_REMAIN
#define regSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_PAGE_PREEMPT
#define regSDMA4_PAGE_PREEMPT_BASE_IDX
#define regSDMA4_PAGE_DUMMY_REG
#define regSDMA4_PAGE_DUMMY_REG_BASE_IDX
#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_PAGE_RB_AQL_CNTL
#define regSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_PAGE_MINOR_PTR_UPDATE
#define regSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA0
#define regSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA1
#define regSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA2
#define regSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA3
#define regSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA4
#define regSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA5
#define regSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA6
#define regSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA7
#define regSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA8
#define regSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA9
#define regSDMA4_PAGE_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_DATA10
#define regSDMA4_PAGE_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_PAGE_MIDCMD_CNTL
#define regSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC0_RB_CNTL
#define regSDMA4_RLC0_RB_CNTL_BASE_IDX
#define regSDMA4_RLC0_RB_BASE
#define regSDMA4_RLC0_RB_BASE_BASE_IDX
#define regSDMA4_RLC0_RB_BASE_HI
#define regSDMA4_RLC0_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC0_RB_RPTR
#define regSDMA4_RLC0_RB_RPTR_BASE_IDX
#define regSDMA4_RLC0_RB_RPTR_HI
#define regSDMA4_RLC0_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC0_RB_WPTR
#define regSDMA4_RLC0_RB_WPTR_BASE_IDX
#define regSDMA4_RLC0_RB_WPTR_HI
#define regSDMA4_RLC0_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC0_RB_RPTR_ADDR_HI
#define regSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC0_RB_RPTR_ADDR_LO
#define regSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC0_IB_CNTL
#define regSDMA4_RLC0_IB_CNTL_BASE_IDX
#define regSDMA4_RLC0_IB_RPTR
#define regSDMA4_RLC0_IB_RPTR_BASE_IDX
#define regSDMA4_RLC0_IB_OFFSET
#define regSDMA4_RLC0_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC0_IB_BASE_LO
#define regSDMA4_RLC0_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC0_IB_BASE_HI
#define regSDMA4_RLC0_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC0_IB_SIZE
#define regSDMA4_RLC0_IB_SIZE_BASE_IDX
#define regSDMA4_RLC0_SKIP_CNTL
#define regSDMA4_RLC0_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC0_CONTEXT_STATUS
#define regSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC0_DOORBELL
#define regSDMA4_RLC0_DOORBELL_BASE_IDX
#define regSDMA4_RLC0_STATUS
#define regSDMA4_RLC0_STATUS_BASE_IDX
#define regSDMA4_RLC0_DOORBELL_LOG
#define regSDMA4_RLC0_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC0_WATERMARK
#define regSDMA4_RLC0_WATERMARK_BASE_IDX
#define regSDMA4_RLC0_DOORBELL_OFFSET
#define regSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC0_CSA_ADDR_LO
#define regSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC0_CSA_ADDR_HI
#define regSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC0_IB_SUB_REMAIN
#define regSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC0_PREEMPT
#define regSDMA4_RLC0_PREEMPT_BASE_IDX
#define regSDMA4_RLC0_DUMMY_REG
#define regSDMA4_RLC0_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC0_RB_AQL_CNTL
#define regSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC0_MINOR_PTR_UPDATE
#define regSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA0
#define regSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA1
#define regSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA2
#define regSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA3
#define regSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA4
#define regSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA5
#define regSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA6
#define regSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA7
#define regSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA8
#define regSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA9
#define regSDMA4_RLC0_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_DATA10
#define regSDMA4_RLC0_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC0_MIDCMD_CNTL
#define regSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC1_RB_CNTL
#define regSDMA4_RLC1_RB_CNTL_BASE_IDX
#define regSDMA4_RLC1_RB_BASE
#define regSDMA4_RLC1_RB_BASE_BASE_IDX
#define regSDMA4_RLC1_RB_BASE_HI
#define regSDMA4_RLC1_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC1_RB_RPTR
#define regSDMA4_RLC1_RB_RPTR_BASE_IDX
#define regSDMA4_RLC1_RB_RPTR_HI
#define regSDMA4_RLC1_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC1_RB_WPTR
#define regSDMA4_RLC1_RB_WPTR_BASE_IDX
#define regSDMA4_RLC1_RB_WPTR_HI
#define regSDMA4_RLC1_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC1_RB_RPTR_ADDR_HI
#define regSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC1_RB_RPTR_ADDR_LO
#define regSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC1_IB_CNTL
#define regSDMA4_RLC1_IB_CNTL_BASE_IDX
#define regSDMA4_RLC1_IB_RPTR
#define regSDMA4_RLC1_IB_RPTR_BASE_IDX
#define regSDMA4_RLC1_IB_OFFSET
#define regSDMA4_RLC1_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC1_IB_BASE_LO
#define regSDMA4_RLC1_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC1_IB_BASE_HI
#define regSDMA4_RLC1_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC1_IB_SIZE
#define regSDMA4_RLC1_IB_SIZE_BASE_IDX
#define regSDMA4_RLC1_SKIP_CNTL
#define regSDMA4_RLC1_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC1_CONTEXT_STATUS
#define regSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC1_DOORBELL
#define regSDMA4_RLC1_DOORBELL_BASE_IDX
#define regSDMA4_RLC1_STATUS
#define regSDMA4_RLC1_STATUS_BASE_IDX
#define regSDMA4_RLC1_DOORBELL_LOG
#define regSDMA4_RLC1_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC1_WATERMARK
#define regSDMA4_RLC1_WATERMARK_BASE_IDX
#define regSDMA4_RLC1_DOORBELL_OFFSET
#define regSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC1_CSA_ADDR_LO
#define regSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC1_CSA_ADDR_HI
#define regSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC1_IB_SUB_REMAIN
#define regSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC1_PREEMPT
#define regSDMA4_RLC1_PREEMPT_BASE_IDX
#define regSDMA4_RLC1_DUMMY_REG
#define regSDMA4_RLC1_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC1_RB_AQL_CNTL
#define regSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC1_MINOR_PTR_UPDATE
#define regSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA0
#define regSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA1
#define regSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA2
#define regSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA3
#define regSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA4
#define regSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA5
#define regSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA6
#define regSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA7
#define regSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA8
#define regSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA9
#define regSDMA4_RLC1_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_DATA10
#define regSDMA4_RLC1_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC1_MIDCMD_CNTL
#define regSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC2_RB_CNTL
#define regSDMA4_RLC2_RB_CNTL_BASE_IDX
#define regSDMA4_RLC2_RB_BASE
#define regSDMA4_RLC2_RB_BASE_BASE_IDX
#define regSDMA4_RLC2_RB_BASE_HI
#define regSDMA4_RLC2_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC2_RB_RPTR
#define regSDMA4_RLC2_RB_RPTR_BASE_IDX
#define regSDMA4_RLC2_RB_RPTR_HI
#define regSDMA4_RLC2_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC2_RB_WPTR
#define regSDMA4_RLC2_RB_WPTR_BASE_IDX
#define regSDMA4_RLC2_RB_WPTR_HI
#define regSDMA4_RLC2_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC2_RB_RPTR_ADDR_HI
#define regSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC2_RB_RPTR_ADDR_LO
#define regSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC2_IB_CNTL
#define regSDMA4_RLC2_IB_CNTL_BASE_IDX
#define regSDMA4_RLC2_IB_RPTR
#define regSDMA4_RLC2_IB_RPTR_BASE_IDX
#define regSDMA4_RLC2_IB_OFFSET
#define regSDMA4_RLC2_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC2_IB_BASE_LO
#define regSDMA4_RLC2_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC2_IB_BASE_HI
#define regSDMA4_RLC2_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC2_IB_SIZE
#define regSDMA4_RLC2_IB_SIZE_BASE_IDX
#define regSDMA4_RLC2_SKIP_CNTL
#define regSDMA4_RLC2_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC2_CONTEXT_STATUS
#define regSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC2_DOORBELL
#define regSDMA4_RLC2_DOORBELL_BASE_IDX
#define regSDMA4_RLC2_STATUS
#define regSDMA4_RLC2_STATUS_BASE_IDX
#define regSDMA4_RLC2_DOORBELL_LOG
#define regSDMA4_RLC2_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC2_WATERMARK
#define regSDMA4_RLC2_WATERMARK_BASE_IDX
#define regSDMA4_RLC2_DOORBELL_OFFSET
#define regSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC2_CSA_ADDR_LO
#define regSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC2_CSA_ADDR_HI
#define regSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC2_IB_SUB_REMAIN
#define regSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC2_PREEMPT
#define regSDMA4_RLC2_PREEMPT_BASE_IDX
#define regSDMA4_RLC2_DUMMY_REG
#define regSDMA4_RLC2_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC2_RB_AQL_CNTL
#define regSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC2_MINOR_PTR_UPDATE
#define regSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA0
#define regSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA1
#define regSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA2
#define regSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA3
#define regSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA4
#define regSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA5
#define regSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA6
#define regSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA7
#define regSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA8
#define regSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA9
#define regSDMA4_RLC2_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_DATA10
#define regSDMA4_RLC2_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC2_MIDCMD_CNTL
#define regSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC3_RB_CNTL
#define regSDMA4_RLC3_RB_CNTL_BASE_IDX
#define regSDMA4_RLC3_RB_BASE
#define regSDMA4_RLC3_RB_BASE_BASE_IDX
#define regSDMA4_RLC3_RB_BASE_HI
#define regSDMA4_RLC3_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC3_RB_RPTR
#define regSDMA4_RLC3_RB_RPTR_BASE_IDX
#define regSDMA4_RLC3_RB_RPTR_HI
#define regSDMA4_RLC3_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC3_RB_WPTR
#define regSDMA4_RLC3_RB_WPTR_BASE_IDX
#define regSDMA4_RLC3_RB_WPTR_HI
#define regSDMA4_RLC3_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC3_RB_RPTR_ADDR_HI
#define regSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC3_RB_RPTR_ADDR_LO
#define regSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC3_IB_CNTL
#define regSDMA4_RLC3_IB_CNTL_BASE_IDX
#define regSDMA4_RLC3_IB_RPTR
#define regSDMA4_RLC3_IB_RPTR_BASE_IDX
#define regSDMA4_RLC3_IB_OFFSET
#define regSDMA4_RLC3_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC3_IB_BASE_LO
#define regSDMA4_RLC3_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC3_IB_BASE_HI
#define regSDMA4_RLC3_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC3_IB_SIZE
#define regSDMA4_RLC3_IB_SIZE_BASE_IDX
#define regSDMA4_RLC3_SKIP_CNTL
#define regSDMA4_RLC3_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC3_CONTEXT_STATUS
#define regSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC3_DOORBELL
#define regSDMA4_RLC3_DOORBELL_BASE_IDX
#define regSDMA4_RLC3_STATUS
#define regSDMA4_RLC3_STATUS_BASE_IDX
#define regSDMA4_RLC3_DOORBELL_LOG
#define regSDMA4_RLC3_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC3_WATERMARK
#define regSDMA4_RLC3_WATERMARK_BASE_IDX
#define regSDMA4_RLC3_DOORBELL_OFFSET
#define regSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC3_CSA_ADDR_LO
#define regSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC3_CSA_ADDR_HI
#define regSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC3_IB_SUB_REMAIN
#define regSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC3_PREEMPT
#define regSDMA4_RLC3_PREEMPT_BASE_IDX
#define regSDMA4_RLC3_DUMMY_REG
#define regSDMA4_RLC3_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC3_RB_AQL_CNTL
#define regSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC3_MINOR_PTR_UPDATE
#define regSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA0
#define regSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA1
#define regSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA2
#define regSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA3
#define regSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA4
#define regSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA5
#define regSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA6
#define regSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA7
#define regSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA8
#define regSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA9
#define regSDMA4_RLC3_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_DATA10
#define regSDMA4_RLC3_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC3_MIDCMD_CNTL
#define regSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC4_RB_CNTL
#define regSDMA4_RLC4_RB_CNTL_BASE_IDX
#define regSDMA4_RLC4_RB_BASE
#define regSDMA4_RLC4_RB_BASE_BASE_IDX
#define regSDMA4_RLC4_RB_BASE_HI
#define regSDMA4_RLC4_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC4_RB_RPTR
#define regSDMA4_RLC4_RB_RPTR_BASE_IDX
#define regSDMA4_RLC4_RB_RPTR_HI
#define regSDMA4_RLC4_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC4_RB_WPTR
#define regSDMA4_RLC4_RB_WPTR_BASE_IDX
#define regSDMA4_RLC4_RB_WPTR_HI
#define regSDMA4_RLC4_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC4_RB_RPTR_ADDR_HI
#define regSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC4_RB_RPTR_ADDR_LO
#define regSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC4_IB_CNTL
#define regSDMA4_RLC4_IB_CNTL_BASE_IDX
#define regSDMA4_RLC4_IB_RPTR
#define regSDMA4_RLC4_IB_RPTR_BASE_IDX
#define regSDMA4_RLC4_IB_OFFSET
#define regSDMA4_RLC4_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC4_IB_BASE_LO
#define regSDMA4_RLC4_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC4_IB_BASE_HI
#define regSDMA4_RLC4_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC4_IB_SIZE
#define regSDMA4_RLC4_IB_SIZE_BASE_IDX
#define regSDMA4_RLC4_SKIP_CNTL
#define regSDMA4_RLC4_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC4_CONTEXT_STATUS
#define regSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC4_DOORBELL
#define regSDMA4_RLC4_DOORBELL_BASE_IDX
#define regSDMA4_RLC4_STATUS
#define regSDMA4_RLC4_STATUS_BASE_IDX
#define regSDMA4_RLC4_DOORBELL_LOG
#define regSDMA4_RLC4_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC4_WATERMARK
#define regSDMA4_RLC4_WATERMARK_BASE_IDX
#define regSDMA4_RLC4_DOORBELL_OFFSET
#define regSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC4_CSA_ADDR_LO
#define regSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC4_CSA_ADDR_HI
#define regSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC4_IB_SUB_REMAIN
#define regSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC4_PREEMPT
#define regSDMA4_RLC4_PREEMPT_BASE_IDX
#define regSDMA4_RLC4_DUMMY_REG
#define regSDMA4_RLC4_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC4_RB_AQL_CNTL
#define regSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC4_MINOR_PTR_UPDATE
#define regSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA0
#define regSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA1
#define regSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA2
#define regSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA3
#define regSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA4
#define regSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA5
#define regSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA6
#define regSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA7
#define regSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA8
#define regSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA9
#define regSDMA4_RLC4_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_DATA10
#define regSDMA4_RLC4_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC4_MIDCMD_CNTL
#define regSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC5_RB_CNTL
#define regSDMA4_RLC5_RB_CNTL_BASE_IDX
#define regSDMA4_RLC5_RB_BASE
#define regSDMA4_RLC5_RB_BASE_BASE_IDX
#define regSDMA4_RLC5_RB_BASE_HI
#define regSDMA4_RLC5_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC5_RB_RPTR
#define regSDMA4_RLC5_RB_RPTR_BASE_IDX
#define regSDMA4_RLC5_RB_RPTR_HI
#define regSDMA4_RLC5_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC5_RB_WPTR
#define regSDMA4_RLC5_RB_WPTR_BASE_IDX
#define regSDMA4_RLC5_RB_WPTR_HI
#define regSDMA4_RLC5_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC5_RB_RPTR_ADDR_HI
#define regSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC5_RB_RPTR_ADDR_LO
#define regSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC5_IB_CNTL
#define regSDMA4_RLC5_IB_CNTL_BASE_IDX
#define regSDMA4_RLC5_IB_RPTR
#define regSDMA4_RLC5_IB_RPTR_BASE_IDX
#define regSDMA4_RLC5_IB_OFFSET
#define regSDMA4_RLC5_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC5_IB_BASE_LO
#define regSDMA4_RLC5_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC5_IB_BASE_HI
#define regSDMA4_RLC5_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC5_IB_SIZE
#define regSDMA4_RLC5_IB_SIZE_BASE_IDX
#define regSDMA4_RLC5_SKIP_CNTL
#define regSDMA4_RLC5_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC5_CONTEXT_STATUS
#define regSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC5_DOORBELL
#define regSDMA4_RLC5_DOORBELL_BASE_IDX
#define regSDMA4_RLC5_STATUS
#define regSDMA4_RLC5_STATUS_BASE_IDX
#define regSDMA4_RLC5_DOORBELL_LOG
#define regSDMA4_RLC5_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC5_WATERMARK
#define regSDMA4_RLC5_WATERMARK_BASE_IDX
#define regSDMA4_RLC5_DOORBELL_OFFSET
#define regSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC5_CSA_ADDR_LO
#define regSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC5_CSA_ADDR_HI
#define regSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC5_IB_SUB_REMAIN
#define regSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC5_PREEMPT
#define regSDMA4_RLC5_PREEMPT_BASE_IDX
#define regSDMA4_RLC5_DUMMY_REG
#define regSDMA4_RLC5_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC5_RB_AQL_CNTL
#define regSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC5_MINOR_PTR_UPDATE
#define regSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA0
#define regSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA1
#define regSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA2
#define regSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA3
#define regSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA4
#define regSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA5
#define regSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA6
#define regSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA7
#define regSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA8
#define regSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA9
#define regSDMA4_RLC5_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_DATA10
#define regSDMA4_RLC5_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC5_MIDCMD_CNTL
#define regSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC6_RB_CNTL
#define regSDMA4_RLC6_RB_CNTL_BASE_IDX
#define regSDMA4_RLC6_RB_BASE
#define regSDMA4_RLC6_RB_BASE_BASE_IDX
#define regSDMA4_RLC6_RB_BASE_HI
#define regSDMA4_RLC6_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC6_RB_RPTR
#define regSDMA4_RLC6_RB_RPTR_BASE_IDX
#define regSDMA4_RLC6_RB_RPTR_HI
#define regSDMA4_RLC6_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC6_RB_WPTR
#define regSDMA4_RLC6_RB_WPTR_BASE_IDX
#define regSDMA4_RLC6_RB_WPTR_HI
#define regSDMA4_RLC6_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC6_RB_RPTR_ADDR_HI
#define regSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC6_RB_RPTR_ADDR_LO
#define regSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC6_IB_CNTL
#define regSDMA4_RLC6_IB_CNTL_BASE_IDX
#define regSDMA4_RLC6_IB_RPTR
#define regSDMA4_RLC6_IB_RPTR_BASE_IDX
#define regSDMA4_RLC6_IB_OFFSET
#define regSDMA4_RLC6_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC6_IB_BASE_LO
#define regSDMA4_RLC6_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC6_IB_BASE_HI
#define regSDMA4_RLC6_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC6_IB_SIZE
#define regSDMA4_RLC6_IB_SIZE_BASE_IDX
#define regSDMA4_RLC6_SKIP_CNTL
#define regSDMA4_RLC6_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC6_CONTEXT_STATUS
#define regSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC6_DOORBELL
#define regSDMA4_RLC6_DOORBELL_BASE_IDX
#define regSDMA4_RLC6_STATUS
#define regSDMA4_RLC6_STATUS_BASE_IDX
#define regSDMA4_RLC6_DOORBELL_LOG
#define regSDMA4_RLC6_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC6_WATERMARK
#define regSDMA4_RLC6_WATERMARK_BASE_IDX
#define regSDMA4_RLC6_DOORBELL_OFFSET
#define regSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC6_CSA_ADDR_LO
#define regSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC6_CSA_ADDR_HI
#define regSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC6_IB_SUB_REMAIN
#define regSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC6_PREEMPT
#define regSDMA4_RLC6_PREEMPT_BASE_IDX
#define regSDMA4_RLC6_DUMMY_REG
#define regSDMA4_RLC6_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC6_RB_AQL_CNTL
#define regSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC6_MINOR_PTR_UPDATE
#define regSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA0
#define regSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA1
#define regSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA2
#define regSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA3
#define regSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA4
#define regSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA5
#define regSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA6
#define regSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA7
#define regSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA8
#define regSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA9
#define regSDMA4_RLC6_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_DATA10
#define regSDMA4_RLC6_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC6_MIDCMD_CNTL
#define regSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX
#define regSDMA4_RLC7_RB_CNTL
#define regSDMA4_RLC7_RB_CNTL_BASE_IDX
#define regSDMA4_RLC7_RB_BASE
#define regSDMA4_RLC7_RB_BASE_BASE_IDX
#define regSDMA4_RLC7_RB_BASE_HI
#define regSDMA4_RLC7_RB_BASE_HI_BASE_IDX
#define regSDMA4_RLC7_RB_RPTR
#define regSDMA4_RLC7_RB_RPTR_BASE_IDX
#define regSDMA4_RLC7_RB_RPTR_HI
#define regSDMA4_RLC7_RB_RPTR_HI_BASE_IDX
#define regSDMA4_RLC7_RB_WPTR
#define regSDMA4_RLC7_RB_WPTR_BASE_IDX
#define regSDMA4_RLC7_RB_WPTR_HI
#define regSDMA4_RLC7_RB_WPTR_HI_BASE_IDX
#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL
#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX
#define regSDMA4_RLC7_RB_RPTR_ADDR_HI
#define regSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX
#define regSDMA4_RLC7_RB_RPTR_ADDR_LO
#define regSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX
#define regSDMA4_RLC7_IB_CNTL
#define regSDMA4_RLC7_IB_CNTL_BASE_IDX
#define regSDMA4_RLC7_IB_RPTR
#define regSDMA4_RLC7_IB_RPTR_BASE_IDX
#define regSDMA4_RLC7_IB_OFFSET
#define regSDMA4_RLC7_IB_OFFSET_BASE_IDX
#define regSDMA4_RLC7_IB_BASE_LO
#define regSDMA4_RLC7_IB_BASE_LO_BASE_IDX
#define regSDMA4_RLC7_IB_BASE_HI
#define regSDMA4_RLC7_IB_BASE_HI_BASE_IDX
#define regSDMA4_RLC7_IB_SIZE
#define regSDMA4_RLC7_IB_SIZE_BASE_IDX
#define regSDMA4_RLC7_SKIP_CNTL
#define regSDMA4_RLC7_SKIP_CNTL_BASE_IDX
#define regSDMA4_RLC7_CONTEXT_STATUS
#define regSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX
#define regSDMA4_RLC7_DOORBELL
#define regSDMA4_RLC7_DOORBELL_BASE_IDX
#define regSDMA4_RLC7_STATUS
#define regSDMA4_RLC7_STATUS_BASE_IDX
#define regSDMA4_RLC7_DOORBELL_LOG
#define regSDMA4_RLC7_DOORBELL_LOG_BASE_IDX
#define regSDMA4_RLC7_WATERMARK
#define regSDMA4_RLC7_WATERMARK_BASE_IDX
#define regSDMA4_RLC7_DOORBELL_OFFSET
#define regSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX
#define regSDMA4_RLC7_CSA_ADDR_LO
#define regSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX
#define regSDMA4_RLC7_CSA_ADDR_HI
#define regSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX
#define regSDMA4_RLC7_IB_SUB_REMAIN
#define regSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX
#define regSDMA4_RLC7_PREEMPT
#define regSDMA4_RLC7_PREEMPT_BASE_IDX
#define regSDMA4_RLC7_DUMMY_REG
#define regSDMA4_RLC7_DUMMY_REG_BASE_IDX
#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI
#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX
#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO
#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX
#define regSDMA4_RLC7_RB_AQL_CNTL
#define regSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX
#define regSDMA4_RLC7_MINOR_PTR_UPDATE
#define regSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA0
#define regSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA1
#define regSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA2
#define regSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA3
#define regSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA4
#define regSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA5
#define regSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA6
#define regSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA7
#define regSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA8
#define regSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA9
#define regSDMA4_RLC7_MIDCMD_DATA9_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_DATA10
#define regSDMA4_RLC7_MIDCMD_DATA10_BASE_IDX
#define regSDMA4_RLC7_MIDCMD_CNTL
#define regSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX

#endif