/* * Copyright 2011 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ /* * Authors: * Christian König <[email protected]> */ #include <linux/firmware.h> #include <linux/module.h> #include <drm/drm.h> #include <drm/drm_drv.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_uvd.h" #include "amdgpu_cs.h" #include "cikd.h" #include "uvd/uvd_4_2_d.h" #include "amdgpu_ras.h" /* 1 second timeout */ #define UVD_IDLE_TIMEOUT … /* Firmware versions for VI */ #define FW_1_65_10 … #define FW_1_87_11 … #define FW_1_87_12 … #define FW_1_37_15 … /* Polaris10/11 firmware version */ #define FW_1_66_16 … /* Firmware Names */ #ifdef CONFIG_DRM_AMDGPU_SI #define FIRMWARE_TAHITI … #define FIRMWARE_VERDE … #define FIRMWARE_PITCAIRN … #define FIRMWARE_OLAND … #endif #ifdef CONFIG_DRM_AMDGPU_CIK #define FIRMWARE_BONAIRE … #define FIRMWARE_KABINI … #define FIRMWARE_KAVERI … #define FIRMWARE_HAWAII … #define FIRMWARE_MULLINS … #endif #define FIRMWARE_TONGA … #define FIRMWARE_CARRIZO … #define FIRMWARE_FIJI … #define FIRMWARE_STONEY … #define FIRMWARE_POLARIS10 … #define FIRMWARE_POLARIS11 … #define FIRMWARE_POLARIS12 … #define FIRMWARE_VEGAM … #define FIRMWARE_VEGA10 … #define FIRMWARE_VEGA12 … #define FIRMWARE_VEGA20 … /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ #define UVD_GPCOM_VCPU_CMD … #define UVD_GPCOM_VCPU_DATA0 … #define UVD_GPCOM_VCPU_DATA1 … #define UVD_NO_OP … #define UVD_BASE_SI … /* * amdgpu_uvd_cs_ctx - Command submission parser context * * Used for emulating virtual memory support on UVD 4.2. */ struct amdgpu_uvd_cs_ctx { … }; #ifdef CONFIG_DRM_AMDGPU_SI MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); #endif #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); #endif MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo); static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev, uint32_t size, struct amdgpu_bo **bo_ptr) { … } int amdgpu_uvd_sw_init(struct amdgpu_device *adev) { … } int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) { … } /** * amdgpu_uvd_entity_init - init entity * * @adev: amdgpu_device pointer * @ring: amdgpu_ring pointer to check * * Initialize the entity used for handle management in the kernel driver. */ int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) { … } int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) { … } int amdgpu_uvd_suspend(struct amdgpu_device *adev) { … } int amdgpu_uvd_resume(struct amdgpu_device *adev) { … } void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) { … } static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) { … } static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) { … } /** * amdgpu_uvd_cs_pass1 - first parsing round * * @ctx: UVD parser context * * Make sure UVD message and feedback buffers are in VRAM and * nobody is violating an 256MB boundary. */ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) { … } /** * amdgpu_uvd_cs_msg_decode - handle UVD decode message * * @adev: amdgpu_device pointer * @msg: pointer to message structure * @buf_sizes: placeholder to put the different buffer lengths * * Peek into the decode message and calculate the necessary buffer sizes. */ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, unsigned int buf_sizes[]) { … } /** * amdgpu_uvd_cs_msg - handle UVD message * * @ctx: UVD parser context * @bo: buffer object containing the message * @offset: offset into the buffer object * * Peek into the UVD message and extract the session id. * Make sure that we don't open up to many sessions. */ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, struct amdgpu_bo *bo, unsigned int offset) { … } /** * amdgpu_uvd_cs_pass2 - second parsing round * * @ctx: UVD parser context * * Patch buffer addresses, make sure buffer sizes are correct. */ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) { … } /** * amdgpu_uvd_cs_reg - parse register writes * * @ctx: UVD parser context * @cb: callback function * * Parse the register writes, call cb on each complete command. */ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) { … } /** * amdgpu_uvd_cs_packets - parse UVD packets * * @ctx: UVD parser context * @cb: callback function * * Parse the command stream packets. */ static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) { … } /** * amdgpu_uvd_ring_parse_cs - UVD command submission parser * * @parser: Command submission parser context * @job: the job to parse * @ib: the IB to patch * * Parse the command stream, patch in addresses as necessary. */ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, struct amdgpu_job *job, struct amdgpu_ib *ib) { … } static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) { … } /* multiple fence commands without any stream commands in between can * crash the vcpu so just try to emmit a dummy create/destroy msg to * avoid this */ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, struct dma_fence **fence) { … } int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, bool direct, struct dma_fence **fence) { … } static void amdgpu_uvd_idle_work_handler(struct work_struct *work) { … } void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) { … } void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) { … } /** * amdgpu_uvd_ring_test_ib - test ib execution * * @ring: amdgpu_ring pointer * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT * * Test if we can successfully execute an IB */ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) { … } /** * amdgpu_uvd_used_handles - returns used UVD handles * * @adev: amdgpu_device pointer * * Returns the number of UVD handles in use */ uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) { … }
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