/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _vce_4_0_OFFSET_HEADER #define _vce_4_0_OFFSET_HEADER // addressBlock: vce0_vce_dec // base address: 0x22000 #define mmVCE_STATUS … #define mmVCE_STATUS_BASE_IDX … #define mmVCE_VCPU_CNTL … #define mmVCE_VCPU_CNTL_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET0 … #define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE0 … #define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET1 … #define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE1 … #define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET2 … #define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE2 … #define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET3 … #define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE3 … #define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET4 … #define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE4 … #define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET5 … #define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE5 … #define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET6 … #define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE6 … #define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET7 … #define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE7 … #define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX … #define mmVCE_VCPU_CACHE_OFFSET8 … #define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX … #define mmVCE_VCPU_CACHE_SIZE8 … #define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX … #define mmVCE_SOFT_RESET … #define mmVCE_SOFT_RESET_BASE_IDX … #define mmVCE_RB_BASE_LO2 … #define mmVCE_RB_BASE_LO2_BASE_IDX … #define mmVCE_RB_BASE_HI2 … #define mmVCE_RB_BASE_HI2_BASE_IDX … #define mmVCE_RB_SIZE2 … #define mmVCE_RB_SIZE2_BASE_IDX … #define mmVCE_RB_RPTR2 … #define mmVCE_RB_RPTR2_BASE_IDX … #define mmVCE_RB_WPTR2 … #define mmVCE_RB_WPTR2_BASE_IDX … #define mmVCE_RB_BASE_LO … #define mmVCE_RB_BASE_LO_BASE_IDX … #define mmVCE_RB_BASE_HI … #define mmVCE_RB_BASE_HI_BASE_IDX … #define mmVCE_RB_SIZE … #define mmVCE_RB_SIZE_BASE_IDX … #define mmVCE_RB_RPTR … #define mmVCE_RB_RPTR_BASE_IDX … #define mmVCE_RB_WPTR … #define mmVCE_RB_WPTR_BASE_IDX … #define mmVCE_RB_ARB_CTRL … #define mmVCE_RB_ARB_CTRL_BASE_IDX … #define mmVCE_CLOCK_GATING_A … #define mmVCE_CLOCK_GATING_A_BASE_IDX … #define mmVCE_CLOCK_GATING_B … #define mmVCE_CLOCK_GATING_B_BASE_IDX … #define mmVCE_RB_BASE_LO3 … #define mmVCE_RB_BASE_LO3_BASE_IDX … #define mmVCE_RB_BASE_HI3 … #define mmVCE_RB_BASE_HI3_BASE_IDX … #define mmVCE_RB_SIZE3 … #define mmVCE_RB_SIZE3_BASE_IDX … #define mmVCE_RB_RPTR3 … #define mmVCE_RB_RPTR3_BASE_IDX … #define mmVCE_RB_WPTR3 … #define mmVCE_RB_WPTR3_BASE_IDX … #define mmVCE_SYS_INT_EN … #define mmVCE_SYS_INT_EN_BASE_IDX … #define mmVCE_SYS_INT_ACK … #define mmVCE_SYS_INT_ACK_BASE_IDX … #define mmVCE_SYS_INT_STATUS … #define mmVCE_SYS_INT_STATUS_BASE_IDX … // addressBlock: vce0_ctl_dec // base address: 0x22780 #define mmVCE_UENC_CLOCK_GATING … #define mmVCE_UENC_CLOCK_GATING_BASE_IDX … #define mmVCE_UENC_REG_CLOCK_GATING … #define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX … #define mmVCE_UENC_CLOCK_GATING_2 … #define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX … // addressBlock: vce0_vce_sclk_dec // base address: 0x23700 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX … #define mmVCE_LMI_CTRL2 … #define mmVCE_LMI_CTRL2_BASE_IDX … #define mmVCE_LMI_SWAP_CNTL3 … #define mmVCE_LMI_SWAP_CNTL3_BASE_IDX … #define mmVCE_LMI_CTRL … #define mmVCE_LMI_CTRL_BASE_IDX … #define mmVCE_LMI_STATUS … #define mmVCE_LMI_STATUS_BASE_IDX … #define mmVCE_LMI_VM_CTRL … #define mmVCE_LMI_VM_CTRL_BASE_IDX … #define mmVCE_LMI_SWAP_CNTL … #define mmVCE_LMI_SWAP_CNTL_BASE_IDX … #define mmVCE_LMI_SWAP_CNTL1 … #define mmVCE_LMI_SWAP_CNTL1_BASE_IDX … #define mmVCE_LMI_SWAP_CNTL2 … #define mmVCE_LMI_SWAP_CNTL2_BASE_IDX … #define mmVCE_LMI_CACHE_CTRL … #define mmVCE_LMI_CACHE_CTRL_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 … #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX … // addressBlock: vce0_mmsch_dec // base address: 0x23b00 #define mmVCE_MMSCH_VF_VMID … #define mmVCE_MMSCH_VF_VMID_BASE_IDX … #define mmVCE_MMSCH_VF_CTX_ADDR_LO … #define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX … #define mmVCE_MMSCH_VF_CTX_ADDR_HI … #define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX … #define mmVCE_MMSCH_VF_CTX_SIZE … #define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX … #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO … #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX … #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI … #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX … #define mmVCE_MMSCH_VF_GPCOM_SIZE … #define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX … #define mmVCE_MMSCH_VF_MAILBOX_HOST … #define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX … #define mmVCE_MMSCH_VF_MAILBOX_RESP … #define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX … // addressBlock: vce0_vce_rb_pg_dec // base address: 0x23fa0 #define mmVCE_HW_VERSION … #define mmVCE_HW_VERSION_BASE_IDX … #endif
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