/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _vce_4_0_SH_MASK_HEADER #define _vce_4_0_SH_MASK_HEADER // addressBlock: vce0_vce_dec //VCE_STATUS #define VCE_STATUS__JOB_BUSY__SHIFT … #define VCE_STATUS__VCPU_REPORT__SHIFT … #define VCE_STATUS__UENC_BUSY__SHIFT … #define VCE_STATUS__VCE_CONFIGURATION__SHIFT … #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT … #define VCE_STATUS__JOB_BUSY_MASK … #define VCE_STATUS__VCPU_REPORT_MASK … #define VCE_STATUS__UENC_BUSY_MASK … #define VCE_STATUS__VCE_CONFIGURATION_MASK … #define VCE_STATUS__VCE_INSTANCE_ID_MASK … //VCE_VCPU_CNTL #define VCE_VCPU_CNTL__CLK_EN__SHIFT … #define VCE_VCPU_CNTL__ED_ENABLE__SHIFT … #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT … #define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT … #define VCE_VCPU_CNTL__CLK_EN_MASK … #define VCE_VCPU_CNTL__ED_ENABLE_MASK … #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK … #define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK … //VCE_VCPU_CACHE_OFFSET0 #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE0 #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET1 #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE1 #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET2 #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE2 #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET3 #define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE3 #define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE3__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET4 #define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE4 #define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE4__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET5 #define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE5 #define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE5__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET6 #define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE6 #define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE6__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET7 #define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE7 #define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE7__SIZE_MASK … //VCE_VCPU_CACHE_OFFSET8 #define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT … #define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK … //VCE_VCPU_CACHE_SIZE8 #define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT … #define VCE_VCPU_CACHE_SIZE8__SIZE_MASK … //VCE_SOFT_RESET #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT … #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK … #define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK … #define VCE_SOFT_RESET__FME_SOFT_RESET_MASK … #define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK … #define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK … #define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK … #define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK … #define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK … #define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK … #define VCE_SOFT_RESET__IME_SOFT_RESET_MASK … #define VCE_SOFT_RESET__IH_SOFT_RESET_MASK … #define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK … #define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK … #define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK … #define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK … #define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK … #define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK … #define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK … #define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK … #define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK … #define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK … //VCE_RB_BASE_LO2 #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT … #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK … //VCE_RB_BASE_HI2 #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT … #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK … //VCE_RB_SIZE2 #define VCE_RB_SIZE2__RB_SIZE__SHIFT … #define VCE_RB_SIZE2__RB_SIZE_MASK … //VCE_RB_RPTR2 #define VCE_RB_RPTR2__RB_RPTR__SHIFT … #define VCE_RB_RPTR2__RB_RPTR_MASK … //VCE_RB_WPTR2 #define VCE_RB_WPTR2__RB_WPTR__SHIFT … #define VCE_RB_WPTR2__RB_WPTR_MASK … //VCE_RB_BASE_LO #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT … #define VCE_RB_BASE_LO__RB_BASE_LO_MASK … //VCE_RB_BASE_HI #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT … #define VCE_RB_BASE_HI__RB_BASE_HI_MASK … //VCE_RB_SIZE #define VCE_RB_SIZE__RB_SIZE__SHIFT … #define VCE_RB_SIZE__RB_SIZE_MASK … //VCE_RB_RPTR #define VCE_RB_RPTR__RB_RPTR__SHIFT … #define VCE_RB_RPTR__RB_RPTR_MASK … //VCE_RB_WPTR #define VCE_RB_WPTR__RB_WPTR__SHIFT … #define VCE_RB_WPTR__RB_WPTR_MASK … //VCE_RB_ARB_CTRL #define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT … #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT … #define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK … #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK … //VCE_CLOCK_GATING_A #define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT … #define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT … #define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT … #define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK … #define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK … #define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK … //VCE_CLOCK_GATING_B #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT … #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT … #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK … #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK … #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK … //VCE_RB_BASE_LO3 #define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT … #define VCE_RB_BASE_LO3__RB_BASE_LO_MASK … //VCE_RB_BASE_HI3 #define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT … #define VCE_RB_BASE_HI3__RB_BASE_HI_MASK … //VCE_RB_SIZE3 #define VCE_RB_SIZE3__RB_SIZE__SHIFT … #define VCE_RB_SIZE3__RB_SIZE_MASK … //VCE_RB_RPTR3 #define VCE_RB_RPTR3__RB_RPTR__SHIFT … #define VCE_RB_RPTR3__RB_RPTR_MASK … //VCE_RB_WPTR3 #define VCE_RB_WPTR3__RB_WPTR__SHIFT … #define VCE_RB_WPTR3__RB_WPTR_MASK … //VCE_SYS_INT_EN #define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT … #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT … #define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK … #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK … //VCE_SYS_INT_ACK #define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT … #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT … #define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK … #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK … //VCE_SYS_INT_STATUS #define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT … #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT … #define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK … #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK … // addressBlock: vce0_ctl_dec //VCE_UENC_CLOCK_GATING #define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT … #define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT … #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK … #define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK … #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK … #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK … //VCE_UENC_REG_CLOCK_GATING #define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT … #define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK … #define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK … #define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK … //VCE_UENC_CLOCK_GATING_2 #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT … #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT … #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK … #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK … // addressBlock: vce0_vce_sclk_dec //VCE_LMI_VCPU_CACHE_40BIT_BAR #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK … //VCE_LMI_CTRL2 #define VCE_LMI_CTRL2__STALL_ARB__SHIFT … #define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT … #define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT … #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT … #define VCE_LMI_CTRL2__STALL_ARB_MASK … #define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK … #define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK … #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK … //VCE_LMI_SWAP_CNTL3 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT … #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT … #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK … #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK … #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK … //VCE_LMI_CTRL #define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT … #define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT … #define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT … #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT … #define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT … #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT … #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT … #define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK … #define VCE_LMI_CTRL__MASK_MC_URGENT_MASK … #define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK … #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK … #define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK … #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK … #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK … //VCE_LMI_SWAP_CNTL #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT … #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK … #define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK … //VCE_LMI_SWAP_CNTL1 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT … #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK … #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK … //VCE_LMI_SWAP_CNTL2 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT … #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT … #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT … #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK … #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK … #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK … //VCE_LMI_CACHE_CTRL #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT … #define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT … #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK … #define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR0 #define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR1 #define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR2 #define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR3 #define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR4 #define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR5 #define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR6 #define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK … //VCE_LMI_VCPU_CACHE_64BIT_BAR7 #define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR0 #define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR1 #define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR2 #define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR3 #define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR4 #define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR5 #define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR6 #define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK … //VCE_LMI_VCPU_CACHE_40BIT_BAR7 #define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT … #define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK … // addressBlock: vce0_mmsch_dec //VCE_MMSCH_VF_VMID #define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT … #define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT … #define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK … #define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK … //VCE_MMSCH_VF_CTX_ADDR_LO #define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT … #define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK … //VCE_MMSCH_VF_CTX_ADDR_HI #define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT … #define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK … //VCE_MMSCH_VF_CTX_SIZE #define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT … #define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK … //VCE_MMSCH_VF_GPCOM_ADDR_LO #define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT … #define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK … //VCE_MMSCH_VF_GPCOM_ADDR_HI #define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT … #define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK … //VCE_MMSCH_VF_GPCOM_SIZE #define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT … #define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK … //VCE_MMSCH_VF_MAILBOX_HOST #define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT … #define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK … //VCE_MMSCH_VF_MAILBOX_RESP #define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT … #define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK … // addressBlock: vce0_vce_rb_pg_dec //VCE_HW_VERSION #define VCE_HW_VERSION__VCE_VERSION__SHIFT … #define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT … #define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT … #define VCE_HW_VERSION__VCE_VERSION_MASK … #define VCE_HW_VERSION__VCE_CONFIGURATION_MASK … #define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK … #endif
Codebase Browser
linux