/* * Copyright 2014 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * Authors: Christian König <[email protected]> */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_vce.h" #include "vid.h" #include "vce/vce_3_0_d.h" #include "vce/vce_3_0_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" #include "gca/gfx_8_0_d.h" #include "smu/smu_7_1_2_d.h" #include "smu/smu_7_1_2_sh_mask.h" #include "gca/gfx_8_0_sh_mask.h" #include "ivsrcid/ivsrcid_vislands30.h" #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT … #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK … #define GRBM_GFX_INDEX__VCE_ALL_PIPE … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 … #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 … #define mmGRBM_GFX_INDEX_DEFAULT … #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK … #define VCE_V3_0_FW_SIZE … #define VCE_V3_0_STACK_SIZE … #define VCE_V3_0_DATA_SIZE … #define FW_52_8_3 … #define GET_VCE_INSTANCE(i) … static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); static int vce_v3_0_wait_for_idle(void *handle); static int vce_v3_0_set_clockgating_state(void *handle, enum amd_clockgating_state state); /** * vce_v3_0_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vce_v3_0_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vce_v3_0_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) { … } static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) { … } static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev, bool gated) { … } static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev) { … } /** * vce_v3_0_start - start VCE block * * @adev: amdgpu_device pointer * * Setup and start the VCE block */ static int vce_v3_0_start(struct amdgpu_device *adev) { … } static int vce_v3_0_stop(struct amdgpu_device *adev) { … } #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS … #define VCE_HARVEST_FUSE_MACRO__SHIFT … #define VCE_HARVEST_FUSE_MACRO__MASK … static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) { … } static int vce_v3_0_early_init(void *handle) { … } static int vce_v3_0_sw_init(void *handle) { … } static int vce_v3_0_sw_fini(void *handle) { … } static int vce_v3_0_hw_init(void *handle) { … } static int vce_v3_0_hw_fini(void *handle) { … } static int vce_v3_0_suspend(void *handle) { … } static int vce_v3_0_resume(void *handle) { … } static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) { … } static bool vce_v3_0_is_idle(void *handle) { … } static int vce_v3_0_wait_for_idle(void *handle) { … } #define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK … #define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK … #define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK … #define AMDGPU_VCE_STATUS_BUSY_MASK … static bool vce_v3_0_check_soft_reset(void *handle) { … } static int vce_v3_0_soft_reset(void *handle) { … } static int vce_v3_0_pre_soft_reset(void *handle) { … } static int vce_v3_0_post_soft_reset(void *handle) { … } static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int vce_v3_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int vce_v3_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void vce_v3_0_get_clockgating_state(void *handle, u64 *flags) { … } static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) { … } static const struct amd_ip_funcs vce_v3_0_ip_funcs = …; static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = …; static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = …; static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = …; static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) { adev->vce.irq.num_types = 1; adev->vce.irq.funcs = &vce_v3_0_irq_funcs; }; const struct amdgpu_ip_block_version vce_v3_0_ip_block = …; const struct amdgpu_ip_block_version vce_v3_1_ip_block = …; const struct amdgpu_ip_block_version vce_v3_4_ip_block = …;
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