/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _vcn_1_0_OFFSET_HEADER #define _vcn_1_0_OFFSET_HEADER // addressBlock: uvd_uvd_pg_dec // base address: 0x1fb00 #define mmUVD_PGFSM_CONFIG … #define mmUVD_PGFSM_CONFIG_BASE_IDX … #define mmUVD_PGFSM_STATUS … #define mmUVD_PGFSM_STATUS_BASE_IDX … #define mmUVD_POWER_STATUS … #define mmUVD_POWER_STATUS_BASE_IDX … #define mmCC_UVD_HARVESTING … #define mmCC_UVD_HARVESTING_BASE_IDX … #define mmUVD_DPG_LMA_CTL … #define mmUVD_DPG_LMA_CTL_BASE_IDX … #define mmUVD_DPG_LMA_DATA … #define mmUVD_DPG_LMA_DATA_BASE_IDX … #define mmUVD_DPG_LMA_MASK … #define mmUVD_DPG_LMA_MASK_BASE_IDX … #define mmUVD_DPG_PAUSE … #define mmUVD_DPG_PAUSE_BASE_IDX … #define mmUVD_SCRATCH1 … #define mmUVD_SCRATCH1_BASE_IDX … #define mmUVD_SCRATCH2 … #define mmUVD_SCRATCH2_BASE_IDX … #define mmUVD_SCRATCH3 … #define mmUVD_SCRATCH3_BASE_IDX … #define mmUVD_SCRATCH4 … #define mmUVD_SCRATCH4_BASE_IDX … #define mmUVD_SCRATCH5 … #define mmUVD_SCRATCH5_BASE_IDX … #define mmUVD_SCRATCH6 … #define mmUVD_SCRATCH6_BASE_IDX … #define mmUVD_SCRATCH7 … #define mmUVD_SCRATCH7_BASE_IDX … #define mmUVD_SCRATCH8 … #define mmUVD_SCRATCH8_BASE_IDX … #define mmUVD_SCRATCH9 … #define mmUVD_SCRATCH9_BASE_IDX … #define mmUVD_SCRATCH10 … #define mmUVD_SCRATCH10_BASE_IDX … #define mmUVD_SCRATCH11 … #define mmUVD_SCRATCH11_BASE_IDX … #define mmUVD_SCRATCH12 … #define mmUVD_SCRATCH12_BASE_IDX … #define mmUVD_SCRATCH13 … #define mmUVD_SCRATCH13_BASE_IDX … #define mmUVD_SCRATCH14 … #define mmUVD_SCRATCH14_BASE_IDX … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_DPG_VCPU_CACHE_OFFSET0 … #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX … // addressBlock: uvd_uvdgendec // base address: 0x1fc00 #define mmUVD_LCM_CGC_CNTRL … #define mmUVD_LCM_CGC_CNTRL_BASE_IDX … #define mmUVD_MIF_CURR_UV_ADDR_CONFIG … #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX … #define mmUVD_MIF_REF_UV_ADDR_CONFIG … #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX … #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG … #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX … #define mmUVD_MIF_CURR_ADDR_CONFIG … #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX … #define mmUVD_MIF_REF_ADDR_CONFIG … #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX … #define mmUVD_MIF_RECON1_ADDR_CONFIG … #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX … // addressBlock: uvd_uvdnpdec // base address: 0x20000 #define mmUVD_JPEG_CNTL … #define mmUVD_JPEG_CNTL_BASE_IDX … #define mmUVD_JPEG_RB_BASE … #define mmUVD_JPEG_RB_BASE_BASE_IDX … #define mmUVD_JPEG_RB_WPTR … #define mmUVD_JPEG_RB_WPTR_BASE_IDX … #define mmUVD_JPEG_RB_RPTR … #define mmUVD_JPEG_RB_RPTR_BASE_IDX … #define mmUVD_JPEG_RB_SIZE … #define mmUVD_JPEG_RB_SIZE_BASE_IDX … #define mmUVD_JPEG_ADDR_CONFIG … #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX … #define mmUVD_JPEG_PITCH … #define mmUVD_JPEG_PITCH_BASE_IDX … #define mmUVD_JPEG_GPCOM_CMD … #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX … #define mmUVD_JPEG_GPCOM_DATA0 … #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX … #define mmUVD_JPEG_GPCOM_DATA1 … #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX … #define mmUVD_JPEG_JRB_BASE_LO … #define mmUVD_JPEG_JRB_BASE_LO_BASE_IDX … #define mmUVD_JPEG_JRB_BASE_HI … #define mmUVD_JPEG_JRB_BASE_HI_BASE_IDX … #define mmUVD_JPEG_JRB_SIZE … #define mmUVD_JPEG_JRB_SIZE_BASE_IDX … #define mmUVD_JPEG_JRB_RPTR … #define mmUVD_JPEG_JRB_RPTR_BASE_IDX … #define mmUVD_JPEG_JRB_WPTR … #define mmUVD_JPEG_JRB_WPTR_BASE_IDX … #define mmUVD_JPEG_UV_ADDR_CONFIG … #define mmUVD_JPEG_UV_ADDR_CONFIG_BASE_IDX … #define mmUVD_SEMA_ADDR_LOW … #define mmUVD_SEMA_ADDR_LOW_BASE_IDX … #define mmUVD_SEMA_ADDR_HIGH … #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX … #define mmUVD_SEMA_CMD … #define mmUVD_SEMA_CMD_BASE_IDX … #define mmUVD_GPCOM_VCPU_CMD … #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX … #define mmUVD_GPCOM_VCPU_DATA0 … #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX … #define mmUVD_GPCOM_VCPU_DATA1 … #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX … #define mmUVD_ENGINE_CNTL … #define mmUVD_ENGINE_CNTL_BASE_IDX … #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG … #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX … #define mmUVD_UDEC_ADDR_CONFIG … #define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX … #define mmUVD_UDEC_DB_ADDR_CONFIG … #define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX … #define mmUVD_UDEC_DBW_ADDR_CONFIG … #define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX … #define mmUVD_SUVD_CGC_GATE … #define mmUVD_SUVD_CGC_GATE_BASE_IDX … #define mmUVD_SUVD_CGC_STATUS … #define mmUVD_SUVD_CGC_STATUS_BASE_IDX … #define mmUVD_SUVD_CGC_CTRL … #define mmUVD_SUVD_CGC_CTRL_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_NO_OP … #define mmUVD_NO_OP_BASE_IDX … #define mmUVD_JPEG_CNTL2 … #define mmUVD_JPEG_CNTL2_BASE_IDX … #define mmUVD_VERSION … #define mmUVD_VERSION_BASE_IDX … #define mmUVD_GP_SCRATCH8 … #define mmUVD_GP_SCRATCH8_BASE_IDX … #define mmUVD_GP_SCRATCH9 … #define mmUVD_GP_SCRATCH9_BASE_IDX … #define mmUVD_GP_SCRATCH10 … #define mmUVD_GP_SCRATCH10_BASE_IDX … #define mmUVD_GP_SCRATCH11 … #define mmUVD_GP_SCRATCH11_BASE_IDX … #define mmUVD_GP_SCRATCH12 … #define mmUVD_GP_SCRATCH12_BASE_IDX … #define mmUVD_GP_SCRATCH13 … #define mmUVD_GP_SCRATCH13_BASE_IDX … #define mmUVD_GP_SCRATCH14 … #define mmUVD_GP_SCRATCH14_BASE_IDX … #define mmUVD_GP_SCRATCH15 … #define mmUVD_GP_SCRATCH15_BASE_IDX … #define mmUVD_GP_SCRATCH16 … #define mmUVD_GP_SCRATCH16_BASE_IDX … #define mmUVD_GP_SCRATCH17 … #define mmUVD_GP_SCRATCH17_BASE_IDX … #define mmUVD_GP_SCRATCH18 … #define mmUVD_GP_SCRATCH18_BASE_IDX … #define mmUVD_GP_SCRATCH19 … #define mmUVD_GP_SCRATCH19_BASE_IDX … #define mmUVD_GP_SCRATCH20 … #define mmUVD_GP_SCRATCH20_BASE_IDX … #define mmUVD_GP_SCRATCH21 … #define mmUVD_GP_SCRATCH21_BASE_IDX … #define mmUVD_GP_SCRATCH22 … #define mmUVD_GP_SCRATCH22_BASE_IDX … #define mmUVD_GP_SCRATCH23 … #define mmUVD_GP_SCRATCH23_BASE_IDX … #define mmUVD_RB_BASE_LO2 … #define mmUVD_RB_BASE_LO2_BASE_IDX … #define mmUVD_RB_BASE_HI2 … #define mmUVD_RB_BASE_HI2_BASE_IDX … #define mmUVD_RB_SIZE2 … #define mmUVD_RB_SIZE2_BASE_IDX … #define mmUVD_RB_RPTR2 … #define mmUVD_RB_RPTR2_BASE_IDX … #define mmUVD_RB_WPTR2 … #define mmUVD_RB_WPTR2_BASE_IDX … #define mmUVD_RB_BASE_LO … #define mmUVD_RB_BASE_LO_BASE_IDX … #define mmUVD_RB_BASE_HI … #define mmUVD_RB_BASE_HI_BASE_IDX … #define mmUVD_RB_SIZE … #define mmUVD_RB_SIZE_BASE_IDX … #define mmUVD_RB_RPTR … #define mmUVD_RB_RPTR_BASE_IDX … #define mmUVD_RB_WPTR … #define mmUVD_RB_WPTR_BASE_IDX … #define mmUVD_RB_WPTR4 … #define mmUVD_RB_WPTR4_BASE_IDX … #define mmUVD_JRBC_RB_RPTR … #define mmUVD_JRBC_RB_RPTR_BASE_IDX … #define mmUVD_LMI_JPEG_VMID … #define mmUVD_LMI_JPEG_VMID_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH … #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX … // addressBlock: uvd_uvddec // base address: 0x20c00 #define mmUVD_SEMA_CNTL … #define mmUVD_SEMA_CNTL_BASE_IDX … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_JRBC_IB_VMID … #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX … #define mmUVD_LMI_JRBC_RB_VMID … #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX … #define mmUVD_JRBC_RB_WPTR … #define mmUVD_JRBC_RB_WPTR_BASE_IDX … #define mmUVD_JRBC_RB_CNTL … #define mmUVD_JRBC_RB_CNTL_BASE_IDX … #define mmUVD_JRBC_IB_SIZE … #define mmUVD_JRBC_IB_SIZE_BASE_IDX … #define mmUVD_JRBC_LMI_SWAP_CNTL … #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX … #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW … #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX … #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH … #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX … #define mmUVD_JRBC_RB_REF_DATA … #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX … #define mmUVD_JRBC_RB_COND_RD_TIMER … #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define mmUVD_JRBC_EXTERNAL_REG_BASE … #define mmUVD_JRBC_EXTERNAL_REG_BASE_BASE_IDX … #define mmUVD_JRBC_SOFT_RESET … #define mmUVD_JRBC_SOFT_RESET_BASE_IDX … #define mmUVD_JRBC_STATUS … #define mmUVD_JRBC_STATUS_BASE_IDX … #define mmUVD_RB_RPTR3 … #define mmUVD_RB_RPTR3_BASE_IDX … #define mmUVD_RB_WPTR3 … #define mmUVD_RB_WPTR3_BASE_IDX … #define mmUVD_RB_BASE_LO3 … #define mmUVD_RB_BASE_LO3_BASE_IDX … #define mmUVD_RB_BASE_HI3 … #define mmUVD_RB_BASE_HI3_BASE_IDX … #define mmUVD_RB_SIZE3 … #define mmUVD_RB_SIZE3_BASE_IDX … #define mmJPEG_CGC_GATE … #define mmJPEG_CGC_GATE_BASE_IDX … #define mmUVD_CTX_INDEX … #define mmUVD_CTX_INDEX_BASE_IDX … #define mmUVD_CTX_DATA … #define mmUVD_CTX_DATA_BASE_IDX … #define mmUVD_CGC_GATE … #define mmUVD_CGC_GATE_BASE_IDX … #define mmUVD_CGC_STATUS … #define mmUVD_CGC_STATUS_BASE_IDX … #define mmUVD_CGC_CTRL … #define mmUVD_CGC_CTRL_BASE_IDX … #define mmUVD_GP_SCRATCH0 … #define mmUVD_GP_SCRATCH0_BASE_IDX … #define mmUVD_GP_SCRATCH1 … #define mmUVD_GP_SCRATCH1_BASE_IDX … #define mmUVD_GP_SCRATCH2 … #define mmUVD_GP_SCRATCH2_BASE_IDX … #define mmUVD_GP_SCRATCH3 … #define mmUVD_GP_SCRATCH3_BASE_IDX … #define mmUVD_GP_SCRATCH4 … #define mmUVD_GP_SCRATCH4_BASE_IDX … #define mmUVD_GP_SCRATCH5 … #define mmUVD_GP_SCRATCH5_BASE_IDX … #define mmUVD_GP_SCRATCH6 … #define mmUVD_GP_SCRATCH6_BASE_IDX … #define mmUVD_GP_SCRATCH7 … #define mmUVD_GP_SCRATCH7_BASE_IDX … #define mmUVD_LMI_VCPU_CACHE_VMID … #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX … #define mmUVD_LMI_CTRL2 … #define mmUVD_LMI_CTRL2_BASE_IDX … #define mmUVD_MASTINT_EN … #define mmUVD_MASTINT_EN_BASE_IDX … #define mmUVD_SYS_INT_EN … #define mmUVD_SYS_INT_EN_BASE_IDX … #define mmJPEG_CGC_CTRL … #define mmJPEG_CGC_CTRL_BASE_IDX … #define mmUVD_LMI_CTRL … #define mmUVD_LMI_CTRL_BASE_IDX … #define mmUVD_LMI_STATUS … #define mmUVD_LMI_STATUS_BASE_IDX … #define mmUVD_LMI_VM_CTRL … #define mmUVD_LMI_VM_CTRL_BASE_IDX … #define mmUVD_LMI_SWAP_CNTL … #define mmUVD_LMI_SWAP_CNTL_BASE_IDX … #define mmUVD_MPC_CNTL … #define mmUVD_MPC_CNTL_BASE_IDX … #define mmUVD_MPC_SET_MUXA0 … #define mmUVD_MPC_SET_MUXA0_BASE_IDX … #define mmUVD_MPC_SET_MUXA1 … #define mmUVD_MPC_SET_MUXA1_BASE_IDX … #define mmUVD_MPC_SET_MUXB0 … #define mmUVD_MPC_SET_MUXB0_BASE_IDX … #define mmUVD_MPC_SET_MUXB1 … #define mmUVD_MPC_SET_MUXB1_BASE_IDX … #define mmUVD_MPC_SET_MUX … #define mmUVD_MPC_SET_MUX_BASE_IDX … #define mmUVD_MPC_SET_ALU … #define mmUVD_MPC_SET_ALU_BASE_IDX … #define mmUVD_GPCOM_SYS_CMD … #define mmUVD_GPCOM_SYS_CMD_BASE_IDX … #define mmUVD_GPCOM_SYS_DATA0 … #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX … #define mmUVD_GPCOM_SYS_DATA1 … #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET0 … #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE0 … #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET1 … #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE1 … #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … #define mmUVD_VCPU_CACHE_OFFSET2 … #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX … #define mmUVD_VCPU_CACHE_SIZE2 … #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX … #define mmUVD_VCPU_CNTL … #define mmUVD_VCPU_CNTL_BASE_IDX … #define mmUVD_SOFT_RESET … #define mmUVD_SOFT_RESET_BASE_IDX … #define mmUVD_LMI_RBC_IB_VMID … #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX … #define mmUVD_RBC_IB_SIZE … #define mmUVD_RBC_IB_SIZE_BASE_IDX … #define mmUVD_RBC_RB_RPTR … #define mmUVD_RBC_RB_RPTR_BASE_IDX … #define mmUVD_RBC_RB_WPTR … #define mmUVD_RBC_RB_WPTR_BASE_IDX … #define mmUVD_RBC_RB_WPTR_CNTL … #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX … #define mmUVD_RBC_RB_CNTL … #define mmUVD_RBC_RB_CNTL_BASE_IDX … #define mmUVD_RBC_RB_RPTR_ADDR … #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX … #define mmUVD_STATUS … #define mmUVD_STATUS_BASE_IDX … #define mmUVD_SEMA_TIMEOUT_STATUS … #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX … #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL … #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define mmUVD_CONTEXT_ID … #define mmUVD_CONTEXT_ID_BASE_IDX … #define mmUVD_CONTEXT_ID2 … #define mmUVD_CONTEXT_ID2_BASE_IDX … #define mmUVD_RBC_WPTR_POLL_CNTL … #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX … #define mmUVD_RBC_WPTR_POLL_ADDR … #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX … #define mmUVD_RB_BASE_LO4 … #define mmUVD_RB_BASE_LO4_BASE_IDX … #define mmUVD_RB_BASE_HI4 … #define mmUVD_RB_BASE_HI4_BASE_IDX … #define mmUVD_RB_SIZE4 … #define mmUVD_RB_SIZE4_BASE_IDX … #define mmUVD_RB_RPTR4 … #define mmUVD_RB_RPTR4_BASE_IDX … #endif
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