/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __MMSCH_V2_0_H__ #define __MMSCH_V2_0_H__ // addressBlock: uvd0_mmsch_dec // base address: 0x1e000 #define mmMMSCH_UCODE_ADDR … #define mmMMSCH_UCODE_ADDR_BASE_IDX … #define mmMMSCH_UCODE_DATA … #define mmMMSCH_UCODE_DATA_BASE_IDX … #define mmMMSCH_SRAM_ADDR … #define mmMMSCH_SRAM_ADDR_BASE_IDX … #define mmMMSCH_SRAM_DATA … #define mmMMSCH_SRAM_DATA_BASE_IDX … #define mmMMSCH_VF_SRAM_OFFSET … #define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX … #define mmMMSCH_DB_SRAM_OFFSET … #define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX … #define mmMMSCH_CTX_SRAM_OFFSET … #define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX … #define mmMMSCH_CTL … #define mmMMSCH_CTL_BASE_IDX … #define mmMMSCH_INTR … #define mmMMSCH_INTR_BASE_IDX … #define mmMMSCH_INTR_ACK … #define mmMMSCH_INTR_ACK_BASE_IDX … #define mmMMSCH_INTR_STATUS … #define mmMMSCH_INTR_STATUS_BASE_IDX … #define mmMMSCH_VF_VMID … #define mmMMSCH_VF_VMID_BASE_IDX … #define mmMMSCH_VF_CTX_ADDR_LO … #define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX … #define mmMMSCH_VF_CTX_ADDR_HI … #define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX … #define mmMMSCH_VF_CTX_SIZE … #define mmMMSCH_VF_CTX_SIZE_BASE_IDX … #define mmMMSCH_VF_GPCOM_ADDR_LO … #define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX … #define mmMMSCH_VF_GPCOM_ADDR_HI … #define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX … #define mmMMSCH_VF_GPCOM_SIZE … #define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX … #define mmMMSCH_VF_MAILBOX_HOST … #define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX … #define mmMMSCH_VF_MAILBOX_RESP … #define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX … #define mmMMSCH_VF_MAILBOX_0 … #define mmMMSCH_VF_MAILBOX_0_BASE_IDX … #define mmMMSCH_VF_MAILBOX_0_RESP … #define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX … #define mmMMSCH_VF_MAILBOX_1 … #define mmMMSCH_VF_MAILBOX_1_BASE_IDX … #define mmMMSCH_VF_MAILBOX_1_RESP … #define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX … #define mmMMSCH_CNTL … #define mmMMSCH_CNTL_BASE_IDX … #define mmMMSCH_NONCACHE_OFFSET0 … #define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX … #define mmMMSCH_NONCACHE_SIZE0 … #define mmMMSCH_NONCACHE_SIZE0_BASE_IDX … #define mmMMSCH_NONCACHE_OFFSET1 … #define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX … #define mmMMSCH_NONCACHE_SIZE1 … #define mmMMSCH_NONCACHE_SIZE1_BASE_IDX … #define mmMMSCH_PDEBUG_STATUS … #define mmMMSCH_PDEBUG_STATUS_BASE_IDX … #define mmMMSCH_PDEBUG_DATA_32UPPERBITS … #define mmMMSCH_PDEBUG_DATA_32UPPERBITS_BASE_IDX … #define mmMMSCH_PDEBUG_DATA_32LOWERBITS … #define mmMMSCH_PDEBUG_DATA_32LOWERBITS_BASE_IDX … #define mmMMSCH_PDEBUG_EPC … #define mmMMSCH_PDEBUG_EPC_BASE_IDX … #define mmMMSCH_PDEBUG_EXCCAUSE … #define mmMMSCH_PDEBUG_EXCCAUSE_BASE_IDX … #define mmMMSCH_PROC_STATE1 … #define mmMMSCH_PROC_STATE1_BASE_IDX … #define mmMMSCH_LAST_MC_ADDR … #define mmMMSCH_LAST_MC_ADDR_BASE_IDX … #define mmMMSCH_LAST_MEM_ACCESS_HI … #define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX … #define mmMMSCH_LAST_MEM_ACCESS_LO … #define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX … #define mmMMSCH_IOV_ACTIVE_FCN_ID … #define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX … #define mmMMSCH_SCRATCH_0 … #define mmMMSCH_SCRATCH_0_BASE_IDX … #define mmMMSCH_SCRATCH_1 … #define mmMMSCH_SCRATCH_1_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_0 … #define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_CONTROL_0 … #define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_0 … #define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0 … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX … #define mmMMSCH_GPUIOV_DW6_0 … #define mmMMSCH_GPUIOV_DW6_0_BASE_IDX … #define mmMMSCH_GPUIOV_DW7_0 … #define mmMMSCH_GPUIOV_DW7_0_BASE_IDX … #define mmMMSCH_GPUIOV_DW8_0 … #define mmMMSCH_GPUIOV_DW8_0_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_1 … #define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_CONTROL_1 … #define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_1 … #define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1 … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1 … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX … #define mmMMSCH_GPUIOV_DW6_1 … #define mmMMSCH_GPUIOV_DW6_1_BASE_IDX … #define mmMMSCH_GPUIOV_DW7_1 … #define mmMMSCH_GPUIOV_DW7_1_BASE_IDX … #define mmMMSCH_GPUIOV_DW8_1 … #define mmMMSCH_GPUIOV_DW8_1_BASE_IDX … #define mmMMSCH_GPUIOV_CNTXT … #define mmMMSCH_GPUIOV_CNTXT_BASE_IDX … #define mmMMSCH_SCRATCH_2 … #define mmMMSCH_SCRATCH_2_BASE_IDX … #define mmMMSCH_SCRATCH_3 … #define mmMMSCH_SCRATCH_3_BASE_IDX … #define mmMMSCH_SCRATCH_4 … #define mmMMSCH_SCRATCH_4_BASE_IDX … #define mmMMSCH_SCRATCH_5 … #define mmMMSCH_SCRATCH_5_BASE_IDX … #define mmMMSCH_SCRATCH_6 … #define mmMMSCH_SCRATCH_6_BASE_IDX … #define mmMMSCH_SCRATCH_7 … #define mmMMSCH_SCRATCH_7_BASE_IDX … #define mmMMSCH_VFID_FIFO_HEAD_0 … #define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX … #define mmMMSCH_VFID_FIFO_TAIL_0 … #define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX … #define mmMMSCH_VFID_FIFO_HEAD_1 … #define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX … #define mmMMSCH_VFID_FIFO_TAIL_1 … #define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX … #define mmMMSCH_NACK_STATUS … #define mmMMSCH_NACK_STATUS_BASE_IDX … #define mmMMSCH_VF_MAILBOX0_DATA … #define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX … #define mmMMSCH_VF_MAILBOX1_DATA … #define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0 … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0 … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1 … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1 … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX … #define mmMMSCH_GPUIOV_CNTXT_IP … #define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_2 … #define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_CONTROL_2 … #define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_2 … #define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2 … #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2 … #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX … #define mmMMSCH_GPUIOV_DW6_2 … #define mmMMSCH_GPUIOV_DW6_2_BASE_IDX … #define mmMMSCH_GPUIOV_DW7_2 … #define mmMMSCH_GPUIOV_DW7_2_BASE_IDX … #define mmMMSCH_GPUIOV_DW8_2 … #define mmMMSCH_GPUIOV_DW8_2_BASE_IDX … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2 … #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2 … #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 … #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX … #define mmMMSCH_VFID_FIFO_HEAD_2 … #define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX … #define mmMMSCH_VFID_FIFO_TAIL_2 … #define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX … #define mmMMSCH_VM_BUSY_STATUS_0 … #define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX … #define mmMMSCH_VM_BUSY_STATUS_1 … #define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX … #define mmMMSCH_VM_BUSY_STATUS_2 … #define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX … #define MMSCH_VERSION_MAJOR … #define MMSCH_VERSION_MINOR … #define MMSCH_VERSION … enum mmsch_v2_0_command_type { … }; struct mmsch_v2_0_init_header { … }; struct mmsch_v2_0_cmd_direct_reg_header { … }; struct mmsch_v2_0_cmd_indirect_reg_header { … }; struct mmsch_v2_0_cmd_direct_write { … }; struct mmsch_v2_0_cmd_direct_read_modify_write { … }; struct mmsch_v2_0_cmd_direct_polling { … }; struct mmsch_v2_0_cmd_end { … }; struct mmsch_v2_0_cmd_indirect_write { … }; static inline void mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t value) { … } static inline void mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t data) { … } static inline void mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t wait) { … } #define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) … #define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) … #define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) … #endif
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