linux/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _vcn_3_0_0_OFFSET_HEADER
#define _vcn_3_0_0_OFFSET_HEADER

// addressBlock: uvd0_mmsch_dec
// base address: 0x1e000
#define mmMMSCH_UCODE_ADDR
#define mmMMSCH_UCODE_ADDR_BASE_IDX
#define mmMMSCH_UCODE_DATA
#define mmMMSCH_UCODE_DATA_BASE_IDX
#define mmMMSCH_SRAM_ADDR
#define mmMMSCH_SRAM_ADDR_BASE_IDX
#define mmMMSCH_SRAM_DATA
#define mmMMSCH_SRAM_DATA_BASE_IDX
#define mmMMSCH_VF_SRAM_OFFSET
#define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX
#define mmMMSCH_DB_SRAM_OFFSET
#define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX
#define mmMMSCH_CTX_SRAM_OFFSET
#define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX
#define mmMMSCH_CTL
#define mmMMSCH_CTL_BASE_IDX
#define mmMMSCH_INTR
#define mmMMSCH_INTR_BASE_IDX
#define mmMMSCH_INTR_ACK
#define mmMMSCH_INTR_ACK_BASE_IDX
#define mmMMSCH_INTR_STATUS
#define mmMMSCH_INTR_STATUS_BASE_IDX
#define mmMMSCH_VF_VMID
#define mmMMSCH_VF_VMID_BASE_IDX
#define mmMMSCH_VF_CTX_ADDR_LO
#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX
#define mmMMSCH_VF_CTX_ADDR_HI
#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX
#define mmMMSCH_VF_CTX_SIZE
#define mmMMSCH_VF_CTX_SIZE_BASE_IDX
#define mmMMSCH_VF_GPCOM_ADDR_LO
#define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX
#define mmMMSCH_VF_GPCOM_ADDR_HI
#define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX
#define mmMMSCH_VF_GPCOM_SIZE
#define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX
#define mmMMSCH_VF_MAILBOX_HOST
#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX
#define mmMMSCH_VF_MAILBOX_RESP
#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX
#define mmMMSCH_VF_MAILBOX_0
#define mmMMSCH_VF_MAILBOX_0_BASE_IDX
#define mmMMSCH_VF_MAILBOX_0_RESP
#define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX
#define mmMMSCH_VF_MAILBOX_1
#define mmMMSCH_VF_MAILBOX_1_BASE_IDX
#define mmMMSCH_VF_MAILBOX_1_RESP
#define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX
#define mmMMSCH_CNTL
#define mmMMSCH_CNTL_BASE_IDX
#define mmMMSCH_NONCACHE_OFFSET0
#define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX
#define mmMMSCH_NONCACHE_SIZE0
#define mmMMSCH_NONCACHE_SIZE0_BASE_IDX
#define mmMMSCH_NONCACHE_OFFSET1
#define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX
#define mmMMSCH_NONCACHE_SIZE1
#define mmMMSCH_NONCACHE_SIZE1_BASE_IDX
#define mmMMSCH_PROC_STATE1
#define mmMMSCH_PROC_STATE1_BASE_IDX
#define mmMMSCH_LAST_MC_ADDR
#define mmMMSCH_LAST_MC_ADDR_BASE_IDX
#define mmMMSCH_LAST_MEM_ACCESS_HI
#define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX
#define mmMMSCH_LAST_MEM_ACCESS_LO
#define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX
#define mmMMSCH_IOV_ACTIVE_FCN_ID
#define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX
#define mmMMSCH_SCRATCH_0
#define mmMMSCH_SCRATCH_0_BASE_IDX
#define mmMMSCH_SCRATCH_1
#define mmMMSCH_SCRATCH_1_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_0
#define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_CONTROL_0
#define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_0
#define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX
#define mmMMSCH_GPUIOV_DW6_0
#define mmMMSCH_GPUIOV_DW6_0_BASE_IDX
#define mmMMSCH_GPUIOV_DW7_0
#define mmMMSCH_GPUIOV_DW7_0_BASE_IDX
#define mmMMSCH_GPUIOV_DW8_0
#define mmMMSCH_GPUIOV_DW8_0_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_1
#define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_CONTROL_1
#define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_1
#define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX
#define mmMMSCH_GPUIOV_DW6_1
#define mmMMSCH_GPUIOV_DW6_1_BASE_IDX
#define mmMMSCH_GPUIOV_DW7_1
#define mmMMSCH_GPUIOV_DW7_1_BASE_IDX
#define mmMMSCH_GPUIOV_DW8_1
#define mmMMSCH_GPUIOV_DW8_1_BASE_IDX
#define mmMMSCH_GPUIOV_CNTXT
#define mmMMSCH_GPUIOV_CNTXT_BASE_IDX
#define mmMMSCH_SCRATCH_2
#define mmMMSCH_SCRATCH_2_BASE_IDX
#define mmMMSCH_SCRATCH_3
#define mmMMSCH_SCRATCH_3_BASE_IDX
#define mmMMSCH_SCRATCH_4
#define mmMMSCH_SCRATCH_4_BASE_IDX
#define mmMMSCH_SCRATCH_5
#define mmMMSCH_SCRATCH_5_BASE_IDX
#define mmMMSCH_SCRATCH_6
#define mmMMSCH_SCRATCH_6_BASE_IDX
#define mmMMSCH_SCRATCH_7
#define mmMMSCH_SCRATCH_7_BASE_IDX
#define mmMMSCH_VFID_FIFO_HEAD_0
#define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX
#define mmMMSCH_VFID_FIFO_TAIL_0
#define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX
#define mmMMSCH_VFID_FIFO_HEAD_1
#define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX
#define mmMMSCH_VFID_FIFO_TAIL_1
#define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX
#define mmMMSCH_NACK_STATUS
#define mmMMSCH_NACK_STATUS_BASE_IDX
#define mmMMSCH_VF_MAILBOX0_DATA
#define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX
#define mmMMSCH_VF_MAILBOX1_DATA
#define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX
#define mmMMSCH_GPUIOV_CNTXT_IP
#define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_2
#define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_CONTROL_2
#define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_2
#define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX
#define mmMMSCH_GPUIOV_DW6_2
#define mmMMSCH_GPUIOV_DW6_2_BASE_IDX
#define mmMMSCH_GPUIOV_DW7_2
#define mmMMSCH_GPUIOV_DW7_2_BASE_IDX
#define mmMMSCH_GPUIOV_DW8_2
#define mmMMSCH_GPUIOV_DW8_2_BASE_IDX
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2
#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2
#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX
#define mmMMSCH_VFID_FIFO_HEAD_2
#define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX
#define mmMMSCH_VFID_FIFO_TAIL_2
#define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX
#define mmMMSCH_VM_BUSY_STATUS_0
#define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX
#define mmMMSCH_VM_BUSY_STATUS_1
#define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX
#define mmMMSCH_VM_BUSY_STATUS_2
#define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX


// addressBlock: uvd0_jpegnpdec
// base address: 0x1e200
#define mmUVD_JPEG_CNTL
#define mmUVD_JPEG_CNTL_BASE_IDX
#define mmUVD_JPEG_RB_BASE
#define mmUVD_JPEG_RB_BASE_BASE_IDX
#define mmUVD_JPEG_RB_WPTR
#define mmUVD_JPEG_RB_WPTR_BASE_IDX
#define mmUVD_JPEG_RB_RPTR
#define mmUVD_JPEG_RB_RPTR_BASE_IDX
#define mmUVD_JPEG_RB_SIZE
#define mmUVD_JPEG_RB_SIZE_BASE_IDX
#define mmUVD_JPEG_DEC_CNT
#define mmUVD_JPEG_DEC_CNT_BASE_IDX
#define mmUVD_JPEG_SPS_INFO
#define mmUVD_JPEG_SPS_INFO_BASE_IDX
#define mmUVD_JPEG_SPS1_INFO
#define mmUVD_JPEG_SPS1_INFO_BASE_IDX
#define mmUVD_JPEG_RE_TIMER
#define mmUVD_JPEG_RE_TIMER_BASE_IDX
#define mmUVD_JPEG_DEC_SCRATCH0
#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX
#define mmUVD_JPEG_INT_EN
#define mmUVD_JPEG_INT_EN_BASE_IDX
#define mmUVD_JPEG_INT_STAT
#define mmUVD_JPEG_INT_STAT_BASE_IDX
#define mmUVD_JPEG_TIER_CNTL0
#define mmUVD_JPEG_TIER_CNTL0_BASE_IDX
#define mmUVD_JPEG_TIER_CNTL1
#define mmUVD_JPEG_TIER_CNTL1_BASE_IDX
#define mmUVD_JPEG_TIER_CNTL2
#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX
#define mmUVD_JPEG_TIER_STATUS
#define mmUVD_JPEG_TIER_STATUS_BASE_IDX
#define mmUVD_JPEG_OUTBUF_CNTL
#define mmUVD_JPEG_OUTBUF_CNTL_BASE_IDX
#define mmUVD_JPEG_OUTBUF_WPTR
#define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX
#define mmUVD_JPEG_OUTBUF_RPTR
#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX
#define mmUVD_JPEG_PITCH
#define mmUVD_JPEG_PITCH_BASE_IDX
#define mmUVD_JPEG_UV_PITCH
#define mmUVD_JPEG_UV_PITCH_BASE_IDX
#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE
#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX
#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE
#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX
#define mmJPEG_DEC_GFX10_ADDR_CONFIG
#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX
#define mmJPEG_DEC_ADDR_MODE
#define mmJPEG_DEC_ADDR_MODE_BASE_IDX
#define mmUVD_JPEG_OUTPUT_XY
#define mmUVD_JPEG_OUTPUT_XY_BASE_IDX
#define mmUVD_JPEG_GPCOM_CMD
#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX
#define mmUVD_JPEG_GPCOM_DATA0
#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX
#define mmUVD_JPEG_GPCOM_DATA1
#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX
#define mmUVD_JPEG_INDEX
#define mmUVD_JPEG_INDEX_BASE_IDX
#define mmUVD_JPEG_DATA
#define mmUVD_JPEG_DATA_BASE_IDX
#define mmUVD_JPEG_SCRATCH1
#define mmUVD_JPEG_SCRATCH1_BASE_IDX
#define mmUVD_JPEG_DEC_SOFT_RST
#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX


// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
// base address: 0x1e380
#define mmUVD_JPEG_ENC_SPS_INFO
#define mmUVD_JPEG_ENC_SPS_INFO_BASE_IDX
#define mmUVD_JPEG_ENC_SPS_INFO1
#define mmUVD_JPEG_ENC_SPS_INFO1_BASE_IDX
#define mmUVD_JPEG_ENC_TBL_SIZE
#define mmUVD_JPEG_ENC_TBL_SIZE_BASE_IDX
#define mmUVD_JPEG_ENC_TBL_CNTL
#define mmUVD_JPEG_ENC_TBL_CNTL_BASE_IDX
#define mmUVD_JPEG_ENC_MC_REQ_CNTL
#define mmUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX
#define mmUVD_JPEG_ENC_STATUS
#define mmUVD_JPEG_ENC_STATUS_BASE_IDX
#define mmUVD_JPEG_ENC_PITCH
#define mmUVD_JPEG_ENC_PITCH_BASE_IDX
#define mmUVD_JPEG_ENC_LUMA_BASE
#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX
#define mmUVD_JPEG_ENC_CHROMAU_BASE
#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX
#define mmUVD_JPEG_ENC_CHROMAV_BASE
#define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX
#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE
#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX
#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE
#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX
#define mmJPEG_ENC_GFX10_ADDR_CONFIG
#define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX
#define mmJPEG_ENC_ADDR_MODE
#define mmJPEG_ENC_ADDR_MODE_BASE_IDX
#define mmUVD_JPEG_ENC_GPCOM_CMD
#define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX
#define mmUVD_JPEG_ENC_GPCOM_DATA0
#define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX
#define mmUVD_JPEG_ENC_GPCOM_DATA1
#define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX
#define mmUVD_JPEG_TBL_DAT0
#define mmUVD_JPEG_TBL_DAT0_BASE_IDX
#define mmUVD_JPEG_TBL_DAT1
#define mmUVD_JPEG_TBL_DAT1_BASE_IDX
#define mmUVD_JPEG_TBL_IDX
#define mmUVD_JPEG_TBL_IDX_BASE_IDX
#define mmUVD_JPEG_ENC_CGC_CNTL
#define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX
#define mmUVD_JPEG_ENC_SCRATCH0
#define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX
#define mmUVD_JPEG_ENC_SOFT_RST
#define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX


// addressBlock: uvd0_uvd_jrbc_dec
// base address: 0x1e400
#define mmUVD_JRBC_RB_WPTR
#define mmUVD_JRBC_RB_WPTR_BASE_IDX
#define mmUVD_JRBC_RB_CNTL
#define mmUVD_JRBC_RB_CNTL_BASE_IDX
#define mmUVD_JRBC_IB_SIZE
#define mmUVD_JRBC_IB_SIZE_BASE_IDX
#define mmUVD_JRBC_URGENT_CNTL
#define mmUVD_JRBC_URGENT_CNTL_BASE_IDX
#define mmUVD_JRBC_RB_REF_DATA
#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX
#define mmUVD_JRBC_RB_COND_RD_TIMER
#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX
#define mmUVD_JRBC_SOFT_RESET
#define mmUVD_JRBC_SOFT_RESET_BASE_IDX
#define mmUVD_JRBC_STATUS
#define mmUVD_JRBC_STATUS_BASE_IDX
#define mmUVD_JRBC_RB_RPTR
#define mmUVD_JRBC_RB_RPTR_BASE_IDX
#define mmUVD_JRBC_RB_BUF_STATUS
#define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX
#define mmUVD_JRBC_IB_BUF_STATUS
#define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX
#define mmUVD_JRBC_IB_SIZE_UPDATE
#define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX
#define mmUVD_JRBC_IB_COND_RD_TIMER
#define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX
#define mmUVD_JRBC_IB_REF_DATA
#define mmUVD_JRBC_IB_REF_DATA_BASE_IDX
#define mmUVD_JPEG_PREEMPT_CMD
#define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX
#define mmUVD_JPEG_PREEMPT_FENCE_DATA0
#define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX
#define mmUVD_JPEG_PREEMPT_FENCE_DATA1
#define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX
#define mmUVD_JRBC_RB_SIZE
#define mmUVD_JRBC_RB_SIZE_BASE_IDX
#define mmUVD_JRBC_SCRATCH0
#define mmUVD_JRBC_SCRATCH0_BASE_IDX


// addressBlock: uvd0_uvd_jrbc_enc_dec
// base address: 0x1e480
#define mmUVD_JRBC_ENC_RB_WPTR
#define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX
#define mmUVD_JRBC_ENC_RB_CNTL
#define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX
#define mmUVD_JRBC_ENC_IB_SIZE
#define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX
#define mmUVD_JRBC_ENC_URGENT_CNTL
#define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX
#define mmUVD_JRBC_ENC_RB_REF_DATA
#define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX
#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER
#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX
#define mmUVD_JRBC_ENC_SOFT_RESET
#define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX
#define mmUVD_JRBC_ENC_STATUS
#define mmUVD_JRBC_ENC_STATUS_BASE_IDX
#define mmUVD_JRBC_ENC_RB_RPTR
#define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX
#define mmUVD_JRBC_ENC_RB_BUF_STATUS
#define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX
#define mmUVD_JRBC_ENC_IB_BUF_STATUS
#define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX
#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE
#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX
#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER
#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX
#define mmUVD_JRBC_ENC_IB_REF_DATA
#define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX
#define mmUVD_JPEG_ENC_PREEMPT_CMD
#define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX
#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0
#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX
#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1
#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX
#define mmUVD_JRBC_ENC_RB_SIZE
#define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX
#define mmUVD_JRBC_ENC_SCRATCH0
#define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX


// addressBlock: uvd0_uvd_jmi_dec
// base address: 0x1e500
#define mmUVD_JADP_MCIF_URGENT_CTRL
#define mmUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX
#define mmUVD_JMI_URGENT_CTRL
#define mmUVD_JMI_URGENT_CTRL_BASE_IDX
#define mmUVD_JPEG_DEC_PF_CTRL
#define mmUVD_JPEG_DEC_PF_CTRL_BASE_IDX
#define mmUVD_JPEG_ENC_PF_CTRL
#define mmUVD_JPEG_ENC_PF_CTRL_BASE_IDX
#define mmUVD_JMI_CTRL
#define mmUVD_JMI_CTRL_BASE_IDX
#define mmUVD_LMI_JRBC_CTRL
#define mmUVD_LMI_JRBC_CTRL_BASE_IDX
#define mmUVD_LMI_JPEG_CTRL
#define mmUVD_LMI_JPEG_CTRL_BASE_IDX
#define mmUVD_JMI_EJRBC_CTRL
#define mmUVD_JMI_EJRBC_CTRL_BASE_IDX
#define mmUVD_LMI_EJPEG_CTRL
#define mmUVD_LMI_EJPEG_CTRL_BASE_IDX
#define mmUVD_JMI_SCALER_CTRL
#define mmUVD_JMI_SCALER_CTRL_BASE_IDX
#define mmJPEG_LMI_DROP
#define mmJPEG_LMI_DROP_BASE_IDX
#define mmUVD_JMI_EJPEG_DROP
#define mmUVD_JMI_EJPEG_DROP_BASE_IDX
#define mmJPEG_MEMCHECK_CLAMPING
#define mmJPEG_MEMCHECK_CLAMPING_BASE_IDX
#define mmUVD_JMI_EJPEG_MEMCHECK_CLAMPING
#define mmUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX
#define mmUVD_LMI_JRBC_IB_VMID
#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX
#define mmUVD_LMI_JRBC_RB_VMID
#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX
#define mmUVD_LMI_JPEG_VMID
#define mmUVD_LMI_JPEG_VMID_BASE_IDX
#define mmUVD_JMI_ENC_JRBC_IB_VMID
#define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX
#define mmUVD_JMI_ENC_JRBC_RB_VMID
#define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX
#define mmUVD_JMI_ENC_JPEG_VMID
#define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX
#define mmJPEG_MEMCHECK_SAFE_ADDR
#define mmJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX
#define mmJPEG_MEMCHECK_SAFE_ADDR_64BIT
#define mmJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX
#define mmUVD_JMI_LAT_CTRL
#define mmUVD_JMI_LAT_CTRL_BASE_IDX
#define mmUVD_JMI_LAT_CNTR
#define mmUVD_JMI_LAT_CNTR_BASE_IDX
#define mmUVD_JMI_AVG_LAT_CNTR
#define mmUVD_JMI_AVG_LAT_CNTR_BASE_IDX
#define mmUVD_JMI_PERFMON_CTRL
#define mmUVD_JMI_PERFMON_CTRL_BASE_IDX
#define mmUVD_JMI_PERFMON_COUNT_LO
#define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX
#define mmUVD_JMI_PERFMON_COUNT_HI
#define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX
#define mmUVD_JMI_CLEAN_STATUS
#define mmUVD_JMI_CLEAN_STATUS_BASE_IDX
#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW
#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH
#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW
#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH
#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW
#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW
#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH
#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_PEL_RD_64BIT_BAR_LOW
#define mmUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_PEL_RD_64BIT_BAR_HIGH
#define mmUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_BS_WR_64BIT_BAR_LOW
#define mmUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_BS_WR_64BIT_BAR_HIGH
#define mmUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_SCALAR_RD_64BIT_BAR_LOW
#define mmUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH
#define mmUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_SCALAR_WR_64BIT_BAR_LOW
#define mmUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH
#define mmUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW
#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW
#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH
#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JPEG_PREEMPT_VMID
#define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX
#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID
#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX
#define mmUVD_LMI_JPEG2_VMID
#define mmUVD_LMI_JPEG2_VMID_BASE_IDX
#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW
#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH
#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW
#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH
#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_JPEG_CTRL2
#define mmUVD_LMI_JPEG_CTRL2_BASE_IDX
#define mmUVD_JMI_DEC_SWAP_CNTL
#define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX
#define mmUVD_JMI_ENC_SWAP_CNTL
#define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX
#define mmUVD_JMI_CNTL
#define mmUVD_JMI_CNTL_BASE_IDX
#define mmUVD_JMI_ATOMIC_CNTL
#define mmUVD_JMI_ATOMIC_CNTL_BASE_IDX
#define mmUVD_JMI_ATOMIC_CNTL2
#define mmUVD_JMI_ATOMIC_CNTL2_BASE_IDX
#define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW
#define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH
#define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW
#define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH
#define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX
#define mmJPEG2_LMI_DROP
#define mmJPEG2_LMI_DROP_BASE_IDX
#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW
#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH
#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_JMI_DEC_SWAP_CNTL2
#define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX
#define mmUVD_JPEG_DEC2_PF_CTRL
#define mmUVD_JPEG_DEC2_PF_CTRL_BASE_IDX


// addressBlock: uvd0_uvd_jpeg_common_dec
// base address: 0x1e700
#define mmJPEG_SOFT_RESET_STATUS
#define mmJPEG_SOFT_RESET_STATUS_BASE_IDX
#define mmJPEG_SYS_INT_EN
#define mmJPEG_SYS_INT_EN_BASE_IDX
#define mmJPEG_SYS_INT_STATUS
#define mmJPEG_SYS_INT_STATUS_BASE_IDX
#define mmJPEG_SYS_INT_ACK
#define mmJPEG_SYS_INT_ACK_BASE_IDX
#define mmJPEG_MEMCHECK_SYS_INT_EN
#define mmJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX
#define mmJPEG_MEMCHECK_SYS_INT_STAT
#define mmJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX
#define mmJPEG_MEMCHECK_SYS_INT_ACK
#define mmJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX
#define mmUVD_JPEG_IOV_ACTIVE_FCN_ID
#define mmUVD_JPEG_IOV_ACTIVE_FCN_ID_BASE_IDX
#define mmJPEG_MASTINT_EN
#define mmJPEG_MASTINT_EN_BASE_IDX
#define mmJPEG_IH_CTRL
#define mmJPEG_IH_CTRL_BASE_IDX
#define mmJRBBM_ARB_CTRL
#define mmJRBBM_ARB_CTRL_BASE_IDX


// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
// base address: 0x1e780
#define mmJPEG_CGC_GATE
#define mmJPEG_CGC_GATE_BASE_IDX
#define mmJPEG_CGC_CTRL
#define mmJPEG_CGC_CTRL_BASE_IDX
#define mmJPEG_CGC_STATUS
#define mmJPEG_CGC_STATUS_BASE_IDX
#define mmJPEG_COMN_CGC_MEM_CTRL
#define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX
#define mmJPEG_DEC_CGC_MEM_CTRL
#define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX
#define mmJPEG2_DEC_CGC_MEM_CTRL
#define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX
#define mmJPEG_ENC_CGC_MEM_CTRL
#define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX
#define mmJPEG_SOFT_RESET2
#define mmJPEG_SOFT_RESET2_BASE_IDX
#define mmJPEG_PERF_BANK_CONF
#define mmJPEG_PERF_BANK_CONF_BASE_IDX
#define mmJPEG_PERF_BANK_EVENT_SEL
#define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX
#define mmJPEG_PERF_BANK_COUNT0
#define mmJPEG_PERF_BANK_COUNT0_BASE_IDX
#define mmJPEG_PERF_BANK_COUNT1
#define mmJPEG_PERF_BANK_COUNT1_BASE_IDX
#define mmJPEG_PERF_BANK_COUNT2
#define mmJPEG_PERF_BANK_COUNT2_BASE_IDX
#define mmJPEG_PERF_BANK_COUNT3
#define mmJPEG_PERF_BANK_COUNT3_BASE_IDX


// addressBlock: uvd0_uvd_pg_dec
// base address: 0x1f800
#define mmUVD_PGFSM_CONFIG
#define mmUVD_PGFSM_CONFIG_BASE_IDX
#define mmUVD_PGFSM_STATUS
#define mmUVD_PGFSM_STATUS_BASE_IDX
#define mmUVD_POWER_STATUS
#define mmUVD_POWER_STATUS_BASE_IDX
#define mmUVD_PG_IND_INDEX
#define mmUVD_PG_IND_INDEX_BASE_IDX
#define mmUVD_PG_IND_DATA
#define mmUVD_PG_IND_DATA_BASE_IDX
#define mmCC_UVD_HARVESTING
#define mmCC_UVD_HARVESTING_BASE_IDX
#define mmUVD_JPEG_POWER_STATUS
#define mmUVD_JPEG_POWER_STATUS_BASE_IDX
#define mmUVD_MC_DJPEG_RD_SPACE
#define mmUVD_MC_DJPEG_RD_SPACE_BASE_IDX
#define mmUVD_MC_DJPEG_WR_SPACE
#define mmUVD_MC_DJPEG_WR_SPACE_BASE_IDX
#define mmUVD_MC_EJPEG_RD_SPACE
#define mmUVD_MC_EJPEG_RD_SPACE_BASE_IDX
#define mmUVD_MC_EJPEG_WR_SPACE
#define mmUVD_MC_EJPEG_WR_SPACE_BASE_IDX
#define mmUVD_DPG_LMA_CTL
#define mmUVD_DPG_LMA_CTL_BASE_IDX
#define mmUVD_DPG_LMA_DATA
#define mmUVD_DPG_LMA_DATA_BASE_IDX
#define mmUVD_DPG_LMA_MASK
#define mmUVD_DPG_LMA_MASK_BASE_IDX
#define mmUVD_DPG_PAUSE
#define mmUVD_DPG_PAUSE_BASE_IDX
#define mmUVD_SCRATCH1
#define mmUVD_SCRATCH1_BASE_IDX
#define mmUVD_SCRATCH2
#define mmUVD_SCRATCH2_BASE_IDX
#define mmUVD_SCRATCH3
#define mmUVD_SCRATCH3_BASE_IDX
#define mmUVD_SCRATCH4
#define mmUVD_SCRATCH4_BASE_IDX
#define mmUVD_SCRATCH5
#define mmUVD_SCRATCH5_BASE_IDX
#define mmUVD_SCRATCH6
#define mmUVD_SCRATCH6_BASE_IDX
#define mmUVD_SCRATCH7
#define mmUVD_SCRATCH7_BASE_IDX
#define mmUVD_SCRATCH8
#define mmUVD_SCRATCH8_BASE_IDX
#define mmUVD_SCRATCH9
#define mmUVD_SCRATCH9_BASE_IDX
#define mmUVD_SCRATCH10
#define mmUVD_SCRATCH10_BASE_IDX
#define mmUVD_SCRATCH11
#define mmUVD_SCRATCH11_BASE_IDX
#define mmUVD_SCRATCH12
#define mmUVD_SCRATCH12_BASE_IDX
#define mmUVD_SCRATCH13
#define mmUVD_SCRATCH13_BASE_IDX
#define mmUVD_SCRATCH14
#define mmUVD_SCRATCH14_BASE_IDX
#define mmUVD_FREE_COUNTER_REG
#define mmUVD_FREE_COUNTER_REG_BASE_IDX
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_DPG_VCPU_CACHE_OFFSET0
#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX
#define mmUVD_DPG_LMI_VCPU_CACHE_VMID
#define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX
#define mmUVD_REG_FILTER_EN
#define mmUVD_REG_FILTER_EN_BASE_IDX
#define mmCC_UVD_VCPU_ERR_DETECT_BOT_LO
#define mmCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX
#define mmCC_UVD_VCPU_ERR_DETECT_BOT_HI
#define mmCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX
#define mmCC_UVD_VCPU_ERR_DETECT_TOP_LO
#define mmCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX
#define mmCC_UVD_VCPU_ERR_DETECT_TOP_HI
#define mmCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX
#define mmCC_UVD_VCPU_ERR
#define mmCC_UVD_VCPU_ERR_BASE_IDX
#define mmCC_UVD_VCPU_ERR_INST_ADDR_LO
#define mmCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX
#define mmCC_UVD_VCPU_ERR_INST_ADDR_HI
#define mmCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX
#define mmUVD_PF_STATUS
#define mmUVD_PF_STATUS_BASE_IDX
#define mmUVD_FW_VERSION
#define mmUVD_FW_VERSION_BASE_IDX
#define mmUVD_DPG_CLK_EN_VCPU_REPORT
#define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX
#define mmUVD_SECURITY_REG_VIO_REPORT
#define mmUVD_SECURITY_REG_VIO_REPORT_BASE_IDX
#define mmUVD_LMI_MMSCH_NC_SPACE
#define mmUVD_LMI_MMSCH_NC_SPACE_BASE_IDX
#define mmUVD_LMI_ATOMIC_SPACE
#define mmUVD_LMI_ATOMIC_SPACE_BASE_IDX
#define mmUVD_GFX10_ADDR_CONFIG
#define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX
#define mmUVD_GPCNT2_CNTL
#define mmUVD_GPCNT2_CNTL_BASE_IDX
#define mmUVD_GPCNT2_TARGET_LOWER
#define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX
#define mmUVD_GPCNT2_STATUS_LOWER
#define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX
#define mmUVD_GPCNT2_TARGET_UPPER
#define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX
#define mmUVD_GPCNT2_STATUS_UPPER
#define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX
#define mmUVD_GPCNT3_CNTL
#define mmUVD_GPCNT3_CNTL_BASE_IDX
#define mmUVD_GPCNT3_TARGET_LOWER
#define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX
#define mmUVD_GPCNT3_STATUS_LOWER
#define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX
#define mmUVD_GPCNT3_TARGET_UPPER
#define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX
#define mmUVD_GPCNT3_STATUS_UPPER
#define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX
#define mmUVD_VCLK_DS_CNTL
#define mmUVD_VCLK_DS_CNTL_BASE_IDX
#define mmUVD_DCLK_DS_CNTL
#define mmUVD_DCLK_DS_CNTL_BASE_IDX
#define mmUVD_TSC_LOWER
#define mmUVD_TSC_LOWER_BASE_IDX
#define mmUVD_TSC_UPPER
#define mmUVD_TSC_UPPER_BASE_IDX
#define mmVCN_FEATURES
#define mmVCN_FEATURES_BASE_IDX
#define mmUVD_GPUIOV_STATUS
#define mmUVD_GPUIOV_STATUS_BASE_IDX


// addressBlock: uvd0_uvddec
// base address: 0x1fa00
#define mmUVD_STATUS
#define mmUVD_STATUS_BASE_IDX
#define mmUVD_ENC_PIPE_BUSY
#define mmUVD_ENC_PIPE_BUSY_BASE_IDX
#define mmUVD_FW_POWER_STATUS
#define mmUVD_FW_POWER_STATUS_BASE_IDX
#define mmUVD_CNTL
#define mmUVD_CNTL_BASE_IDX
#define mmUVD_SOFT_RESET
#define mmUVD_SOFT_RESET_BASE_IDX
#define mmUVD_SOFT_RESET2
#define mmUVD_SOFT_RESET2_BASE_IDX
#define mmUVD_MMSCH_SOFT_RESET
#define mmUVD_MMSCH_SOFT_RESET_BASE_IDX
#define mmUVD_WIG_CTRL
#define mmUVD_WIG_CTRL_BASE_IDX
#define mmUVD_CGC_GATE
#define mmUVD_CGC_GATE_BASE_IDX
#define mmUVD_CGC_STATUS
#define mmUVD_CGC_STATUS_BASE_IDX
#define mmUVD_CGC_CTRL
#define mmUVD_CGC_CTRL_BASE_IDX
#define mmUVD_CGC_UDEC_STATUS
#define mmUVD_CGC_UDEC_STATUS_BASE_IDX
#define mmUVD_SUVD_CGC_GATE
#define mmUVD_SUVD_CGC_GATE_BASE_IDX
#define mmUVD_SUVD_CGC_STATUS
#define mmUVD_SUVD_CGC_STATUS_BASE_IDX
#define mmUVD_SUVD_CGC_CTRL
#define mmUVD_SUVD_CGC_CTRL_BASE_IDX
#define mmUVD_GPCOM_VCPU_CMD
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX
#define mmUVD_GPCOM_VCPU_DATA0
#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX
#define mmUVD_GPCOM_VCPU_DATA1
#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX
#define mmUVD_GPCOM_SYS_CMD
#define mmUVD_GPCOM_SYS_CMD_BASE_IDX
#define mmUVD_GPCOM_SYS_DATA0
#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX
#define mmUVD_GPCOM_SYS_DATA1
#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX
#define mmUVD_VCPU_INT_EN
#define mmUVD_VCPU_INT_EN_BASE_IDX
#define mmUVD_VCPU_INT_STATUS
#define mmUVD_VCPU_INT_STATUS_BASE_IDX
#define mmUVD_VCPU_INT_ACK
#define mmUVD_VCPU_INT_ACK_BASE_IDX
#define mmUVD_VCPU_INT_ROUTE
#define mmUVD_VCPU_INT_ROUTE_BASE_IDX
#define mmUVD_DRV_FW_MSG
#define mmUVD_DRV_FW_MSG_BASE_IDX
#define mmUVD_FW_DRV_MSG_ACK
#define mmUVD_FW_DRV_MSG_ACK_BASE_IDX
#define mmUVD_SUVD_INT_EN
#define mmUVD_SUVD_INT_EN_BASE_IDX
#define mmUVD_SUVD_INT_STATUS
#define mmUVD_SUVD_INT_STATUS_BASE_IDX
#define mmUVD_SUVD_INT_ACK
#define mmUVD_SUVD_INT_ACK_BASE_IDX
#define mmUVD_ENC_VCPU_INT_EN
#define mmUVD_ENC_VCPU_INT_EN_BASE_IDX
#define mmUVD_ENC_VCPU_INT_STATUS
#define mmUVD_ENC_VCPU_INT_STATUS_BASE_IDX
#define mmUVD_ENC_VCPU_INT_ACK
#define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX
#define mmUVD_MASTINT_EN
#define mmUVD_MASTINT_EN_BASE_IDX
#define mmUVD_SYS_INT_EN
#define mmUVD_SYS_INT_EN_BASE_IDX
#define mmUVD_SYS_INT_STATUS
#define mmUVD_SYS_INT_STATUS_BASE_IDX
#define mmUVD_SYS_INT_ACK
#define mmUVD_SYS_INT_ACK_BASE_IDX
#define mmUVD_JOB_DONE
#define mmUVD_JOB_DONE_BASE_IDX
#define mmUVD_CBUF_ID
#define mmUVD_CBUF_ID_BASE_IDX
#define mmUVD_CONTEXT_ID
#define mmUVD_CONTEXT_ID_BASE_IDX
#define mmUVD_CONTEXT_ID2
#define mmUVD_CONTEXT_ID2_BASE_IDX
#define mmUVD_NO_OP
#define mmUVD_NO_OP_BASE_IDX
#define mmUVD_RB_BASE_LO
#define mmUVD_RB_BASE_LO_BASE_IDX
#define mmUVD_RB_BASE_HI
#define mmUVD_RB_BASE_HI_BASE_IDX
#define mmUVD_RB_SIZE
#define mmUVD_RB_SIZE_BASE_IDX
#define mmUVD_RB_RPTR
#define mmUVD_RB_RPTR_BASE_IDX
#define mmUVD_RB_WPTR
#define mmUVD_RB_WPTR_BASE_IDX
#define mmUVD_RB_BASE_LO2
#define mmUVD_RB_BASE_LO2_BASE_IDX
#define mmUVD_RB_BASE_HI2
#define mmUVD_RB_BASE_HI2_BASE_IDX
#define mmUVD_RB_SIZE2
#define mmUVD_RB_SIZE2_BASE_IDX
#define mmUVD_RB_RPTR2
#define mmUVD_RB_RPTR2_BASE_IDX
#define mmUVD_RB_WPTR2
#define mmUVD_RB_WPTR2_BASE_IDX
#define mmUVD_RB_BASE_LO3
#define mmUVD_RB_BASE_LO3_BASE_IDX
#define mmUVD_RB_BASE_HI3
#define mmUVD_RB_BASE_HI3_BASE_IDX
#define mmUVD_RB_SIZE3
#define mmUVD_RB_SIZE3_BASE_IDX
#define mmUVD_RB_RPTR3
#define mmUVD_RB_RPTR3_BASE_IDX
#define mmUVD_RB_WPTR3
#define mmUVD_RB_WPTR3_BASE_IDX
#define mmUVD_RB_BASE_LO4
#define mmUVD_RB_BASE_LO4_BASE_IDX
#define mmUVD_RB_BASE_HI4
#define mmUVD_RB_BASE_HI4_BASE_IDX
#define mmUVD_RB_SIZE4
#define mmUVD_RB_SIZE4_BASE_IDX
#define mmUVD_RB_RPTR4
#define mmUVD_RB_RPTR4_BASE_IDX
#define mmUVD_RB_WPTR4
#define mmUVD_RB_WPTR4_BASE_IDX
#define mmUVD_OUT_RB_BASE_LO
#define mmUVD_OUT_RB_BASE_LO_BASE_IDX
#define mmUVD_OUT_RB_BASE_HI
#define mmUVD_OUT_RB_BASE_HI_BASE_IDX
#define mmUVD_OUT_RB_SIZE
#define mmUVD_OUT_RB_SIZE_BASE_IDX
#define mmUVD_OUT_RB_RPTR
#define mmUVD_OUT_RB_RPTR_BASE_IDX
#define mmUVD_OUT_RB_WPTR
#define mmUVD_OUT_RB_WPTR_BASE_IDX
#define mmUVD_IOV_ACTIVE_FCN_ID
#define mmUVD_IOV_ACTIVE_FCN_ID_BASE_IDX
#define mmUVD_IOV_MAILBOX
#define mmUVD_IOV_MAILBOX_BASE_IDX
#define mmUVD_IOV_MAILBOX_RESP
#define mmUVD_IOV_MAILBOX_RESP_BASE_IDX
#define mmUVD_RB_ARB_CTRL
#define mmUVD_RB_ARB_CTRL_BASE_IDX
#define mmUVD_CTX_INDEX
#define mmUVD_CTX_INDEX_BASE_IDX
#define mmUVD_CTX_DATA
#define mmUVD_CTX_DATA_BASE_IDX
#define mmUVD_CXW_WR
#define mmUVD_CXW_WR_BASE_IDX
#define mmUVD_CXW_WR_INT_ID
#define mmUVD_CXW_WR_INT_ID_BASE_IDX
#define mmUVD_CXW_WR_INT_CTX_ID
#define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX
#define mmUVD_CXW_INT_ID
#define mmUVD_CXW_INT_ID_BASE_IDX
#define mmUVD_MPEG2_ERROR
#define mmUVD_MPEG2_ERROR_BASE_IDX
#define mmUVD_TOP_CTRL
#define mmUVD_TOP_CTRL_BASE_IDX
#define mmUVD_YBASE
#define mmUVD_YBASE_BASE_IDX
#define mmUVD_UVBASE
#define mmUVD_UVBASE_BASE_IDX
#define mmUVD_PITCH
#define mmUVD_PITCH_BASE_IDX
#define mmUVD_WIDTH
#define mmUVD_WIDTH_BASE_IDX
#define mmUVD_HEIGHT
#define mmUVD_HEIGHT_BASE_IDX
#define mmUVD_PICCOUNT
#define mmUVD_PICCOUNT_BASE_IDX
#define mmUVD_MPRD_INITIAL_XY
#define mmUVD_MPRD_INITIAL_XY_BASE_IDX
#define mmUVD_MPEG2_CTRL
#define mmUVD_MPEG2_CTRL_BASE_IDX
#define mmUVD_MB_CTL_BUF_BASE
#define mmUVD_MB_CTL_BUF_BASE_BASE_IDX
#define mmUVD_PIC_CTL_BUF_BASE
#define mmUVD_PIC_CTL_BUF_BASE_BASE_IDX
#define mmUVD_DXVA_BUF_SIZE
#define mmUVD_DXVA_BUF_SIZE_BASE_IDX
#define mmUVD_SCRATCH_NP
#define mmUVD_SCRATCH_NP_BASE_IDX
#define mmUVD_CLK_SWT_HANDSHAKE
#define mmUVD_CLK_SWT_HANDSHAKE_BASE_IDX
#define mmUVD_VERSION
#define mmUVD_VERSION_BASE_IDX
#define mmUVD_GP_SCRATCH0
#define mmUVD_GP_SCRATCH0_BASE_IDX
#define mmUVD_GP_SCRATCH1
#define mmUVD_GP_SCRATCH1_BASE_IDX
#define mmUVD_GP_SCRATCH2
#define mmUVD_GP_SCRATCH2_BASE_IDX
#define mmUVD_GP_SCRATCH3
#define mmUVD_GP_SCRATCH3_BASE_IDX
#define mmUVD_GP_SCRATCH4
#define mmUVD_GP_SCRATCH4_BASE_IDX
#define mmUVD_GP_SCRATCH5
#define mmUVD_GP_SCRATCH5_BASE_IDX
#define mmUVD_GP_SCRATCH6
#define mmUVD_GP_SCRATCH6_BASE_IDX
#define mmUVD_GP_SCRATCH7
#define mmUVD_GP_SCRATCH7_BASE_IDX
#define mmUVD_GP_SCRATCH8
#define mmUVD_GP_SCRATCH8_BASE_IDX
#define mmUVD_GP_SCRATCH9
#define mmUVD_GP_SCRATCH9_BASE_IDX
#define mmUVD_GP_SCRATCH10
#define mmUVD_GP_SCRATCH10_BASE_IDX
#define mmUVD_GP_SCRATCH11
#define mmUVD_GP_SCRATCH11_BASE_IDX
#define mmUVD_GP_SCRATCH12
#define mmUVD_GP_SCRATCH12_BASE_IDX
#define mmUVD_GP_SCRATCH13
#define mmUVD_GP_SCRATCH13_BASE_IDX
#define mmUVD_GP_SCRATCH14
#define mmUVD_GP_SCRATCH14_BASE_IDX
#define mmUVD_GP_SCRATCH15
#define mmUVD_GP_SCRATCH15_BASE_IDX
#define mmUVD_GP_SCRATCH16
#define mmUVD_GP_SCRATCH16_BASE_IDX
#define mmUVD_GP_SCRATCH17
#define mmUVD_GP_SCRATCH17_BASE_IDX
#define mmUVD_GP_SCRATCH18
#define mmUVD_GP_SCRATCH18_BASE_IDX
#define mmUVD_GP_SCRATCH19
#define mmUVD_GP_SCRATCH19_BASE_IDX
#define mmUVD_GP_SCRATCH20
#define mmUVD_GP_SCRATCH20_BASE_IDX
#define mmUVD_GP_SCRATCH21
#define mmUVD_GP_SCRATCH21_BASE_IDX
#define mmUVD_GP_SCRATCH22
#define mmUVD_GP_SCRATCH22_BASE_IDX
#define mmUVD_GP_SCRATCH23
#define mmUVD_GP_SCRATCH23_BASE_IDX
#define mmUVD_AUDIO_RB_BASE_LO
#define mmUVD_AUDIO_RB_BASE_LO_BASE_IDX
#define mmUVD_AUDIO_RB_BASE_HI
#define mmUVD_AUDIO_RB_BASE_HI_BASE_IDX
#define mmUVD_AUDIO_RB_SIZE
#define mmUVD_AUDIO_RB_SIZE_BASE_IDX
#define mmUVD_AUDIO_RB_RPTR
#define mmUVD_AUDIO_RB_RPTR_BASE_IDX
#define mmUVD_AUDIO_RB_WPTR
#define mmUVD_AUDIO_RB_WPTR_BASE_IDX
#define mmUVD_VCPU_INT_STATUS2
#define mmUVD_VCPU_INT_STATUS2_BASE_IDX
#define mmUVD_VCPU_INT_ACK2
#define mmUVD_VCPU_INT_ACK2_BASE_IDX
#define mmUVD_VCPU_INT_EN2
#define mmUVD_VCPU_INT_EN2_BASE_IDX
#define mmUVD_SUVD_CGC_STATUS2
#define mmUVD_SUVD_CGC_STATUS2_BASE_IDX
#define mmUVD_SUVD_CGC_GATE2
#define mmUVD_SUVD_CGC_GATE2_BASE_IDX
#define mmUVD_SUVD_INT_STATUS2
#define mmUVD_SUVD_INT_STATUS2_BASE_IDX
#define mmUVD_SUVD_INT_EN2
#define mmUVD_SUVD_INT_EN2_BASE_IDX
#define mmUVD_SUVD_INT_ACK2
#define mmUVD_SUVD_INT_ACK2_BASE_IDX


// addressBlock: uvd0_ecpudec
// base address: 0x1fd00
#define mmUVD_VCPU_CACHE_OFFSET0
#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE0
#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET1
#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE1
#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET2
#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE2
#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET3
#define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE3
#define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET4
#define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE4
#define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET5
#define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE5
#define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET6
#define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE6
#define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET7
#define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE7
#define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX
#define mmUVD_VCPU_CACHE_OFFSET8
#define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX
#define mmUVD_VCPU_CACHE_SIZE8
#define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX
#define mmUVD_VCPU_NONCACHE_OFFSET0
#define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX
#define mmUVD_VCPU_NONCACHE_SIZE0
#define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX
#define mmUVD_VCPU_NONCACHE_OFFSET1
#define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX
#define mmUVD_VCPU_NONCACHE_SIZE1
#define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX
#define mmUVD_VCPU_CNTL
#define mmUVD_VCPU_CNTL_BASE_IDX
#define mmUVD_VCPU_PRID
#define mmUVD_VCPU_PRID_BASE_IDX
#define mmUVD_VCPU_TRCE
#define mmUVD_VCPU_TRCE_BASE_IDX
#define mmUVD_VCPU_TRCE_RD
#define mmUVD_VCPU_TRCE_RD_BASE_IDX
#define mmUVD_VCPU_IND_INDEX
#define mmUVD_VCPU_IND_INDEX_BASE_IDX
#define mmUVD_VCPU_IND_DATA
#define mmUVD_VCPU_IND_DATA_BASE_IDX


// addressBlock: uvd0_uvd_mpcdec
// base address: 0x20310
#define mmUVD_MP_SWAP_CNTL
#define mmUVD_MP_SWAP_CNTL_BASE_IDX
#define mmUVD_MP_SWAP_CNTL2
#define mmUVD_MP_SWAP_CNTL2_BASE_IDX
#define mmUVD_MPC_LUMA_SRCH
#define mmUVD_MPC_LUMA_SRCH_BASE_IDX
#define mmUVD_MPC_LUMA_HIT
#define mmUVD_MPC_LUMA_HIT_BASE_IDX
#define mmUVD_MPC_LUMA_HITPEND
#define mmUVD_MPC_LUMA_HITPEND_BASE_IDX
#define mmUVD_MPC_CHROMA_SRCH
#define mmUVD_MPC_CHROMA_SRCH_BASE_IDX
#define mmUVD_MPC_CHROMA_HIT
#define mmUVD_MPC_CHROMA_HIT_BASE_IDX
#define mmUVD_MPC_CHROMA_HITPEND
#define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX
#define mmUVD_MPC_CNTL
#define mmUVD_MPC_CNTL_BASE_IDX
#define mmUVD_MPC_PITCH
#define mmUVD_MPC_PITCH_BASE_IDX
#define mmUVD_MPC_SET_MUXA0
#define mmUVD_MPC_SET_MUXA0_BASE_IDX
#define mmUVD_MPC_SET_MUXA1
#define mmUVD_MPC_SET_MUXA1_BASE_IDX
#define mmUVD_MPC_SET_MUXB0
#define mmUVD_MPC_SET_MUXB0_BASE_IDX
#define mmUVD_MPC_SET_MUXB1
#define mmUVD_MPC_SET_MUXB1_BASE_IDX
#define mmUVD_MPC_SET_MUX
#define mmUVD_MPC_SET_MUX_BASE_IDX
#define mmUVD_MPC_SET_ALU
#define mmUVD_MPC_SET_ALU_BASE_IDX
#define mmUVD_MPC_PERF0
#define mmUVD_MPC_PERF0_BASE_IDX
#define mmUVD_MPC_PERF1
#define mmUVD_MPC_PERF1_BASE_IDX
#define mmUVD_MPC_IND_INDEX
#define mmUVD_MPC_IND_INDEX_BASE_IDX
#define mmUVD_MPC_IND_DATA
#define mmUVD_MPC_IND_DATA_BASE_IDX


// addressBlock: uvd0_uvd_rbcdec
// base address: 0x20370
#define mmUVD_RBC_IB_SIZE
#define mmUVD_RBC_IB_SIZE_BASE_IDX
#define mmUVD_RBC_IB_SIZE_UPDATE
#define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX
#define mmUVD_RBC_RB_CNTL
#define mmUVD_RBC_RB_CNTL_BASE_IDX
#define mmUVD_RBC_RB_RPTR_ADDR
#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX
#define mmUVD_RBC_RB_RPTR
#define mmUVD_RBC_RB_RPTR_BASE_IDX
#define mmUVD_RBC_RB_WPTR
#define mmUVD_RBC_RB_WPTR_BASE_IDX
#define mmUVD_RBC_VCPU_ACCESS
#define mmUVD_RBC_VCPU_ACCESS_BASE_IDX
#define mmUVD_FW_SEMAPHORE_CNTL
#define mmUVD_FW_SEMAPHORE_CNTL_BASE_IDX
#define mmUVD_RBC_READ_REQ_URGENT_CNTL
#define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX
#define mmUVD_RBC_RB_WPTR_CNTL
#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX
#define mmUVD_RBC_WPTR_STATUS
#define mmUVD_RBC_WPTR_STATUS_BASE_IDX
#define mmUVD_RBC_WPTR_POLL_CNTL
#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX
#define mmUVD_RBC_WPTR_POLL_ADDR
#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX
#define mmUVD_SEMA_CMD
#define mmUVD_SEMA_CMD_BASE_IDX
#define mmUVD_SEMA_ADDR_LOW
#define mmUVD_SEMA_ADDR_LOW_BASE_IDX
#define mmUVD_SEMA_ADDR_HIGH
#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX
#define mmUVD_ENGINE_CNTL
#define mmUVD_ENGINE_CNTL_BASE_IDX
#define mmUVD_SEMA_TIMEOUT_STATUS
#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX
#define mmUVD_SEMA_CNTL
#define mmUVD_SEMA_CNTL_BASE_IDX
#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX
#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX
#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX
#define mmUVD_JOB_START
#define mmUVD_JOB_START_BASE_IDX
#define mmUVD_RBC_BUF_STATUS
#define mmUVD_RBC_BUF_STATUS_BASE_IDX
#define mmUVD_RBC_SWAP_CNTL
#define mmUVD_RBC_SWAP_CNTL_BASE_IDX


// addressBlock: uvd0_lmi_adpdec
// base address: 0x20870
#define mmUVD_LMI_RE_64BIT_BAR_LOW
#define mmUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_RE_64BIT_BAR_HIGH
#define mmUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_IT_64BIT_BAR_LOW
#define mmUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_IT_64BIT_BAR_HIGH
#define mmUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MP_64BIT_BAR_LOW
#define mmUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MP_64BIT_BAR_HIGH
#define mmUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_CM_64BIT_BAR_LOW
#define mmUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_CM_64BIT_BAR_HIGH
#define mmUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_DB_64BIT_BAR_LOW
#define mmUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_DB_64BIT_BAR_HIGH
#define mmUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_DBW_64BIT_BAR_LOW
#define mmUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_DBW_64BIT_BAR_HIGH
#define mmUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_IDCT_64BIT_BAR_LOW
#define mmUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_IDCT_64BIT_BAR_HIGH
#define mmUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MPRD_S0_64BIT_BAR_LOW
#define mmUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MPRD_S0_64BIT_BAR_HIGH
#define mmUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MPRD_S1_64BIT_BAR_LOW
#define mmUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MPRD_S1_64BIT_BAR_HIGH
#define mmUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MPRD_DBW_64BIT_BAR_LOW
#define mmUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH
#define mmUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MPC_64BIT_BAR_LOW
#define mmUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MPC_64BIT_BAR_HIGH
#define mmUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_LBSI_64BIT_BAR_LOW
#define mmUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_LBSI_64BIT_BAR_HIGH
#define mmUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_CENC_64BIT_BAR_LOW
#define mmUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_CENC_64BIT_BAR_HIGH
#define mmUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_SRE_64BIT_BAR_LOW
#define mmUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_SRE_64BIT_BAR_HIGH
#define mmUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_REF_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW
#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH
#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_SPH_64BIT_BAR_HIGH
#define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW
#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH
#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MMSCH_NC_VMID
#define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX
#define mmUVD_LMI_MMSCH_CTRL
#define mmUVD_LMI_MMSCH_CTRL_BASE_IDX
#define mmUVD_MMSCH_LMI_STATUS
#define mmUVD_MMSCH_LMI_STATUS_BASE_IDX
#define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX
#define mmUVD_ADP_ATOMIC_CONFIG
#define mmUVD_ADP_ATOMIC_CONFIG_BASE_IDX
#define mmUVD_LMI_ARB_CTRL2
#define mmUVD_LMI_ARB_CTRL2_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI
#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX
#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI
#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX
#define mmUVD_LMI_LAT_CTRL
#define mmUVD_LMI_LAT_CTRL_BASE_IDX
#define mmUVD_LMI_LAT_CNTR
#define mmUVD_LMI_LAT_CNTR_BASE_IDX
#define mmUVD_LMI_AVG_LAT_CNTR
#define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX
#define mmUVD_LMI_SPH
#define mmUVD_LMI_SPH_BASE_IDX
#define mmUVD_LMI_VCPU_CACHE_VMID
#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX
#define mmUVD_LMI_CTRL2
#define mmUVD_LMI_CTRL2_BASE_IDX
#define mmUVD_LMI_URGENT_CTRL
#define mmUVD_LMI_URGENT_CTRL_BASE_IDX
#define mmUVD_LMI_CTRL
#define mmUVD_LMI_CTRL_BASE_IDX
#define mmUVD_LMI_STATUS
#define mmUVD_LMI_STATUS_BASE_IDX
#define mmUVD_LMI_PERFMON_CTRL
#define mmUVD_LMI_PERFMON_CTRL_BASE_IDX
#define mmUVD_LMI_PERFMON_COUNT_LO
#define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX
#define mmUVD_LMI_PERFMON_COUNT_HI
#define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX
#define mmUVD_LMI_ADP_SWAP_CNTL
#define mmUVD_LMI_ADP_SWAP_CNTL_BASE_IDX
#define mmUVD_LMI_RBC_RB_VMID
#define mmUVD_LMI_RBC_RB_VMID_BASE_IDX
#define mmUVD_LMI_RBC_IB_VMID
#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX
#define mmUVD_LMI_MC_CREDITS
#define mmUVD_LMI_MC_CREDITS_BASE_IDX
#define mmUVD_LMI_ADP_IND_INDEX
#define mmUVD_LMI_ADP_IND_INDEX_BASE_IDX
#define mmUVD_LMI_ADP_IND_DATA
#define mmUVD_LMI_ADP_IND_DATA_BASE_IDX
#define mmUVD_LMI_ADP_PF_EN
#define mmUVD_LMI_ADP_PF_EN_BASE_IDX
#define mmUVD_LMI_ADP_CNN_CTRL
#define mmUVD_LMI_ADP_CNN_CTRL_BASE_IDX
#define mmUVD_LMI_PREF_CTRL
#define mmUVD_LMI_PREF_CTRL_BASE_IDX
#define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW
#define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX
#define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH
#define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX


// addressBlock: uvdctxind
// base address: 0x0
#define ixUVD_CGC_MEM_CTRL
#define ixUVD_CGC_CTRL2
#define ixUVD_CGC_MEM_DS_CTRL
#define ixUVD_CGC_MEM_SD_CTRL
#define ixUVD_SW_SCRATCH_00
#define ixUVD_SW_SCRATCH_01
#define ixUVD_SW_SCRATCH_02
#define ixUVD_SW_SCRATCH_03
#define ixUVD_SW_SCRATCH_04
#define ixUVD_SW_SCRATCH_05
#define ixUVD_SW_SCRATCH_06
#define ixUVD_SW_SCRATCH_07
#define ixUVD_SW_SCRATCH_08
#define ixUVD_SW_SCRATCH_09
#define ixUVD_SW_SCRATCH_10
#define ixUVD_SW_SCRATCH_11
#define ixUVD_SW_SCRATCH_12
#define ixUVD_SW_SCRATCH_13
#define ixUVD_SW_SCRATCH_14
#define ixUVD_SW_SCRATCH_15
#define ixUVD_MEMCHECK_SYS_INT_EN
#define ixUVD_MEMCHECK_SYS_INT_STAT
#define ixUVD_MEMCHECK_SYS_INT_ACK
#define ixUVD_MEMCHECK_VCPU_INT_EN
#define ixUVD_MEMCHECK_VCPU_INT_STAT
#define ixUVD_MEMCHECK_VCPU_INT_ACK
#define ixUVD_MEMCHECK2_SYS_INT_STAT
#define ixUVD_MEMCHECK2_SYS_INT_ACK
#define ixUVD_MEMCHECK2_VCPU_INT_STAT
#define ixUVD_MEMCHECK2_VCPU_INT_ACK
#define ixUVD_IH_SEM_CTRL


#endif