/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _vcn_4_0_3_OFFSET_HEADER #define _vcn_4_0_3_OFFSET_HEADER // addressBlock: aid_uvd0_uvddec // base address: 0x1fb00 #define regUVD_TOP_CTRL … #define regUVD_TOP_CTRL_BASE_IDX … #define regUVD_CGC_GATE … #define regUVD_CGC_GATE_BASE_IDX … #define regUVD_CGC_CTRL … #define regUVD_CGC_CTRL_BASE_IDX … #define regAVM_SUVD_CGC_GATE … #define regAVM_SUVD_CGC_GATE_BASE_IDX … #define regCDEFE_SUVD_CGC_GATE … #define regCDEFE_SUVD_CGC_GATE_BASE_IDX … #define regEFC_SUVD_CGC_GATE … #define regEFC_SUVD_CGC_GATE_BASE_IDX … #define regENT_SUVD_CGC_GATE … #define regENT_SUVD_CGC_GATE_BASE_IDX … #define regIME_SUVD_CGC_GATE … #define regIME_SUVD_CGC_GATE_BASE_IDX … #define regPPU_SUVD_CGC_GATE … #define regPPU_SUVD_CGC_GATE_BASE_IDX … #define regSAOE_SUVD_CGC_GATE … #define regSAOE_SUVD_CGC_GATE_BASE_IDX … #define regSCM_SUVD_CGC_GATE … #define regSCM_SUVD_CGC_GATE_BASE_IDX … #define regSDB_SUVD_CGC_GATE … #define regSDB_SUVD_CGC_GATE_BASE_IDX … #define regSIT0_NXT_SUVD_CGC_GATE … #define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX … #define regSIT1_NXT_SUVD_CGC_GATE … #define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX … #define regSIT2_NXT_SUVD_CGC_GATE … #define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX … #define regSIT_SUVD_CGC_GATE … #define regSIT_SUVD_CGC_GATE_BASE_IDX … #define regSMPA_SUVD_CGC_GATE … #define regSMPA_SUVD_CGC_GATE_BASE_IDX … #define regSMP_SUVD_CGC_GATE … #define regSMP_SUVD_CGC_GATE_BASE_IDX … #define regSRE_SUVD_CGC_GATE … #define regSRE_SUVD_CGC_GATE_BASE_IDX … #define regUVD_MPBE0_SUVD_CGC_GATE … #define regUVD_MPBE0_SUVD_CGC_GATE_BASE_IDX … #define regUVD_MPBE1_SUVD_CGC_GATE … #define regUVD_MPBE1_SUVD_CGC_GATE_BASE_IDX … #define regUVD_SUVD_CGC_GATE … #define regUVD_SUVD_CGC_GATE_BASE_IDX … #define regAVM_SUVD_CGC_GATE2 … #define regAVM_SUVD_CGC_GATE2_BASE_IDX … #define regCDEFE_SUVD_CGC_GATE2 … #define regCDEFE_SUVD_CGC_GATE2_BASE_IDX … #define regDBR_SUVD_CGC_GATE2 … #define regDBR_SUVD_CGC_GATE2_BASE_IDX … #define regENT_SUVD_CGC_GATE2 … #define regENT_SUVD_CGC_GATE2_BASE_IDX … #define regIME_SUVD_CGC_GATE2 … #define regIME_SUVD_CGC_GATE2_BASE_IDX … #define regMPC1_SUVD_CGC_GATE2 … #define regMPC1_SUVD_CGC_GATE2_BASE_IDX … #define regSAOE_SUVD_CGC_GATE2 … #define regSAOE_SUVD_CGC_GATE2_BASE_IDX … #define regSDB_SUVD_CGC_GATE2 … #define regSDB_SUVD_CGC_GATE2_BASE_IDX … #define regSIT0_NXT_SUVD_CGC_GATE2 … #define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX … #define regSIT1_NXT_SUVD_CGC_GATE2 … #define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX … #define regSIT2_NXT_SUVD_CGC_GATE2 … #define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX … #define regSIT_SUVD_CGC_GATE2 … #define regSIT_SUVD_CGC_GATE2_BASE_IDX … #define regSMPA_SUVD_CGC_GATE2 … #define regSMPA_SUVD_CGC_GATE2_BASE_IDX … #define regSMP_SUVD_CGC_GATE2 … #define regSMP_SUVD_CGC_GATE2_BASE_IDX … #define regSRE_SUVD_CGC_GATE2 … #define regSRE_SUVD_CGC_GATE2_BASE_IDX … #define regUVD_MPBE0_SUVD_CGC_GATE2 … #define regUVD_MPBE0_SUVD_CGC_GATE2_BASE_IDX … #define regUVD_MPBE1_SUVD_CGC_GATE2 … #define regUVD_MPBE1_SUVD_CGC_GATE2_BASE_IDX … #define regUVD_SUVD_CGC_GATE2 … #define regUVD_SUVD_CGC_GATE2_BASE_IDX … #define regAVM_SUVD_CGC_CTRL … #define regAVM_SUVD_CGC_CTRL_BASE_IDX … #define regCDEFE_SUVD_CGC_CTRL … #define regCDEFE_SUVD_CGC_CTRL_BASE_IDX … #define regDBR_SUVD_CGC_CTRL … #define regDBR_SUVD_CGC_CTRL_BASE_IDX … #define regEFC_SUVD_CGC_CTRL … #define regEFC_SUVD_CGC_CTRL_BASE_IDX … #define regENT_SUVD_CGC_CTRL … #define regENT_SUVD_CGC_CTRL_BASE_IDX … #define regIME_SUVD_CGC_CTRL … #define regIME_SUVD_CGC_CTRL_BASE_IDX … #define regMPC1_SUVD_CGC_CTRL … #define regMPC1_SUVD_CGC_CTRL_BASE_IDX … #define regPPU_SUVD_CGC_CTRL … #define regPPU_SUVD_CGC_CTRL_BASE_IDX … #define regSAOE_SUVD_CGC_CTRL … #define regSAOE_SUVD_CGC_CTRL_BASE_IDX … #define regSCM_SUVD_CGC_CTRL … #define regSCM_SUVD_CGC_CTRL_BASE_IDX … #define regSDB_SUVD_CGC_CTRL … #define regSDB_SUVD_CGC_CTRL_BASE_IDX … #define regSIT0_NXT_SUVD_CGC_CTRL … #define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX … #define regSIT1_NXT_SUVD_CGC_CTRL … #define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX … #define regSIT2_NXT_SUVD_CGC_CTRL … #define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX … #define regSIT_SUVD_CGC_CTRL … #define regSIT_SUVD_CGC_CTRL_BASE_IDX … #define regSMPA_SUVD_CGC_CTRL … #define regSMPA_SUVD_CGC_CTRL_BASE_IDX … #define regSMP_SUVD_CGC_CTRL … #define regSMP_SUVD_CGC_CTRL_BASE_IDX … #define regSRE_SUVD_CGC_CTRL … #define regSRE_SUVD_CGC_CTRL_BASE_IDX … #define regUVD_MPBE0_SUVD_CGC_CTRL … #define regUVD_MPBE0_SUVD_CGC_CTRL_BASE_IDX … #define regUVD_MPBE1_SUVD_CGC_CTRL … #define regUVD_MPBE1_SUVD_CGC_CTRL_BASE_IDX … #define regUVD_SUVD_CGC_CTRL … #define regUVD_SUVD_CGC_CTRL_BASE_IDX … #define regUVD_CGC_CTRL3 … #define regUVD_CGC_CTRL3_BASE_IDX … #define regUVD_GPCOM_VCPU_DATA0 … #define regUVD_GPCOM_VCPU_DATA0_BASE_IDX … #define regUVD_GPCOM_VCPU_DATA1 … #define regUVD_GPCOM_VCPU_DATA1_BASE_IDX … #define regUVD_GPCOM_SYS_CMD … #define regUVD_GPCOM_SYS_CMD_BASE_IDX … #define regUVD_GPCOM_SYS_DATA0 … #define regUVD_GPCOM_SYS_DATA0_BASE_IDX … #define regUVD_GPCOM_SYS_DATA1 … #define regUVD_GPCOM_SYS_DATA1_BASE_IDX … #define regUVD_VCPU_INT_EN … #define regUVD_VCPU_INT_EN_BASE_IDX … #define regUVD_VCPU_INT_STATUS … #define regUVD_VCPU_INT_STATUS_BASE_IDX … #define regUVD_VCPU_INT_ACK … #define regUVD_VCPU_INT_ACK_BASE_IDX … #define regUVD_VCPU_INT_ROUTE … #define regUVD_VCPU_INT_ROUTE_BASE_IDX … #define regUVD_DRV_FW_MSG … #define regUVD_DRV_FW_MSG_BASE_IDX … #define regUVD_FW_DRV_MSG_ACK … #define regUVD_FW_DRV_MSG_ACK_BASE_IDX … #define regUVD_SUVD_INT_EN … #define regUVD_SUVD_INT_EN_BASE_IDX … #define regUVD_SUVD_INT_STATUS … #define regUVD_SUVD_INT_STATUS_BASE_IDX … #define regUVD_SUVD_INT_ACK … #define regUVD_SUVD_INT_ACK_BASE_IDX … #define regUVD_ENC_VCPU_INT_EN … #define regUVD_ENC_VCPU_INT_EN_BASE_IDX … #define regUVD_ENC_VCPU_INT_STATUS … #define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX … #define regUVD_ENC_VCPU_INT_ACK … #define regUVD_ENC_VCPU_INT_ACK_BASE_IDX … #define regUVD_MASTINT_EN … #define regUVD_MASTINT_EN_BASE_IDX … #define regUVD_SYS_INT_EN … #define regUVD_SYS_INT_EN_BASE_IDX … #define regUVD_SYS_INT_STATUS … #define regUVD_SYS_INT_STATUS_BASE_IDX … #define regUVD_SYS_INT_ACK … #define regUVD_SYS_INT_ACK_BASE_IDX … #define regUVD_JOB_DONE … #define regUVD_JOB_DONE_BASE_IDX … #define regUVD_CBUF_ID … #define regUVD_CBUF_ID_BASE_IDX … #define regUVD_CONTEXT_ID … #define regUVD_CONTEXT_ID_BASE_IDX … #define regUVD_CONTEXT_ID2 … #define regUVD_CONTEXT_ID2_BASE_IDX … #define regUVD_NO_OP … #define regUVD_NO_OP_BASE_IDX … #define regUVD_RB_BASE_LO … #define regUVD_RB_BASE_LO_BASE_IDX … #define regUVD_RB_BASE_HI … #define regUVD_RB_BASE_HI_BASE_IDX … #define regUVD_RB_SIZE … #define regUVD_RB_SIZE_BASE_IDX … #define regUVD_RB_BASE_LO2 … #define regUVD_RB_BASE_LO2_BASE_IDX … #define regUVD_RB_BASE_HI2 … #define regUVD_RB_BASE_HI2_BASE_IDX … #define regUVD_RB_SIZE2 … #define regUVD_RB_SIZE2_BASE_IDX … #define regUVD_RB_BASE_LO3 … #define regUVD_RB_BASE_LO3_BASE_IDX … #define regUVD_RB_BASE_HI3 … #define regUVD_RB_BASE_HI3_BASE_IDX … #define regUVD_RB_SIZE3 … #define regUVD_RB_SIZE3_BASE_IDX … #define regUVD_RB_BASE_LO4 … #define regUVD_RB_BASE_LO4_BASE_IDX … #define regUVD_RB_BASE_HI4 … #define regUVD_RB_BASE_HI4_BASE_IDX … #define regUVD_RB_SIZE4 … #define regUVD_RB_SIZE4_BASE_IDX … #define regUVD_OUT_RB_BASE_LO … #define regUVD_OUT_RB_BASE_LO_BASE_IDX … #define regUVD_OUT_RB_BASE_HI … #define regUVD_OUT_RB_BASE_HI_BASE_IDX … #define regUVD_OUT_RB_SIZE … #define regUVD_OUT_RB_SIZE_BASE_IDX … #define regUVD_IOV_ACTIVE_FCN_ID … #define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX … #define regUVD_IOV_MAILBOX … #define regUVD_IOV_MAILBOX_BASE_IDX … #define regUVD_IOV_MAILBOX_RESP … #define regUVD_IOV_MAILBOX_RESP_BASE_IDX … #define regUVD_RB_ARB_CTRL … #define regUVD_RB_ARB_CTRL_BASE_IDX … #define regUVD_CTX_INDEX … #define regUVD_CTX_INDEX_BASE_IDX … #define regUVD_CTX_DATA … #define regUVD_CTX_DATA_BASE_IDX … #define regUVD_CXW_WR … #define regUVD_CXW_WR_BASE_IDX … #define regUVD_CXW_WR_INT_ID … #define regUVD_CXW_WR_INT_ID_BASE_IDX … #define regUVD_CXW_WR_INT_CTX_ID … #define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX … #define regUVD_CXW_INT_ID … #define regUVD_CXW_INT_ID_BASE_IDX … #define regUVD_MPEG2_ERROR … #define regUVD_MPEG2_ERROR_BASE_IDX … #define regUVD_YBASE … #define regUVD_YBASE_BASE_IDX … #define regUVD_UVBASE … #define regUVD_UVBASE_BASE_IDX … #define regUVD_PITCH … #define regUVD_PITCH_BASE_IDX … #define regUVD_WIDTH … #define regUVD_WIDTH_BASE_IDX … #define regUVD_HEIGHT … #define regUVD_HEIGHT_BASE_IDX … #define regUVD_PICCOUNT … #define regUVD_PICCOUNT_BASE_IDX … #define regUVD_MPRD_INITIAL_XY … #define regUVD_MPRD_INITIAL_XY_BASE_IDX … #define regUVD_MPEG2_CTRL … #define regUVD_MPEG2_CTRL_BASE_IDX … #define regUVD_MB_CTL_BUF_BASE … #define regUVD_MB_CTL_BUF_BASE_BASE_IDX … #define regUVD_PIC_CTL_BUF_BASE … #define regUVD_PIC_CTL_BUF_BASE_BASE_IDX … #define regUVD_DXVA_BUF_SIZE … #define regUVD_DXVA_BUF_SIZE_BASE_IDX … #define regUVD_SCRATCH_NP … #define regUVD_SCRATCH_NP_BASE_IDX … #define regUVD_CLK_SWT_HANDSHAKE … #define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX … #define regUVD_GP_SCRATCH0 … #define regUVD_GP_SCRATCH0_BASE_IDX … #define regUVD_GP_SCRATCH1 … #define regUVD_GP_SCRATCH1_BASE_IDX … #define regUVD_GP_SCRATCH2 … #define regUVD_GP_SCRATCH2_BASE_IDX … #define regUVD_GP_SCRATCH3 … #define regUVD_GP_SCRATCH3_BASE_IDX … #define regUVD_GP_SCRATCH4 … #define regUVD_GP_SCRATCH4_BASE_IDX … #define regUVD_GP_SCRATCH5 … #define regUVD_GP_SCRATCH5_BASE_IDX … #define regUVD_GP_SCRATCH6 … #define regUVD_GP_SCRATCH6_BASE_IDX … #define regUVD_GP_SCRATCH7 … #define regUVD_GP_SCRATCH7_BASE_IDX … #define regUVD_GP_SCRATCH8 … #define regUVD_GP_SCRATCH8_BASE_IDX … #define regUVD_GP_SCRATCH9 … #define regUVD_GP_SCRATCH9_BASE_IDX … #define regUVD_GP_SCRATCH10 … #define regUVD_GP_SCRATCH10_BASE_IDX … #define regUVD_GP_SCRATCH11 … #define regUVD_GP_SCRATCH11_BASE_IDX … #define regUVD_GP_SCRATCH12 … #define regUVD_GP_SCRATCH12_BASE_IDX … #define regUVD_GP_SCRATCH13 … #define regUVD_GP_SCRATCH13_BASE_IDX … #define regUVD_GP_SCRATCH14 … #define regUVD_GP_SCRATCH14_BASE_IDX … #define regUVD_GP_SCRATCH15 … #define regUVD_GP_SCRATCH15_BASE_IDX … #define regUVD_GP_SCRATCH16 … #define regUVD_GP_SCRATCH16_BASE_IDX … #define regUVD_GP_SCRATCH17 … #define regUVD_GP_SCRATCH17_BASE_IDX … #define regUVD_GP_SCRATCH18 … #define regUVD_GP_SCRATCH18_BASE_IDX … #define regUVD_GP_SCRATCH19 … #define regUVD_GP_SCRATCH19_BASE_IDX … #define regUVD_GP_SCRATCH20 … #define regUVD_GP_SCRATCH20_BASE_IDX … #define regUVD_GP_SCRATCH21 … #define regUVD_GP_SCRATCH21_BASE_IDX … #define regUVD_GP_SCRATCH22 … #define regUVD_GP_SCRATCH22_BASE_IDX … #define regUVD_GP_SCRATCH23 … #define regUVD_GP_SCRATCH23_BASE_IDX … #define regUVD_AUDIO_RB_BASE_LO … #define regUVD_AUDIO_RB_BASE_LO_BASE_IDX … #define regUVD_AUDIO_RB_BASE_HI … #define regUVD_AUDIO_RB_BASE_HI_BASE_IDX … #define regUVD_AUDIO_RB_SIZE … #define regUVD_AUDIO_RB_SIZE_BASE_IDX … #define regUVD_VCPU_INT_STATUS2 … #define regUVD_VCPU_INT_STATUS2_BASE_IDX … #define regUVD_VCPU_INT_ACK2 … #define regUVD_VCPU_INT_ACK2_BASE_IDX … #define regUVD_VCPU_INT_EN2 … #define regUVD_VCPU_INT_EN2_BASE_IDX … #define regUVD_SUVD_CGC_STATUS2 … #define regUVD_SUVD_CGC_STATUS2_BASE_IDX … #define regUVD_SUVD_INT_STATUS2 … #define regUVD_SUVD_INT_STATUS2_BASE_IDX … #define regUVD_SUVD_INT_EN2 … #define regUVD_SUVD_INT_EN2_BASE_IDX … #define regUVD_SUVD_INT_ACK2 … #define regUVD_SUVD_INT_ACK2_BASE_IDX … #define regUVD_STATUS … #define regUVD_STATUS_BASE_IDX … #define regUVD_ENC_PIPE_BUSY … #define regUVD_ENC_PIPE_BUSY_BASE_IDX … #define regUVD_FW_POWER_STATUS … #define regUVD_FW_POWER_STATUS_BASE_IDX … #define regUVD_CNTL … #define regUVD_CNTL_BASE_IDX … #define regUVD_SOFT_RESET … #define regUVD_SOFT_RESET_BASE_IDX … #define regUVD_SOFT_RESET2 … #define regUVD_SOFT_RESET2_BASE_IDX … #define regUVD_MMSCH_SOFT_RESET … #define regUVD_MMSCH_SOFT_RESET_BASE_IDX … #define regUVD_WIG_CTRL … #define regUVD_WIG_CTRL_BASE_IDX … #define regUVD_CGC_STATUS … #define regUVD_CGC_STATUS_BASE_IDX … #define regUVD_CGC_UDEC_STATUS … #define regUVD_CGC_UDEC_STATUS_BASE_IDX … #define regUVD_SUVD_CGC_STATUS … #define regUVD_SUVD_CGC_STATUS_BASE_IDX … #define regUVD_GPCOM_VCPU_CMD … #define regUVD_GPCOM_VCPU_CMD_BASE_IDX … // addressBlock: aid_uvd0_ecpudec // base address: 0x1fe00 #define regUVD_VCPU_CACHE_OFFSET0 … #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE0 … #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET1 … #define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE1 … #define regUVD_VCPU_CACHE_SIZE1_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET2 … #define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE2 … #define regUVD_VCPU_CACHE_SIZE2_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET3 … #define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE3 … #define regUVD_VCPU_CACHE_SIZE3_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET4 … #define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE4 … #define regUVD_VCPU_CACHE_SIZE4_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET5 … #define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE5 … #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET6 … #define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE6 … #define regUVD_VCPU_CACHE_SIZE6_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET7 … #define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE7 … #define regUVD_VCPU_CACHE_SIZE7_BASE_IDX … #define regUVD_VCPU_CACHE_OFFSET8 … #define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX … #define regUVD_VCPU_CACHE_SIZE8 … #define regUVD_VCPU_CACHE_SIZE8_BASE_IDX … #define regUVD_VCPU_NONCACHE_OFFSET0 … #define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX … #define regUVD_VCPU_NONCACHE_SIZE0 … #define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX … #define regUVD_VCPU_NONCACHE_OFFSET1 … #define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX … #define regUVD_VCPU_NONCACHE_SIZE1 … #define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX … #define regUVD_VCPU_CNTL … #define regUVD_VCPU_CNTL_BASE_IDX … #define regUVD_VCPU_PRID … #define regUVD_VCPU_PRID_BASE_IDX … #define regUVD_VCPU_TRCE … #define regUVD_VCPU_TRCE_BASE_IDX … #define regUVD_VCPU_TRCE_RD … #define regUVD_VCPU_TRCE_RD_BASE_IDX … #define regUVD_VCPU_IND_INDEX … #define regUVD_VCPU_IND_INDEX_BASE_IDX … #define regUVD_VCPU_IND_DATA … #define regUVD_VCPU_IND_DATA_BASE_IDX … // addressBlock: aid_uvd0_uvd_mpcdec // base address: 0x1ff30 #define regUVD_MP_SWAP_CNTL … #define regUVD_MP_SWAP_CNTL_BASE_IDX … #define regUVD_MP_SWAP_CNTL2 … #define regUVD_MP_SWAP_CNTL2_BASE_IDX … #define regUVD_MPC_LUMA_SRCH … #define regUVD_MPC_LUMA_SRCH_BASE_IDX … #define regUVD_MPC_LUMA_HIT … #define regUVD_MPC_LUMA_HIT_BASE_IDX … #define regUVD_MPC_LUMA_HITPEND … #define regUVD_MPC_LUMA_HITPEND_BASE_IDX … #define regUVD_MPC_CHROMA_SRCH … #define regUVD_MPC_CHROMA_SRCH_BASE_IDX … #define regUVD_MPC_CHROMA_HIT … #define regUVD_MPC_CHROMA_HIT_BASE_IDX … #define regUVD_MPC_CHROMA_HITPEND … #define regUVD_MPC_CHROMA_HITPEND_BASE_IDX … #define regUVD_MPC_CNTL … #define regUVD_MPC_CNTL_BASE_IDX … #define regUVD_MPC_PITCH … #define regUVD_MPC_PITCH_BASE_IDX … #define regUVD_MPC_SET_MUXA0 … #define regUVD_MPC_SET_MUXA0_BASE_IDX … #define regUVD_MPC_SET_MUXA1 … #define regUVD_MPC_SET_MUXA1_BASE_IDX … #define regUVD_MPC_SET_MUXB0 … #define regUVD_MPC_SET_MUXB0_BASE_IDX … #define regUVD_MPC_SET_MUXB1 … #define regUVD_MPC_SET_MUXB1_BASE_IDX … #define regUVD_MPC_SET_MUX … #define regUVD_MPC_SET_MUX_BASE_IDX … #define regUVD_MPC_SET_ALU … #define regUVD_MPC_SET_ALU_BASE_IDX … #define regUVD_MPC_PERF0 … #define regUVD_MPC_PERF0_BASE_IDX … #define regUVD_MPC_PERF1 … #define regUVD_MPC_PERF1_BASE_IDX … #define regUVD_MPC_IND_INDEX … #define regUVD_MPC_IND_INDEX_BASE_IDX … #define regUVD_MPC_IND_DATA … #define regUVD_MPC_IND_DATA_BASE_IDX … // addressBlock: aid_uvd0_uvd_rbcdec // base address: 0x1ff90 #define regUVD_RBC_IB_SIZE … #define regUVD_RBC_IB_SIZE_BASE_IDX … #define regUVD_RBC_IB_SIZE_UPDATE … #define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_RBC_RB_CNTL … #define regUVD_RBC_RB_CNTL_BASE_IDX … #define regUVD_RBC_RB_RPTR_ADDR … #define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX … #define regUVD_RBC_VCPU_ACCESS … #define regUVD_RBC_VCPU_ACCESS_BASE_IDX … #define regUVD_FW_SEMAPHORE_CNTL … #define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX … #define regUVD_RBC_READ_REQ_URGENT_CNTL … #define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX … #define regUVD_RBC_RB_WPTR_CNTL … #define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX … #define regUVD_RBC_WPTR_STATUS … #define regUVD_RBC_WPTR_STATUS_BASE_IDX … #define regUVD_RBC_WPTR_POLL_CNTL … #define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX … #define regUVD_RBC_WPTR_POLL_ADDR … #define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX … #define regUVD_SEMA_CMD … #define regUVD_SEMA_CMD_BASE_IDX … #define regUVD_SEMA_ADDR_LOW … #define regUVD_SEMA_ADDR_LOW_BASE_IDX … #define regUVD_SEMA_ADDR_HIGH … #define regUVD_SEMA_ADDR_HIGH_BASE_IDX … #define regUVD_ENGINE_CNTL … #define regUVD_ENGINE_CNTL_BASE_IDX … #define regUVD_SEMA_TIMEOUT_STATUS … #define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX … #define regUVD_SEMA_CNTL … #define regUVD_SEMA_CNTL_BASE_IDX … #define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … #define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL … #define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX … #define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL … #define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX … #define regUVD_JOB_START … #define regUVD_JOB_START_BASE_IDX … #define regUVD_RBC_BUF_STATUS … #define regUVD_RBC_BUF_STATUS_BASE_IDX … #define regUVD_RBC_SWAP_CNTL … #define regUVD_RBC_SWAP_CNTL_BASE_IDX … // addressBlock: aid_uvd0_lmi_adpdec // base address: 0x20090 #define regUVD_LMI_RE_64BIT_BAR_LOW … #define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_RE_64BIT_BAR_HIGH … #define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_IT_64BIT_BAR_LOW … #define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_IT_64BIT_BAR_HIGH … #define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MP_64BIT_BAR_LOW … #define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MP_64BIT_BAR_HIGH … #define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_CM_64BIT_BAR_LOW … #define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_CM_64BIT_BAR_HIGH … #define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_DB_64BIT_BAR_LOW … #define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_DB_64BIT_BAR_HIGH … #define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_DBW_64BIT_BAR_LOW … #define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_DBW_64BIT_BAR_HIGH … #define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_IDCT_64BIT_BAR_LOW … #define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_IDCT_64BIT_BAR_HIGH … #define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW … #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH … #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW … #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH … #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW … #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH … #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MPC_64BIT_BAR_LOW … #define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MPC_64BIT_BAR_HIGH … #define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW … #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH … #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW … #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH … #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_LBSI_64BIT_BAR_LOW … #define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_LBSI_64BIT_BAR_HIGH … #define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_CENC_64BIT_BAR_LOW … #define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_CENC_64BIT_BAR_HIGH … #define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_SRE_64BIT_BAR_LOW … #define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_SRE_64BIT_BAR_HIGH … #define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW … #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_REF_64BIT_BAR_LOW … #define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW … #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW … #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW … #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW … #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH … #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW … #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW … #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_SPH_64BIT_BAR_HIGH … #define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_ADP_ATOMIC_CONFIG … #define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX … #define regUVD_LMI_ARB_CTRL2 … #define regUVD_LMI_ARB_CTRL2_BASE_IDX … #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI … #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX … #define regUVD_LMI_VCPU_NC_VMIDS_MULTI … #define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX … #define regUVD_LMI_LAT_CTRL … #define regUVD_LMI_LAT_CTRL_BASE_IDX … #define regUVD_LMI_LAT_CNTR … #define regUVD_LMI_LAT_CNTR_BASE_IDX … #define regUVD_LMI_AVG_LAT_CNTR … #define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX … #define regUVD_LMI_SPH … #define regUVD_LMI_SPH_BASE_IDX … #define regUVD_LMI_VCPU_CACHE_VMID … #define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX … #define regUVD_LMI_CTRL2 … #define regUVD_LMI_CTRL2_BASE_IDX … #define regUVD_LMI_URGENT_CTRL … #define regUVD_LMI_URGENT_CTRL_BASE_IDX … #define regUVD_LMI_CTRL … #define regUVD_LMI_CTRL_BASE_IDX … #define regUVD_LMI_STATUS … #define regUVD_LMI_STATUS_BASE_IDX … #define regUVD_LMI_PERFMON_CTRL … #define regUVD_LMI_PERFMON_CTRL_BASE_IDX … #define regUVD_LMI_PERFMON_COUNT_LO … #define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX … #define regUVD_LMI_PERFMON_COUNT_HI … #define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX … #define regUVD_LMI_ADP_SWAP_CNTL … #define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX … #define regUVD_LMI_RBC_RB_VMID … #define regUVD_LMI_RBC_RB_VMID_BASE_IDX … #define regUVD_LMI_RBC_IB_VMID … #define regUVD_LMI_RBC_IB_VMID_BASE_IDX … #define regUVD_LMI_MC_CREDITS … #define regUVD_LMI_MC_CREDITS_BASE_IDX … #define regUVD_LMI_ADP_IND_INDEX … #define regUVD_LMI_ADP_IND_INDEX_BASE_IDX … #define regUVD_LMI_ADP_IND_DATA … #define regUVD_LMI_ADP_IND_DATA_BASE_IDX … #define regUVD_LMI_ADP_PF_EN … #define regUVD_LMI_ADP_PF_EN_BASE_IDX … #define regUVD_LMI_PREF_CTRL … #define regUVD_LMI_PREF_CTRL_BASE_IDX … #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW … #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH … #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX … #define regVCN_RAS_CNTL … #define regVCN_RAS_CNTL_BASE_IDX … // addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec // base address: 0x20f00 #define regUVD_JPEG_CNTL … #define regUVD_JPEG_CNTL_BASE_IDX … #define regUVD_JPEG_RB_BASE … #define regUVD_JPEG_RB_BASE_BASE_IDX … #define regUVD_JPEG_RB_WPTR … #define regUVD_JPEG_RB_WPTR_BASE_IDX … #define regUVD_JPEG_RB_RPTR … #define regUVD_JPEG_RB_RPTR_BASE_IDX … #define regUVD_JPEG_RB_SIZE … #define regUVD_JPEG_RB_SIZE_BASE_IDX … #define regUVD_JPEG_DEC_CNT … #define regUVD_JPEG_DEC_CNT_BASE_IDX … #define regUVD_JPEG_SPS_INFO … #define regUVD_JPEG_SPS_INFO_BASE_IDX … #define regUVD_JPEG_SPS1_INFO … #define regUVD_JPEG_SPS1_INFO_BASE_IDX … #define regUVD_JPEG_RE_TIMER … #define regUVD_JPEG_RE_TIMER_BASE_IDX … #define regUVD_JPEG_DEC_SCRATCH0 … #define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX … #define regUVD_JPEG_INT_EN … #define regUVD_JPEG_INT_EN_BASE_IDX … #define regUVD_JPEG_INT_STAT … #define regUVD_JPEG_INT_STAT_BASE_IDX … #define regUVD_JPEG_TIER_CNTL0 … #define regUVD_JPEG_TIER_CNTL0_BASE_IDX … #define regUVD_JPEG_TIER_CNTL1 … #define regUVD_JPEG_TIER_CNTL1_BASE_IDX … #define regUVD_JPEG_TIER_CNTL2 … #define regUVD_JPEG_TIER_CNTL2_BASE_IDX … #define regUVD_JPEG_TIER_STATUS … #define regUVD_JPEG_TIER_STATUS_BASE_IDX … // addressBlock: aid_uvd0_uvd_jpeg_sclk0_jpegnpsclkdec // base address: 0x21000 #define regUVD_JPEG_OUTBUF_CNTL … #define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX … #define regUVD_JPEG_OUTBUF_WPTR … #define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX … #define regUVD_JPEG_OUTBUF_RPTR … #define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX … #define regUVD_JPEG_PITCH … #define regUVD_JPEG_PITCH_BASE_IDX … #define regUVD_JPEG_UV_PITCH … #define regUVD_JPEG_UV_PITCH_BASE_IDX … #define regJPEG_DEC_Y_GFX8_TILING_SURFACE … #define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX … #define regJPEG_DEC_UV_GFX8_TILING_SURFACE … #define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX … #define regJPEG_DEC_GFX8_ADDR_CONFIG … #define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX … #define regJPEG_DEC_Y_GFX10_TILING_SURFACE … #define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX … #define regJPEG_DEC_UV_GFX10_TILING_SURFACE … #define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX … #define regJPEG_DEC_GFX10_ADDR_CONFIG … #define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX … #define regJPEG_DEC_ADDR_MODE … #define regJPEG_DEC_ADDR_MODE_BASE_IDX … #define regUVD_JPEG_OUTPUT_XY … #define regUVD_JPEG_OUTPUT_XY_BASE_IDX … #define regUVD_JPEG_GPCOM_CMD … #define regUVD_JPEG_GPCOM_CMD_BASE_IDX … #define regUVD_JPEG_GPCOM_DATA0 … #define regUVD_JPEG_GPCOM_DATA0_BASE_IDX … #define regUVD_JPEG_GPCOM_DATA1 … #define regUVD_JPEG_GPCOM_DATA1_BASE_IDX … #define regUVD_JPEG_SCRATCH1 … #define regUVD_JPEG_SCRATCH1_BASE_IDX … #define regUVD_JPEG_DEC_SOFT_RST … #define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc0_uvd_jrbc_dec // base address: 0x21100 #define regUVD_JRBC0_UVD_JRBC_RB_WPTR … #define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_CNTL … #define regUVD_JRBC0_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_IB_SIZE … #define regUVD_JRBC0_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC0_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_STATUS … #define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_RPTR … #define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_RB_SIZE … #define regUVD_JRBC0_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC0_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC0_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi0_uvd_jmi_dec // base address: 0x21180 #define regUVD_JMI0_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI0_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_CTRL … #define regUVD_JMI0_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_CTRL … #define regUVD_JMI0_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI0_JPEG_LMI_DROP … #define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI0_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI0_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_VMID … #define regUVD_JMI0_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI0_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI0_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi_common_dec // base address: 0x21300 #define regUVD_JADP_MCIF_URGENT_CTRL … #define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX … #define regUVD_JMI_URGENT_CTRL … #define regUVD_JMI_URGENT_CTRL_BASE_IDX … #define regUVD_JMI_CTRL … #define regUVD_JMI_CTRL_BASE_IDX … #define regJPEG_MEMCHECK_CLAMPING_CNTL … #define regJPEG_MEMCHECK_CLAMPING_CNTL_BASE_IDX … #define regJPEG_MEMCHECK_SAFE_ADDR … #define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX … #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT … #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX … #define regUVD_JMI_LAT_CTRL … #define regUVD_JMI_LAT_CTRL_BASE_IDX … #define regUVD_JMI_LAT_CNTR … #define regUVD_JMI_LAT_CNTR_BASE_IDX … #define regUVD_JMI_AVG_LAT_CNTR … #define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX … #define regUVD_JMI_PERFMON_CTRL … #define regUVD_JMI_PERFMON_CTRL_BASE_IDX … #define regUVD_JMI_PERFMON_COUNT_LO … #define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX … #define regUVD_JMI_PERFMON_COUNT_HI … #define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX … #define regUVD_JMI_CLEAN_STATUS … #define regUVD_JMI_CLEAN_STATUS_BASE_IDX … #define regUVD_JMI_CNTL … #define regUVD_JMI_CNTL_BASE_IDX … // addressBlock: aid_uvd0_uvd_jpeg_common_dec // base address: 0x21400 #define regJPEG_SOFT_RESET_STATUS … #define regJPEG_SOFT_RESET_STATUS_BASE_IDX … #define regJPEG_SYS_INT_EN … #define regJPEG_SYS_INT_EN_BASE_IDX … #define regJPEG_SYS_INT_EN1 … #define regJPEG_SYS_INT_EN1_BASE_IDX … #define regJPEG_SYS_INT_STATUS … #define regJPEG_SYS_INT_STATUS_BASE_IDX … #define regJPEG_SYS_INT_STATUS1 … #define regJPEG_SYS_INT_STATUS1_BASE_IDX … #define regJPEG_SYS_INT_ACK … #define regJPEG_SYS_INT_ACK_BASE_IDX … #define regJPEG_SYS_INT_ACK1 … #define regJPEG_SYS_INT_ACK1_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_EN … #define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_EN1 … #define regJPEG_MEMCHECK_SYS_INT_EN1_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_STAT … #define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_STAT1 … #define regJPEG_MEMCHECK_SYS_INT_STAT1_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_STAT2 … #define regJPEG_MEMCHECK_SYS_INT_STAT2_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_ACK … #define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_ACK1 … #define regJPEG_MEMCHECK_SYS_INT_ACK1_BASE_IDX … #define regJPEG_MEMCHECK_SYS_INT_ACK2 … #define regJPEG_MEMCHECK_SYS_INT_ACK2_BASE_IDX … #define regJPEG_MASTINT_EN … #define regJPEG_MASTINT_EN_BASE_IDX … #define regJPEG_IH_CTRL … #define regJPEG_IH_CTRL_BASE_IDX … #define regJRBBM_ARB_CTRL … #define regJRBBM_ARB_CTRL_BASE_IDX … // addressBlock: aid_uvd0_uvd_jpeg_common_sclk_dec // base address: 0x21480 #define regJPEG_CGC_GATE … #define regJPEG_CGC_GATE_BASE_IDX … #define regJPEG_CGC_CTRL … #define regJPEG_CGC_CTRL_BASE_IDX … #define regJPEG_CGC_STATUS … #define regJPEG_CGC_STATUS_BASE_IDX … #define regJPEG_COMN_CGC_MEM_CTRL … #define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX … #define regJPEG_DEC_CGC_MEM_CTRL … #define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX … #define regJPEG_ENC_CGC_MEM_CTRL … #define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX … #define regJPEG_PERF_BANK_CONF … #define regJPEG_PERF_BANK_CONF_BASE_IDX … #define regJPEG_PERF_BANK_EVENT_SEL … #define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX … #define regJPEG_PERF_BANK_COUNT0 … #define regJPEG_PERF_BANK_COUNT0_BASE_IDX … #define regJPEG_PERF_BANK_COUNT1 … #define regJPEG_PERF_BANK_COUNT1_BASE_IDX … #define regJPEG_PERF_BANK_COUNT2 … #define regJPEG_PERF_BANK_COUNT2_BASE_IDX … #define regJPEG_PERF_BANK_COUNT3 … #define regJPEG_PERF_BANK_COUNT3_BASE_IDX … // addressBlock: aid_uvd0_uvd_pg_dec // base address: 0x1f800 #define regUVD_PGFSM_CONFIG … #define regUVD_PGFSM_CONFIG_BASE_IDX … #define regUVD_PGFSM_STATUS … #define regUVD_PGFSM_STATUS_BASE_IDX … #define regUVD_POWER_STATUS … #define regUVD_POWER_STATUS_BASE_IDX … #define regUVD_JPEG_POWER_STATUS … #define regUVD_JPEG_POWER_STATUS_BASE_IDX … #define regUVD_MC_DJPEG_RD_SPACE … #define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX … #define regUVD_MC_DJPEG_WR_SPACE … #define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX … #define regUVD_MC_EJPEG_RD_SPACE … #define regUVD_MC_EJPEG_RD_SPACE_BASE_IDX … #define regUVD_MC_EJPEG_WR_SPACE … #define regUVD_MC_EJPEG_WR_SPACE_BASE_IDX … #define regUVD_PG_IND_INDEX … #define regUVD_PG_IND_INDEX_BASE_IDX … #define regUVD_PG_IND_DATA … #define regUVD_PG_IND_DATA_BASE_IDX … #define regCC_UVD_HARVESTING … #define regCC_UVD_HARVESTING_BASE_IDX … #define regUVD_DPG_LMA_CTL … #define regUVD_DPG_LMA_CTL_BASE_IDX … #define regUVD_DPG_LMA_DATA … #define regUVD_DPG_LMA_DATA_BASE_IDX … #define regUVD_DPG_LMA_MASK … #define regUVD_DPG_LMA_MASK_BASE_IDX … #define regUVD_DPG_PAUSE … #define regUVD_DPG_PAUSE_BASE_IDX … #define regUVD_SCRATCH1 … #define regUVD_SCRATCH1_BASE_IDX … #define regUVD_SCRATCH2 … #define regUVD_SCRATCH2_BASE_IDX … #define regUVD_SCRATCH3 … #define regUVD_SCRATCH3_BASE_IDX … #define regUVD_SCRATCH4 … #define regUVD_SCRATCH4_BASE_IDX … #define regUVD_SCRATCH5 … #define regUVD_SCRATCH5_BASE_IDX … #define regUVD_SCRATCH6 … #define regUVD_SCRATCH6_BASE_IDX … #define regUVD_SCRATCH7 … #define regUVD_SCRATCH7_BASE_IDX … #define regUVD_SCRATCH8 … #define regUVD_SCRATCH8_BASE_IDX … #define regUVD_SCRATCH9 … #define regUVD_SCRATCH9_BASE_IDX … #define regUVD_SCRATCH10 … #define regUVD_SCRATCH10_BASE_IDX … #define regUVD_SCRATCH11 … #define regUVD_SCRATCH11_BASE_IDX … #define regUVD_SCRATCH12 … #define regUVD_SCRATCH12_BASE_IDX … #define regUVD_SCRATCH13 … #define regUVD_SCRATCH13_BASE_IDX … #define regUVD_SCRATCH14 … #define regUVD_SCRATCH14_BASE_IDX … #define regUVD_FREE_COUNTER_REG … #define regUVD_FREE_COUNTER_REG_BASE_IDX … #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_DPG_VCPU_CACHE_OFFSET0 … #define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX … #define regUVD_DPG_LMI_VCPU_CACHE_VMID … #define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX … #define regUVD_REG_FILTER_EN … #define regUVD_REG_FILTER_EN_BASE_IDX … #define regUVD_SECURITY_REG_VIO_REPORT … #define regUVD_SECURITY_REG_VIO_REPORT_BASE_IDX … #define regUVD_FW_VERSION … #define regUVD_FW_VERSION_BASE_IDX … #define regUVD_PF_STATUS … #define regUVD_PF_STATUS_BASE_IDX … #define regUVD_DPG_CLK_EN_VCPU_REPORT … #define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX … #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO … #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX … #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI … #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX … #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO … #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX … #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI … #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX … #define regCC_UVD_VCPU_ERR … #define regCC_UVD_VCPU_ERR_BASE_IDX … #define regCC_UVD_VCPU_ERR_INST_ADDR_LO … #define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX … #define regCC_UVD_VCPU_ERR_INST_ADDR_HI … #define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX … #define regUVD_LMI_MMSCH_NC_SPACE … #define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX … #define regUVD_LMI_ATOMIC_SPACE … #define regUVD_LMI_ATOMIC_SPACE_BASE_IDX … #define regUVD_GFX8_ADDR_CONFIG … #define regUVD_GFX8_ADDR_CONFIG_BASE_IDX … #define regUVD_GFX10_ADDR_CONFIG … #define regUVD_GFX10_ADDR_CONFIG_BASE_IDX … #define regUVD_GPCNT2_CNTL … #define regUVD_GPCNT2_CNTL_BASE_IDX … #define regUVD_GPCNT2_TARGET_LOWER … #define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX … #define regUVD_GPCNT2_STATUS_LOWER … #define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX … #define regUVD_GPCNT2_TARGET_UPPER … #define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX … #define regUVD_GPCNT2_STATUS_UPPER … #define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX … #define regUVD_GPCNT3_CNTL … #define regUVD_GPCNT3_CNTL_BASE_IDX … #define regUVD_GPCNT3_TARGET_LOWER … #define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX … #define regUVD_GPCNT3_STATUS_LOWER … #define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX … #define regUVD_GPCNT3_TARGET_UPPER … #define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX … #define regUVD_GPCNT3_STATUS_UPPER … #define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX … #define regUVD_VCLK_DS_CNTL … #define regUVD_VCLK_DS_CNTL_BASE_IDX … #define regUVD_DCLK_DS_CNTL … #define regUVD_DCLK_DS_CNTL_BASE_IDX … #define regUVD_TSC_LOWER … #define regUVD_TSC_LOWER_BASE_IDX … #define regUVD_TSC_UPPER … #define regUVD_TSC_UPPER_BASE_IDX … #define regVCN_FEATURES … #define regVCN_FEATURES_BASE_IDX … #define regUVD_GPUIOV_STATUS … #define regUVD_GPUIOV_STATUS_BASE_IDX … #define regUVD_RAS_VCPU_VCODEC_STATUS … #define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX … #define regUVD_RAS_MMSCH_FATAL_ERROR … #define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX … #define regUVD_RAS_JPEG0_STATUS … #define regUVD_RAS_JPEG0_STATUS_BASE_IDX … #define regUVD_RAS_JPEG1_STATUS … #define regUVD_RAS_JPEG1_STATUS_BASE_IDX … #define regUVD_RAS_CNTL_PMI_ARB … #define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX … #define regUVD_SCRATCH15 … #define regUVD_SCRATCH15_BASE_IDX … #define regVCN_JPEG_DB_CTRL1 … #define regVCN_JPEG_DB_CTRL1_BASE_IDX … #define regVCN_JPEG_DB_CTRL2 … #define regVCN_JPEG_DB_CTRL2_BASE_IDX … #define regVCN_JPEG_DB_CTRL3 … #define regVCN_JPEG_DB_CTRL3_BASE_IDX … #define regVCN_JPEG_DB_CTRL4 … #define regVCN_JPEG_DB_CTRL4_BASE_IDX … #define regVCN_JPEG_DB_CTRL5 … #define regVCN_JPEG_DB_CTRL5_BASE_IDX … #define regVCN_JPEG_DB_CTRL6 … #define regVCN_JPEG_DB_CTRL6_BASE_IDX … #define regVCN_JPEG_DB_CTRL7 … #define regVCN_JPEG_DB_CTRL7_BASE_IDX … #define regUVD_SCRATCH32 … #define regUVD_SCRATCH32_BASE_IDX … #define regUVD_VERSION … #define regUVD_VERSION_BASE_IDX … #define regVCN_RB_DB_CTRL … #define regVCN_RB_DB_CTRL_BASE_IDX … #define regVCN_JPEG_DB_CTRL … #define regVCN_JPEG_DB_CTRL_BASE_IDX … #define regVCN_RB1_DB_CTRL … #define regVCN_RB1_DB_CTRL_BASE_IDX … #define regVCN_RB2_DB_CTRL … #define regVCN_RB2_DB_CTRL_BASE_IDX … #define regVCN_RB3_DB_CTRL … #define regVCN_RB3_DB_CTRL_BASE_IDX … #define regVCN_RB4_DB_CTRL … #define regVCN_RB4_DB_CTRL_BASE_IDX … #define regVCN_RB_ENABLE … #define regVCN_RB_ENABLE_BASE_IDX … #define regVCN_RB_WPTR_CTRL … #define regVCN_RB_WPTR_CTRL_BASE_IDX … #define regUVD_RB_RPTR … #define regUVD_RB_RPTR_BASE_IDX … #define regUVD_RB_WPTR … #define regUVD_RB_WPTR_BASE_IDX … #define regUVD_RB_RPTR2 … #define regUVD_RB_RPTR2_BASE_IDX … #define regUVD_RB_WPTR2 … #define regUVD_RB_WPTR2_BASE_IDX … #define regUVD_RB_RPTR3 … #define regUVD_RB_RPTR3_BASE_IDX … #define regUVD_RB_WPTR3 … #define regUVD_RB_WPTR3_BASE_IDX … #define regUVD_RB_RPTR4 … #define regUVD_RB_RPTR4_BASE_IDX … #define regUVD_RB_WPTR4 … #define regUVD_RB_WPTR4_BASE_IDX … #define regUVD_OUT_RB_RPTR … #define regUVD_OUT_RB_RPTR_BASE_IDX … #define regUVD_OUT_RB_WPTR … #define regUVD_OUT_RB_WPTR_BASE_IDX … #define regUVD_AUDIO_RB_RPTR … #define regUVD_AUDIO_RB_RPTR_BASE_IDX … #define regUVD_AUDIO_RB_WPTR … #define regUVD_AUDIO_RB_WPTR_BASE_IDX … #define regUVD_RBC_RB_RPTR … #define regUVD_RBC_RB_RPTR_BASE_IDX … #define regUVD_RBC_RB_WPTR … #define regUVD_RBC_RB_WPTR_BASE_IDX … #define regUVD_DPG_LMA_CTL2 … #define regUVD_DPG_LMA_CTL2_BASE_IDX … // addressBlock: aid_uvd0_mmsch_dec // base address: 0x20d00 #define regMMSCH_UCODE_ADDR … #define regMMSCH_UCODE_ADDR_BASE_IDX … #define regMMSCH_UCODE_DATA … #define regMMSCH_UCODE_DATA_BASE_IDX … #define regMMSCH_SRAM_ADDR … #define regMMSCH_SRAM_ADDR_BASE_IDX … #define regMMSCH_SRAM_DATA … #define regMMSCH_SRAM_DATA_BASE_IDX … #define regMMSCH_VF_SRAM_OFFSET … #define regMMSCH_VF_SRAM_OFFSET_BASE_IDX … #define regMMSCH_DB_SRAM_OFFSET … #define regMMSCH_DB_SRAM_OFFSET_BASE_IDX … #define regMMSCH_CTX_SRAM_OFFSET … #define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX … #define regMMSCH_CTL … #define regMMSCH_CTL_BASE_IDX … #define regMMSCH_INTR … #define regMMSCH_INTR_BASE_IDX … #define regMMSCH_INTR_ACK … #define regMMSCH_INTR_ACK_BASE_IDX … #define regMMSCH_INTR_STATUS … #define regMMSCH_INTR_STATUS_BASE_IDX … #define regMMSCH_VF_VMID … #define regMMSCH_VF_VMID_BASE_IDX … #define regMMSCH_VF_CTX_ADDR_LO … #define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX … #define regMMSCH_VF_CTX_ADDR_HI … #define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX … #define regMMSCH_VF_CTX_SIZE … #define regMMSCH_VF_CTX_SIZE_BASE_IDX … #define regMMSCH_VF_GPCOM_ADDR_LO … #define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX … #define regMMSCH_VF_GPCOM_ADDR_HI … #define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX … #define regMMSCH_VF_GPCOM_SIZE … #define regMMSCH_VF_GPCOM_SIZE_BASE_IDX … #define regMMSCH_VF_MAILBOX_HOST … #define regMMSCH_VF_MAILBOX_HOST_BASE_IDX … #define regMMSCH_VF_MAILBOX_RESP … #define regMMSCH_VF_MAILBOX_RESP_BASE_IDX … #define regMMSCH_VF_MAILBOX_0 … #define regMMSCH_VF_MAILBOX_0_BASE_IDX … #define regMMSCH_VF_MAILBOX_0_RESP … #define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX … #define regMMSCH_VF_MAILBOX_1 … #define regMMSCH_VF_MAILBOX_1_BASE_IDX … #define regMMSCH_VF_MAILBOX_1_RESP … #define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX … #define regMMSCH_CNTL … #define regMMSCH_CNTL_BASE_IDX … #define regMMSCH_NONCACHE_OFFSET0 … #define regMMSCH_NONCACHE_OFFSET0_BASE_IDX … #define regMMSCH_NONCACHE_SIZE0 … #define regMMSCH_NONCACHE_SIZE0_BASE_IDX … #define regMMSCH_NONCACHE_OFFSET1 … #define regMMSCH_NONCACHE_OFFSET1_BASE_IDX … #define regMMSCH_NONCACHE_SIZE1 … #define regMMSCH_NONCACHE_SIZE1_BASE_IDX … #define regMMSCH_PROC_STATE1 … #define regMMSCH_PROC_STATE1_BASE_IDX … #define regMMSCH_LAST_MC_ADDR … #define regMMSCH_LAST_MC_ADDR_BASE_IDX … #define regMMSCH_LAST_MEM_ACCESS_HI … #define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX … #define regMMSCH_LAST_MEM_ACCESS_LO … #define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX … #define regMMSCH_IOV_ACTIVE_FCN_ID … #define regMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX … #define regMMSCH_SCRATCH_0 … #define regMMSCH_SCRATCH_0_BASE_IDX … #define regMMSCH_SCRATCH_1 … #define regMMSCH_SCRATCH_1_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_0 … #define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX … #define regMMSCH_GPUIOV_CMD_CONTROL_0 … #define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_0 … #define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCNS_0 … #define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX … #define regMMSCH_GPUIOV_DW6_0 … #define regMMSCH_GPUIOV_DW6_0_BASE_IDX … #define regMMSCH_GPUIOV_DW7_0 … #define regMMSCH_GPUIOV_DW7_0_BASE_IDX … #define regMMSCH_GPUIOV_DW8_0 … #define regMMSCH_GPUIOV_DW8_0_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_1 … #define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX … #define regMMSCH_GPUIOV_CMD_CONTROL_1 … #define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_1 … #define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCNS_1 … #define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX … #define regMMSCH_GPUIOV_DW6_1 … #define regMMSCH_GPUIOV_DW6_1_BASE_IDX … #define regMMSCH_GPUIOV_DW7_1 … #define regMMSCH_GPUIOV_DW7_1_BASE_IDX … #define regMMSCH_GPUIOV_DW8_1 … #define regMMSCH_GPUIOV_DW8_1_BASE_IDX … #define regMMSCH_GPUIOV_CNTXT … #define regMMSCH_GPUIOV_CNTXT_BASE_IDX … #define regMMSCH_SCRATCH_2 … #define regMMSCH_SCRATCH_2_BASE_IDX … #define regMMSCH_SCRATCH_3 … #define regMMSCH_SCRATCH_3_BASE_IDX … #define regMMSCH_SCRATCH_4 … #define regMMSCH_SCRATCH_4_BASE_IDX … #define regMMSCH_SCRATCH_5 … #define regMMSCH_SCRATCH_5_BASE_IDX … #define regMMSCH_SCRATCH_6 … #define regMMSCH_SCRATCH_6_BASE_IDX … #define regMMSCH_SCRATCH_7 … #define regMMSCH_SCRATCH_7_BASE_IDX … #define regMMSCH_VFID_FIFO_HEAD_0 … #define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX … #define regMMSCH_VFID_FIFO_TAIL_0 … #define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX … #define regMMSCH_VFID_FIFO_HEAD_1 … #define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX … #define regMMSCH_VFID_FIFO_TAIL_1 … #define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX … #define regMMSCH_NACK_STATUS … #define regMMSCH_NACK_STATUS_BASE_IDX … #define regMMSCH_VF_MAILBOX0_DATA … #define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX … #define regMMSCH_VF_MAILBOX1_DATA … #define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_IP_0 … #define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_IP_1 … #define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX … #define regMMSCH_GPUIOV_CNTXT_IP … #define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_2 … #define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX … #define regMMSCH_GPUIOV_CMD_CONTROL_2 … #define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_2 … #define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 … #define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCNS_2 … #define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX … #define regMMSCH_GPUIOV_DW6_2 … #define regMMSCH_GPUIOV_DW6_2_BASE_IDX … #define regMMSCH_GPUIOV_DW7_2 … #define regMMSCH_GPUIOV_DW7_2_BASE_IDX … #define regMMSCH_GPUIOV_DW8_2 … #define regMMSCH_GPUIOV_DW8_2_BASE_IDX … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 … #define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX … #define regMMSCH_GPUIOV_CMD_STATUS_IP_2 … #define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 … #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX … #define regMMSCH_VFID_FIFO_HEAD_2 … #define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX … #define regMMSCH_VFID_FIFO_TAIL_2 … #define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX … #define regMMSCH_VM_BUSY_STATUS_0 … #define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX … #define regMMSCH_VM_BUSY_STATUS_1 … #define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX … #define regMMSCH_VM_BUSY_STATUS_2 … #define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX … // addressBlock: aid_uvd0_slmi_adpdec // base address: 0x21c00 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW … #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX … #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH … #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_LMI_MMSCH_NC_VMID … #define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX … #define regUVD_LMI_MMSCH_CTRL … #define regUVD_LMI_MMSCH_CTRL_BASE_IDX … #define regUVD_MMSCH_LMI_STATUS … #define regUVD_MMSCH_LMI_STATUS_BASE_IDX … #define regVCN_RAS_CNTL_MMSCH … #define regVCN_RAS_CNTL_MMSCH_BASE_IDX … // addressBlock: aid_uvd0_vcn_edcc_dec // base address: 0x21d20 #define regVCN_UE_ERR_STATUS_LO_VIDD … #define regVCN_UE_ERR_STATUS_LO_VIDD_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_VIDD … #define regVCN_UE_ERR_STATUS_HI_VIDD_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_VIDV … #define regVCN_UE_ERR_STATUS_LO_VIDV_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_VIDV … #define regVCN_UE_ERR_STATUS_HI_VIDV_BASE_IDX … #define regVCN_CE_ERR_STATUS_LO_MMSCHD … #define regVCN_CE_ERR_STATUS_LO_MMSCHD_BASE_IDX … #define regVCN_CE_ERR_STATUS_HI_MMSCHD … #define regVCN_CE_ERR_STATUS_HI_MMSCHD_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG0S … #define regVCN_UE_ERR_STATUS_LO_JPEG0S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG0S … #define regVCN_UE_ERR_STATUS_HI_JPEG0S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG0D … #define regVCN_UE_ERR_STATUS_LO_JPEG0D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG0D … #define regVCN_UE_ERR_STATUS_HI_JPEG0D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG1S … #define regVCN_UE_ERR_STATUS_LO_JPEG1S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG1S … #define regVCN_UE_ERR_STATUS_HI_JPEG1S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG1D … #define regVCN_UE_ERR_STATUS_LO_JPEG1D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG1D … #define regVCN_UE_ERR_STATUS_HI_JPEG1D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG2S … #define regVCN_UE_ERR_STATUS_LO_JPEG2S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG2S … #define regVCN_UE_ERR_STATUS_HI_JPEG2S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG2D … #define regVCN_UE_ERR_STATUS_LO_JPEG2D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG2D … #define regVCN_UE_ERR_STATUS_HI_JPEG2D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG3S … #define regVCN_UE_ERR_STATUS_LO_JPEG3S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG3S … #define regVCN_UE_ERR_STATUS_HI_JPEG3S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG3D … #define regVCN_UE_ERR_STATUS_LO_JPEG3D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG3D … #define regVCN_UE_ERR_STATUS_HI_JPEG3D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG4S … #define regVCN_UE_ERR_STATUS_LO_JPEG4S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG4S … #define regVCN_UE_ERR_STATUS_HI_JPEG4S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG4D … #define regVCN_UE_ERR_STATUS_LO_JPEG4D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG4D … #define regVCN_UE_ERR_STATUS_HI_JPEG4D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG5S … #define regVCN_UE_ERR_STATUS_LO_JPEG5S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG5S … #define regVCN_UE_ERR_STATUS_HI_JPEG5S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG5D … #define regVCN_UE_ERR_STATUS_LO_JPEG5D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG5D … #define regVCN_UE_ERR_STATUS_HI_JPEG5D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG6S … #define regVCN_UE_ERR_STATUS_LO_JPEG6S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG6S … #define regVCN_UE_ERR_STATUS_HI_JPEG6S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG6D … #define regVCN_UE_ERR_STATUS_LO_JPEG6D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG6D … #define regVCN_UE_ERR_STATUS_HI_JPEG6D_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG7S … #define regVCN_UE_ERR_STATUS_LO_JPEG7S_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG7S … #define regVCN_UE_ERR_STATUS_HI_JPEG7S_BASE_IDX … #define regVCN_UE_ERR_STATUS_LO_JPEG7D … #define regVCN_UE_ERR_STATUS_LO_JPEG7D_BASE_IDX … #define regVCN_UE_ERR_STATUS_HI_JPEG7D … #define regVCN_UE_ERR_STATUS_HI_JPEG7D_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc1_uvd_jrbc_dec // base address: 0x1e000 #define regUVD_JRBC1_UVD_JRBC_RB_WPTR … #define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_CNTL … #define regUVD_JRBC1_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_IB_SIZE … #define regUVD_JRBC1_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC1_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_STATUS … #define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_RPTR … #define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_RB_SIZE … #define regUVD_JRBC1_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC1_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC1_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc2_uvd_jrbc_dec // base address: 0x1e100 #define regUVD_JRBC2_UVD_JRBC_RB_WPTR … #define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_CNTL … #define regUVD_JRBC2_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_IB_SIZE … #define regUVD_JRBC2_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC2_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_STATUS … #define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_RPTR … #define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_RB_SIZE … #define regUVD_JRBC2_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC2_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC2_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc3_uvd_jrbc_dec // base address: 0x1e200 #define regUVD_JRBC3_UVD_JRBC_RB_WPTR … #define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_CNTL … #define regUVD_JRBC3_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_IB_SIZE … #define regUVD_JRBC3_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC3_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_STATUS … #define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_RPTR … #define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_RB_SIZE … #define regUVD_JRBC3_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC3_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC3_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc4_uvd_jrbc_dec // base address: 0x1e300 #define regUVD_JRBC4_UVD_JRBC_RB_WPTR … #define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_CNTL … #define regUVD_JRBC4_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_IB_SIZE … #define regUVD_JRBC4_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC4_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC4_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC4_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_STATUS … #define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_RPTR … #define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC4_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC4_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC4_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_RB_SIZE … #define regUVD_JRBC4_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC4_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC4_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc5_uvd_jrbc_dec // base address: 0x1e400 #define regUVD_JRBC5_UVD_JRBC_RB_WPTR … #define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_CNTL … #define regUVD_JRBC5_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_IB_SIZE … #define regUVD_JRBC5_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC5_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC5_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC5_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_STATUS … #define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_RPTR … #define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC5_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC5_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC5_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_RB_SIZE … #define regUVD_JRBC5_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC5_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC5_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc6_uvd_jrbc_dec // base address: 0x1e500 #define regUVD_JRBC6_UVD_JRBC_RB_WPTR … #define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_CNTL … #define regUVD_JRBC6_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_IB_SIZE … #define regUVD_JRBC6_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC6_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC6_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC6_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_STATUS … #define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_RPTR … #define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC6_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC6_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC6_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_RB_SIZE … #define regUVD_JRBC6_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC6_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC6_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jrbc7_uvd_jrbc_dec // base address: 0x1e600 #define regUVD_JRBC7_UVD_JRBC_RB_WPTR … #define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_CNTL … #define regUVD_JRBC7_UVD_JRBC_RB_CNTL_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_IB_SIZE … #define regUVD_JRBC7_UVD_JRBC_IB_SIZE_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_URGENT_CNTL … #define regUVD_JRBC7_UVD_JRBC_URGENT_CNTL_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_REF_DATA … #define regUVD_JRBC7_UVD_JRBC_RB_REF_DATA_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER … #define regUVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_SOFT_RESET … #define regUVD_JRBC7_UVD_JRBC_SOFT_RESET_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_STATUS … #define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_RPTR … #define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_BUF_STATUS … #define regUVD_JRBC7_UVD_JRBC_RB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_IB_BUF_STATUS … #define regUVD_JRBC7_UVD_JRBC_IB_BUF_STATUS_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE … #define regUVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER … #define regUVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_IB_REF_DATA … #define regUVD_JRBC7_UVD_JRBC_IB_REF_DATA_BASE_IDX … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_CMD … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_CMD_BASE_IDX … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0 … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1 … #define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_RB_SIZE … #define regUVD_JRBC7_UVD_JRBC_RB_SIZE_BASE_IDX … #define regUVD_JRBC7_UVD_JRBC_SCRATCH0 … #define regUVD_JRBC7_UVD_JRBC_SCRATCH0_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi1_uvd_jmi_dec // base address: 0x1e080 #define regUVD_JMI1_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI1_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_CTRL … #define regUVD_JMI1_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_CTRL … #define regUVD_JMI1_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI1_JPEG_LMI_DROP … #define regUVD_JMI1_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI1_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI1_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_VMID … #define regUVD_JMI1_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI1_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI1_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi2_uvd_jmi_dec // base address: 0x1e180 #define regUVD_JMI2_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI2_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_CTRL … #define regUVD_JMI2_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_CTRL … #define regUVD_JMI2_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI2_JPEG_LMI_DROP … #define regUVD_JMI2_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI2_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI2_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_VMID … #define regUVD_JMI2_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI2_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI2_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi3_uvd_jmi_dec // base address: 0x1e280 #define regUVD_JMI3_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI3_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_CTRL … #define regUVD_JMI3_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_CTRL … #define regUVD_JMI3_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI3_JPEG_LMI_DROP … #define regUVD_JMI3_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI3_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI3_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_VMID … #define regUVD_JMI3_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI3_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI3_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi4_uvd_jmi_dec // base address: 0x1e380 #define regUVD_JMI4_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI4_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_CTRL … #define regUVD_JMI4_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_CTRL … #define regUVD_JMI4_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI4_JPEG_LMI_DROP … #define regUVD_JMI4_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI4_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI4_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_VMID … #define regUVD_JMI4_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI4_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI4_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi5_uvd_jmi_dec // base address: 0x1e480 #define regUVD_JMI5_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI5_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_CTRL … #define regUVD_JMI5_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_CTRL … #define regUVD_JMI5_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI5_JPEG_LMI_DROP … #define regUVD_JMI5_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI5_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI5_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_VMID … #define regUVD_JMI5_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI5_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI5_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi6_uvd_jmi_dec // base address: 0x1e580 #define regUVD_JMI6_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI6_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_CTRL … #define regUVD_JMI6_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_CTRL … #define regUVD_JMI6_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI6_JPEG_LMI_DROP … #define regUVD_JMI6_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI6_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI6_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_VMID … #define regUVD_JMI6_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI6_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI6_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: aid_uvd0_uvd_jmi7_uvd_jmi_dec // base address: 0x1e680 #define regUVD_JMI7_UVD_JPEG_DEC_PF_CTRL … #define regUVD_JMI7_UVD_JPEG_DEC_PF_CTRL_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_CTRL … #define regUVD_JMI7_UVD_LMI_JRBC_CTRL_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_CTRL … #define regUVD_JMI7_UVD_LMI_JPEG_CTRL_BASE_IDX … #define regUVD_JMI7_JPEG_LMI_DROP … #define regUVD_JMI7_JPEG_LMI_DROP_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_IB_VMID … #define regUVD_JMI7_UVD_LMI_JRBC_IB_VMID_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_RB_VMID … #define regUVD_JMI7_UVD_LMI_JRBC_RB_VMID_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_VMID … #define regUVD_JMI7_UVD_LMI_JPEG_VMID_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID … #define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX … #define regUVD_JMI7_UVD_JMI_DEC_SWAP_CNTL … #define regUVD_JMI7_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX … #define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL … #define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL_BASE_IDX … #define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW … #define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX … #define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH … #define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX … #define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL2 … #define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL2_BASE_IDX … // addressBlock: uvdctxind // base address: 0x0 #define ixUVD_CGC_MEM_CTRL … #define ixUVD_CGC_CTRL2 … #define ixUVD_CGC_MEM_DS_CTRL … #define ixUVD_CGC_MEM_SD_CTRL … #define ixUVD_SW_SCRATCH_00 … #define ixUVD_SW_SCRATCH_01 … #define ixUVD_SW_SCRATCH_02 … #define ixUVD_SW_SCRATCH_03 … #define ixUVD_SW_SCRATCH_04 … #define ixUVD_SW_SCRATCH_05 … #define ixUVD_SW_SCRATCH_06 … #define ixUVD_SW_SCRATCH_07 … #define ixUVD_SW_SCRATCH_08 … #define ixUVD_SW_SCRATCH_09 … #define ixUVD_SW_SCRATCH_10 … #define ixUVD_SW_SCRATCH_11 … #define ixUVD_SW_SCRATCH_12 … #define ixUVD_SW_SCRATCH_13 … #define ixUVD_SW_SCRATCH_14 … #define ixUVD_SW_SCRATCH_15 … #define ixUVD_IH_SEM_CTRL … // addressBlock: lmi_adp_indirect // base address: 0x0 #define ixUVD_LMI_CRC0 … #define ixUVD_LMI_CRC1 … #define ixUVD_LMI_CRC2 … #define ixUVD_LMI_CRC3 … #define ixUVD_LMI_CRC10 … #define ixUVD_LMI_CRC11 … #define ixUVD_LMI_CRC12 … #define ixUVD_LMI_CRC13 … #define ixUVD_LMI_CRC14 … #define ixUVD_LMI_CRC15 … #define ixUVD_LMI_SWAP_CNTL2 … #define ixUVD_MEMCHECK_SYS_INT_EN … #define ixUVD_MEMCHECK_SYS_INT_STAT … #define ixUVD_MEMCHECK_SYS_INT_ACK … #define ixUVD_MEMCHECK_VCPU_INT_EN … #define ixUVD_MEMCHECK_VCPU_INT_STAT … #define ixUVD_MEMCHECK_VCPU_INT_ACK … #define ixUVD_MEMCHECK2_SYS_INT_STAT … #define ixUVD_MEMCHECK2_SYS_INT_ACK … #define ixUVD_MEMCHECK2_VCPU_INT_STAT … #define ixUVD_MEMCHECK2_VCPU_INT_ACK … #endif
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