linux/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "sdma/sdma_4_4_0_offset.h"
#include "sdma/sdma_4_4_0_sh_mask.h"
#include "soc15.h"
#include "amdgpu_ras.h"

#define SDMA1_REG_OFFSET …
#define SDMA2_REG_OFFSET …
#define SDMA3_REG_OFFSET …
#define SDMA4_REG_OFFSET …

/* helper function that allow only use sdma0 register offset
 * to calculate register offset for all the sdma instances */
static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev,
					 uint32_t instance,
					 uint32_t offset)
{ … }

static const struct soc15_ras_field_entry sdma_v4_4_ras_fields[] = …;

static void sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev,
					  uint32_t reg_offset,
					  uint32_t value,
					  uint32_t instance,
					  uint32_t *sec_count)
{ … }

static int sdma_v4_4_query_ras_error_count_by_instance(struct amdgpu_device *adev,
					   uint32_t instance,
					   void *ras_error_status)
{
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
	uint32_t sec_count = 0;
	uint32_t reg_value = 0;
	uint32_t reg_offset = 0;

	reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);
	reg_value = RREG32(reg_offset);
	/* double bit error is not supported */
	if (reg_value)
		sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value,
					      instance, &sec_count);

	reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);
	reg_value = RREG32(reg_offset);
	/* double bit error is not supported */
	if (reg_value)
		sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,
					      instance, &sec_count);

	/*
	 * err_data->ue_count should be initialized to 0
	 * before calling into this function
	 *
	 * SDMA RAS supports single bit uncorrectable error detection.
	 * So, increment uncorrectable error count.
	 */
	err_data->ue_count += sec_count;

	/*
	 * SDMA RAS does not support correctable errors.
	 * Set ce count to 0.
	 */
	err_data->ce_count = 0;

	return 0;
};

static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev)
{ … }

static void sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev,  void *ras_error_status)
{ … }

const struct amdgpu_ras_block_hw_ops sdma_v4_4_ras_hw_ops = …;

struct amdgpu_sdma_ras sdma_v4_4_ras = …;