#include <linux/firmware.h>
#include <drm/drm_drv.h>
#include "amdgpu.h"
#include "amdgpu_vcn.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "vcn_v2_0.h"
#include "mmsch_v1_0.h"
#include "vcn_v2_5.h"
#include "vcn/vcn_2_5_offset.h"
#include "vcn/vcn_2_5_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
#define VCN_VID_SOC_ADDRESS_2_0 …
#define VCN1_VID_SOC_ADDRESS_3_0 …
#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET …
#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET …
#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET …
#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET …
#define mmUVD_NO_OP_INTERNAL_OFFSET …
#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET …
#define mmUVD_SCRATCH9_INTERNAL_OFFSET …
#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET …
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET …
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET …
#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET …
#define VCN25_MAX_HW_INSTANCES_ARCTURUS …
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_5_set_powergating_state(void *handle,
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
static int amdgpu_ih_clientid_vcns[] = …;
static int vcn_v2_5_early_init(void *handle)
{ … }
static int vcn_v2_5_sw_init(void *handle)
{ … }
static int vcn_v2_5_sw_fini(void *handle)
{ … }
static int vcn_v2_5_hw_init(void *handle)
{ … }
static int vcn_v2_5_hw_fini(void *handle)
{ … }
static int vcn_v2_5_suspend(void *handle)
{ … }
static int vcn_v2_5_resume(void *handle)
{ … }
static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
{ … }
static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{ … }
static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
{ … }
static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
uint8_t sram_sel, int inst_idx, uint8_t indirect)
{ … }
static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
{ … }
static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
bool indirect)
{ … }
static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{ … }
static int vcn_v2_5_start(struct amdgpu_device *adev)
{ … }
static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
struct amdgpu_mm_table *table)
{ … }
static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
{ … }
static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
{ … }
static int vcn_v2_5_stop(struct amdgpu_device *adev)
{ … }
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state)
{ … }
static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
{ … }
static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
{ … }
static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
{ … }
static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = …;
static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
{ … }
static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
{ … }
static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
{ … }
static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = …;
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
{ … }
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
{ … }
static bool vcn_v2_5_is_idle(void *handle)
{ … }
static int vcn_v2_5_wait_for_idle(void *handle)
{ … }
static int vcn_v2_5_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{ … }
static int vcn_v2_5_set_powergating_state(void *handle,
enum amd_powergating_state state)
{ … }
static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
enum amdgpu_interrupt_state state)
{ … }
static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned int type,
enum amdgpu_interrupt_state state)
{ … }
static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{ … }
static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = …;
static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = …;
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
{ … }
static const struct amd_ip_funcs vcn_v2_5_ip_funcs = …;
static const struct amd_ip_funcs vcn_v2_6_ip_funcs = …;
const struct amdgpu_ip_block_version vcn_v2_5_ip_block = …;
const struct amdgpu_ip_block_version vcn_v2_6_ip_block = …;
static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
uint32_t instance, uint32_t sub_block)
{ … }
static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
{ … }
const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = …;
static struct amdgpu_vcn_ras vcn_v2_6_ras = …;
static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
{ … }