/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <drm/drm_drv.h> #include "amdgpu.h" #include "amdgpu_vcn.h" #include "amdgpu_pm.h" #include "soc15.h" #include "soc15d.h" #include "vcn_v2_0.h" #include "mmsch_v1_0.h" #include "vcn_v2_5.h" #include "vcn/vcn_2_5_offset.h" #include "vcn/vcn_2_5_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" #define VCN_VID_SOC_ADDRESS_2_0 … #define VCN1_VID_SOC_ADDRESS_3_0 … #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET … #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET … #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET … #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET … #define mmUVD_NO_OP_INTERNAL_OFFSET … #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET … #define mmUVD_SCRATCH9_INTERNAL_OFFSET … #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET … #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET … #define VCN25_MAX_HW_INSTANCES_ARCTURUS … static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v2_5_set_powergating_state(void *handle, enum amd_powergating_state state); static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state); static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); static int amdgpu_ih_clientid_vcns[] = …; /** * vcn_v2_5_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers * Load microcode from filesystem */ static int vcn_v2_5_early_init(void *handle) { … } /** * vcn_v2_5_sw_init - sw init for VCN block * * @handle: amdgpu_device pointer * * Load firmware and sw initialization */ static int vcn_v2_5_sw_init(void *handle) { … } /** * vcn_v2_5_sw_fini - sw fini for VCN block * * @handle: amdgpu_device pointer * * VCN suspend and free up sw allocation */ static int vcn_v2_5_sw_fini(void *handle) { … } /** * vcn_v2_5_hw_init - start and test VCN block * * @handle: amdgpu_device pointer * * Initialize the hardware, boot up the VCPU and do some testing */ static int vcn_v2_5_hw_init(void *handle) { … } /** * vcn_v2_5_hw_fini - stop the hardware block * * @handle: amdgpu_device pointer * * Stop the VCN block, mark ring as not ready any more */ static int vcn_v2_5_hw_fini(void *handle) { … } /** * vcn_v2_5_suspend - suspend VCN block * * @handle: amdgpu_device pointer * * HW fini and suspend VCN block */ static int vcn_v2_5_suspend(void *handle) { … } /** * vcn_v2_5_resume - resume VCN block * * @handle: amdgpu_device pointer * * Resume firmware and hw init VCN block */ static int vcn_v2_5_resume(void *handle) { … } /** * vcn_v2_5_mc_resume - memory controller programming * * @adev: amdgpu_device pointer * * Let the VCN memory controller know it's offsets */ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) { … } static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } /** * vcn_v2_5_disable_clock_gating - disable VCN clock gating * * @adev: amdgpu_device pointer * * Disable clock gating for VCN block */ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) { … } static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, int inst_idx, uint8_t indirect) { … } /** * vcn_v2_5_enable_clock_gating - enable VCN clock gating * * @adev: amdgpu_device pointer * * Enable clock gating for VCN block */ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) { … } static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } static int vcn_v2_5_start(struct amdgpu_device *adev) { … } static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, struct amdgpu_mm_table *table) { … } static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) { … } static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) { … } static int vcn_v2_5_stop(struct amdgpu_device *adev) { … } static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state) { … } /** * vcn_v2_5_dec_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vcn_v2_5_dec_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v2_5_dec_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) { … } static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = …; /** * vcn_v2_5_enc_ring_get_rptr - get enc read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc read pointer */ static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vcn_v2_5_enc_ring_get_wptr - get enc write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc write pointer */ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v2_5_enc_ring_set_wptr - set enc write pointer * * @ring: amdgpu_ring pointer * * Commits the enc write pointer to the hardware */ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) { … } static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = …; static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) { … } static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) { … } static bool vcn_v2_5_is_idle(void *handle) { … } static int vcn_v2_5_wait_for_idle(void *handle) { … } static int vcn_v2_5_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int vcn_v2_5_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int type, enum amdgpu_interrupt_state state) { … } static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = …; static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = …; static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) { … } static const struct amd_ip_funcs vcn_v2_5_ip_funcs = …; static const struct amd_ip_funcs vcn_v2_6_ip_funcs = …; const struct amdgpu_ip_block_version vcn_v2_5_ip_block = …; const struct amdgpu_ip_block_version vcn_v2_6_ip_block = …; static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, uint32_t instance, uint32_t sub_block) { … } static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) { … } const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = …; static struct amdgpu_vcn_ras vcn_v2_6_ras = …; static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) { … }
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