/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_jpeg.h" #include "soc15.h" #include "soc15d.h" #include "vcn_v1_0.h" #include "jpeg_v1_0.h" #include "vcn/vcn_1_0_offset.h" #include "vcn/vcn_1_0_sh_mask.h" static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev); static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring); static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) { … } static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) { … } /** * jpeg_v1_0_decode_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * jpeg_v1_0_decode_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * jpeg_v1_0_decode_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * jpeg_v1_0_decode_ring_insert_start - insert a start command * * @ring: amdgpu_ring pointer * * Write a start command to the ring. */ static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring) { … } /** * jpeg_v1_0_decode_ring_insert_end - insert a end command * * @ring: amdgpu_ring pointer * * Write a end command to the ring. */ static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring) { … } /** * jpeg_v1_0_decode_ring_emit_fence - emit an fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write a fence and a trap command to the ring. */ static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * jpeg_v1_0_decode_ring_emit_ib - execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrieve vmid from * @ib: indirect buffer to execute * @flags: unused * * Write ring commands to execute the indirect buffer. */ static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { … } static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count) { … } static int jpeg_v1_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } /** * jpeg_v1_0_early_init - set function pointers * * @handle: amdgpu_device pointer * * Set ring and irq function pointers */ int jpeg_v1_0_early_init(void *handle) { … } /** * jpeg_v1_0_sw_init - sw init for JPEG block * * @handle: amdgpu_device pointer * */ int jpeg_v1_0_sw_init(void *handle) { … } /** * jpeg_v1_0_sw_fini - sw fini for JPEG block * * @handle: amdgpu_device pointer * * JPEG free up sw allocation */ void jpeg_v1_0_sw_fini(void *handle) { … } /** * jpeg_v1_0_start - start JPEG block * * @adev: amdgpu_device pointer * @mode: SPG or DPG mode * * Setup and start the JPEG block */ void jpeg_v1_0_start(struct amdgpu_device *adev, int mode) { … } static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = …; static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = …; static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev) { … } static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring) { … }