/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_jpeg.h" #include "soc15.h" #include "soc15d.h" #include "jpeg_v4_0_3.h" #include "mmsch_v4_0_3.h" #include "vcn/vcn_4_0_3_offset.h" #include "vcn/vcn_4_0_3_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" #define NORMALIZE_JPEG_REG_OFFSET(offset) … enum jpeg_engin_status { … }; static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); static int jpeg_v4_0_3_set_powergating_state(void *handle, enum amd_powergating_state state); static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); static int amdgpu_ih_srcid_jpeg[] = …; /** * jpeg_v4_0_3_early_init - set function pointers * * @handle: amdgpu_device pointer * * Set ring and irq function pointers */ static int jpeg_v4_0_3_early_init(void *handle) { … } /** * jpeg_v4_0_3_sw_init - sw init for JPEG block * * @handle: amdgpu_device pointer * * Load firmware and sw initialization */ static int jpeg_v4_0_3_sw_init(void *handle) { … } /** * jpeg_v4_0_3_sw_fini - sw fini for JPEG block * * @handle: amdgpu_device pointer * * JPEG suspend and free up sw allocation */ static int jpeg_v4_0_3_sw_fini(void *handle) { … } static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) { … } /** * jpeg_v4_0_3_hw_init - start and test JPEG block * * @handle: amdgpu_device pointer * */ static int jpeg_v4_0_3_hw_init(void *handle) { … } /** * jpeg_v4_0_3_hw_fini - stop the hardware block * * @handle: amdgpu_device pointer * * Stop the JPEG block, mark ring as not ready any more */ static int jpeg_v4_0_3_hw_fini(void *handle) { … } /** * jpeg_v4_0_3_suspend - suspend JPEG block * * @handle: amdgpu_device pointer * * HW fini and suspend JPEG block */ static int jpeg_v4_0_3_suspend(void *handle) { … } /** * jpeg_v4_0_3_resume - resume JPEG block * * @handle: amdgpu_device pointer * * Resume firmware and hw init JPEG block */ static int jpeg_v4_0_3_resume(void *handle) { … } static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) { … } static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) { … } /** * jpeg_v4_0_3_start - start JPEG block * * @adev: amdgpu_device pointer * * Setup and start the JPEG block */ static int jpeg_v4_0_3_start(struct amdgpu_device *adev) { … } /** * jpeg_v4_0_3_stop - stop JPEG block * * @adev: amdgpu_device pointer * * stop the JPEG block */ static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) { … } /** * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) { … } static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) { … } /** * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * jpeg_v4_0_3_dec_ring_insert_start - insert a start command * * @ring: amdgpu_ring pointer * * Write a start command to the ring. */ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) { … } /** * jpeg_v4_0_3_dec_ring_insert_end - insert a end command * * @ring: amdgpu_ring pointer * * Write a end command to the ring. */ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) { … } /** * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write a fence and a trap command to the ring. */ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned int flags) { … } /** * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrieve vmid from * @ib: indirect buffer to execute * @flags: unused * * Write ring commands to execute the indirect buffer. */ void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) { … } static bool jpeg_v4_0_3_is_idle(void *handle) { … } static int jpeg_v4_0_3_wait_for_idle(void *handle) { … } static int jpeg_v4_0_3_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int jpeg_v4_0_3_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int type, enum amdgpu_interrupt_state state) { … } static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = …; static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = …; static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = …; static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = …; static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = …; static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, uint32_t jpeg_inst, void *ras_err_status) { … } static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, void *ras_err_status) { … } static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, uint32_t jpeg_inst) { … } static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) { … } static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = …; static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = …; static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) { … }
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