/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Christian König <[email protected]> */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_uvd.h" #include "vid.h" #include "uvd/uvd_6_0_d.h" #include "uvd/uvd_6_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" #include "smu/smu_7_1_3_d.h" #include "smu/smu_7_1_3_sh_mask.h" #include "bif/bif_5_1_d.h" #include "gmc/gmc_8_1_d.h" #include "vi.h" #include "ivsrcid/ivsrcid_vislands30.h" /* Polaris10/11/12 firmware version */ #define FW_1_130_16 … static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev); static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v6_0_start(struct amdgpu_device *adev); static void uvd_v6_0_stop(struct amdgpu_device *adev); static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state); static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable); /** * uvd_v6_0_enc_support - get encode support status * * @adev: amdgpu_device pointer * * Returns the current hardware encode support status */ static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev) { … } /** * uvd_v6_0_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_enc_ring_get_rptr - get enc read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc read pointer */ static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_enc_ring_get_wptr - get enc write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc write pointer */ static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_enc_ring_set_wptr - set enc write pointer * * @ring: amdgpu_ring pointer * * Commits the enc write pointer to the hardware */ static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working * * @ring: the engine to test on * */ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg * * @ring: ring we should submit the msg to * @handle: session handle to use * @bo: amdgpu object for which we query the offset * @fence: optional fence to return * * Open up a stream for HW test */ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_bo *bo, struct dma_fence **fence) { … } /** * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg * * @ring: ring we should submit the msg to * @handle: session handle to use * @bo: amdgpu object for which we query the offset * @fence: optional fence to return * * Close up a stream for HW test or if userspace failed to do so */ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_bo *bo, struct dma_fence **fence) { … } /** * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working * * @ring: the engine to test on * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT * */ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) { … } static int uvd_v6_0_early_init(void *handle) { … } static int uvd_v6_0_sw_init(void *handle) { … } static int uvd_v6_0_sw_fini(void *handle) { … } /** * uvd_v6_0_hw_init - start and test UVD block * * @handle: handle used to pass amdgpu_device pointer * * Initialize the hardware, boot up the VCPU and do some testing */ static int uvd_v6_0_hw_init(void *handle) { … } /** * uvd_v6_0_hw_fini - stop the hardware block * * @handle: handle used to pass amdgpu_device pointer * * Stop the UVD block, mark ring as not ready any more */ static int uvd_v6_0_hw_fini(void *handle) { … } static int uvd_v6_0_prepare_suspend(void *handle) { … } static int uvd_v6_0_suspend(void *handle) { … } static int uvd_v6_0_resume(void *handle) { … } /** * uvd_v6_0_mc_resume - memory controller programming * * @adev: amdgpu_device pointer * * Let the UVD memory controller know it's offsets */ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) { … } #if 0 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, bool enable) { u32 data, data1; data = RREG32(mmUVD_CGC_GATE); data1 = RREG32(mmUVD_SUVD_CGC_GATE); if (enable) { data |= UVD_CGC_GATE__SYS_MASK | UVD_CGC_GATE__UDEC_MASK | UVD_CGC_GATE__MPEG2_MASK | UVD_CGC_GATE__RBC_MASK | UVD_CGC_GATE__LMI_MC_MASK | UVD_CGC_GATE__IDCT_MASK | UVD_CGC_GATE__MPRD_MASK | UVD_CGC_GATE__MPC_MASK | UVD_CGC_GATE__LBSI_MASK | UVD_CGC_GATE__LRBBM_MASK | UVD_CGC_GATE__UDEC_RE_MASK | UVD_CGC_GATE__UDEC_CM_MASK | UVD_CGC_GATE__UDEC_IT_MASK | UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__VCPU_MASK | UVD_CGC_GATE__SCPU_MASK; data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | UVD_SUVD_CGC_GATE__SMP_MASK | UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK | UVD_SUVD_CGC_GATE__SRE_H264_MASK | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | UVD_SUVD_CGC_GATE__SIT_H264_MASK | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | UVD_SUVD_CGC_GATE__SCM_H264_MASK | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | UVD_SUVD_CGC_GATE__SDB_H264_MASK | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; } else { data &= ~(UVD_CGC_GATE__SYS_MASK | UVD_CGC_GATE__UDEC_MASK | UVD_CGC_GATE__MPEG2_MASK | UVD_CGC_GATE__RBC_MASK | UVD_CGC_GATE__LMI_MC_MASK | UVD_CGC_GATE__LMI_UMC_MASK | UVD_CGC_GATE__IDCT_MASK | UVD_CGC_GATE__MPRD_MASK | UVD_CGC_GATE__MPC_MASK | UVD_CGC_GATE__LBSI_MASK | UVD_CGC_GATE__LRBBM_MASK | UVD_CGC_GATE__UDEC_RE_MASK | UVD_CGC_GATE__UDEC_CM_MASK | UVD_CGC_GATE__UDEC_IT_MASK | UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__VCPU_MASK | UVD_CGC_GATE__SCPU_MASK); data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | UVD_SUVD_CGC_GATE__SMP_MASK | UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK | UVD_SUVD_CGC_GATE__SRE_H264_MASK | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | UVD_SUVD_CGC_GATE__SIT_H264_MASK | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | UVD_SUVD_CGC_GATE__SCM_H264_MASK | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | UVD_SUVD_CGC_GATE__SDB_H264_MASK | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); } WREG32(mmUVD_CGC_GATE, data); WREG32(mmUVD_SUVD_CGC_GATE, data1); } #endif /** * uvd_v6_0_start - start UVD block * * @adev: amdgpu_device pointer * * Setup and start the UVD block */ static int uvd_v6_0_start(struct amdgpu_device *adev) { … } /** * uvd_v6_0_stop - stop UVD block * * @adev: amdgpu_device pointer * * stop the UVD block */ static void uvd_v6_0_stop(struct amdgpu_device *adev) { … } /** * uvd_v6_0_ring_emit_fence - emit an fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write a fence and a trap command to the ring. */ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write enc a fence and a trap command to the ring. */ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing * * @ring: amdgpu_ring pointer */ static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_ring_test_ring - register write test * * @ring: amdgpu_ring pointer * * Test if we can successfully write to the context register */ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) { … } /** * uvd_v6_0_ring_emit_ib - execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrieve vmid from * @ib: indirect buffer to execute * @flags: unused * * Write ring commands to execute the indirect buffer */ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } /** * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrive vmid from * @ib: indirect buffer to execute * @flags: unused * * Write enc ring commands to execute the indirect buffer */ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { … } static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { … } static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { … } static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { … } static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring) { … } static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static bool uvd_v6_0_is_idle(void *handle) { … } static int uvd_v6_0_wait_for_idle(void *handle) { … } #define AMDGPU_UVD_STATUS_BUSY_MASK … static bool uvd_v6_0_check_soft_reset(void *handle) { … } static int uvd_v6_0_pre_soft_reset(void *handle) { … } static int uvd_v6_0_soft_reset(void *handle) { … } static int uvd_v6_0_post_soft_reset(void *handle) { … } static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) { … } #if 0 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) { uint32_t data, data1, cgc_flags, suvd_flags; data = RREG32(mmUVD_CGC_GATE); data1 = RREG32(mmUVD_SUVD_CGC_GATE); cgc_flags = UVD_CGC_GATE__SYS_MASK | UVD_CGC_GATE__UDEC_MASK | UVD_CGC_GATE__MPEG2_MASK | UVD_CGC_GATE__RBC_MASK | UVD_CGC_GATE__LMI_MC_MASK | UVD_CGC_GATE__IDCT_MASK | UVD_CGC_GATE__MPRD_MASK | UVD_CGC_GATE__MPC_MASK | UVD_CGC_GATE__LBSI_MASK | UVD_CGC_GATE__LRBBM_MASK | UVD_CGC_GATE__UDEC_RE_MASK | UVD_CGC_GATE__UDEC_CM_MASK | UVD_CGC_GATE__UDEC_IT_MASK | UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__VCPU_MASK | UVD_CGC_GATE__SCPU_MASK | UVD_CGC_GATE__JPEG_MASK | UVD_CGC_GATE__JPEG2_MASK; suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | UVD_SUVD_CGC_GATE__SMP_MASK | UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK; data |= cgc_flags; data1 |= suvd_flags; WREG32(mmUVD_CGC_GATE, data); WREG32(mmUVD_SUVD_CGC_GATE, data1); } #endif static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) { … } static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int uvd_v6_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void uvd_v6_0_get_clockgating_state(void *handle, u64 *flags) { … } static const struct amd_ip_funcs uvd_v6_0_ip_funcs = …; static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = …; static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = …; static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = …; static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) { … } static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = …; static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version uvd_v6_0_ip_block = …; const struct amdgpu_ip_block_version uvd_v6_2_ip_block = …; const struct amdgpu_ip_block_version uvd_v6_3_ip_block = …;
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