/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <linux/firmware.h> #include <drm/drm_drv.h> #include "amdgpu.h" #include "amdgpu_ucode.h" #include "amdgpu_vpe.h" #include "amdgpu_smu.h" #include "soc15_common.h" #include "vpe_v6_1.h" #define AMDGPU_CSA_VPE_SIZE … /* VPE CSA resides in the 4th page of CSA */ #define AMDGPU_CSA_VPE_OFFSET … /* 1 second timeout */ #define VPE_IDLE_TIMEOUT … #define VPE_MAX_DPM_LEVEL … #define FIXED1_8_BITS_PER_FRACTIONAL_PART … #define GET_PRATIO_INTEGER_PART(x) … static void vpe_set_ring_funcs(struct amdgpu_device *adev); static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) { … } static inline uint16_t complete_integer_division_u16( uint16_t dividend, uint16_t divisor, uint16_t *remainder) { … } static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) { … } static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) { … } /* * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), * VPE FW will dynamically decide which level should be used according to current loading. * * Get VPE and SOC clocks from PM, and select the appropriate four clock values, * calculate the ratios of adjusting from one clock to another. * The VPE FW can then request the appropriate frequency from the PMFW. */ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) { … } int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) { … } int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) { … } int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) { … } int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) { … } static int vpe_early_init(void *handle) { … } static void vpe_idle_work_handler(struct work_struct *work) { … } static int vpe_common_init(struct amdgpu_vpe *vpe) { … } static int vpe_sw_init(void *handle) { … } static int vpe_sw_fini(void *handle) { … } static int vpe_hw_init(void *handle) { … } static int vpe_hw_fini(void *handle) { … } static int vpe_suspend(void *handle) { … } static int vpe_resume(void *handle) { … } static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { … } static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) { … } static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring, uint32_t device_select, uint32_t exec_count) { … } static void vpe_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, unsigned int flags) { … } static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { … } static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring, uint64_t addr) { … } static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) { … } static int vpe_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int vpe_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) { … } static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) { … } static void vpe_ring_set_wptr(struct amdgpu_ring *ring) { … } static int vpe_ring_test_ring(struct amdgpu_ring *ring) { … } static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) { … } static void vpe_ring_begin_use(struct amdgpu_ring *ring) { … } static void vpe_ring_end_use(struct amdgpu_ring *ring) { … } static const struct amdgpu_ring_funcs vpe_ring_funcs = …; static void vpe_set_ring_funcs(struct amdgpu_device *adev) { … } const struct amd_ip_funcs vpe_ip_funcs = …; const struct amdgpu_ip_block_version vpe_v6_1_ip_block = …;
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