// SPDX-License-Identifier: MIT /* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/module.h> #include <linux/debugfs.h> #include "amdgpu.h" #include "soc15_common.h" #include "soc21.h" #include "vcn/vcn_4_0_0_offset.h" #include "vcn/vcn_4_0_0_sh_mask.h" #include "amdgpu_umsch_mm.h" #include "umsch_mm_4_0_api_def.h" #include "umsch_mm_v4_0.h" #define regUVD_IPX_DLDO_CONFIG … #define regUVD_IPX_DLDO_CONFIG_BASE_IDX … #define regUVD_IPX_DLDO_STATUS … #define regUVD_IPX_DLDO_STATUS_BASE_IDX … #define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT … #define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK … #define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT … #define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK … static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch) { … } static void umsch_mm_v4_0_aggregated_doorbell_init(struct amdgpu_umsch_mm *umsch) { … } static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch) { … } static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch) { … } static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch) { … } static int umsch_mm_v4_0_add_queue(struct amdgpu_umsch_mm *umsch, struct umsch_mm_add_queue_input *input_ptr) { … } static int umsch_mm_v4_0_remove_queue(struct amdgpu_umsch_mm *umsch, struct umsch_mm_remove_queue_input *input_ptr) { … } static int umsch_mm_v4_0_set_regs(struct amdgpu_umsch_mm *umsch) { … } static const struct umsch_mm_funcs umsch_mm_v4_0_funcs = …; void umsch_mm_v4_0_set_funcs(struct amdgpu_umsch_mm *umsch) { … }
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