/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "athub_v3_0.h" #include "athub/athub_3_0_0_offset.h" #include "athub/athub_3_0_0_sh_mask.h" #include "navi10_enum.h" #include "soc15_common.h" #define regATHUB_MISC_CNTL_V3_0_1 … #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX … #define regATHUB_MISC_CNTL_V3_3_0 … #define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX … static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) { … } static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) { … } static void athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } int athub_v3_0_set_clockgating(struct amdgpu_device *adev, enum amd_clockgating_state state) { … } void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) { … }
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