linux/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 *
 */
#ifndef _smuio_13_0_2_OFFSET_HEADER
#define _smuio_13_0_2_OFFSET_HEADER



// addressBlock: smuio_smuio_SmuSmuioDec
// base address: 0x5a000
#define regSMUSVI0_TEL_PLANE0
#define regSMUSVI0_TEL_PLANE0_BASE_IDX
#define regSMUSVI0_PLANE0_CURRENTVID
#define regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX
#define regSMUIO_MCM_CONFIG
#define regSMUIO_MCM_CONFIG_BASE_IDX
#define regCKSVII2C_IC_CON
#define regCKSVII2C_IC_CON_BASE_IDX
#define regCKSVII2C_IC_TAR
#define regCKSVII2C_IC_TAR_BASE_IDX
#define regCKSVII2C_IC_SAR
#define regCKSVII2C_IC_SAR_BASE_IDX
#define regCKSVII2C_IC_HS_MADDR
#define regCKSVII2C_IC_HS_MADDR_BASE_IDX
#define regCKSVII2C_IC_DATA_CMD
#define regCKSVII2C_IC_DATA_CMD_BASE_IDX
#define regCKSVII2C_IC_SS_SCL_HCNT
#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX
#define regCKSVII2C_IC_SS_SCL_LCNT
#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX
#define regCKSVII2C_IC_FS_SCL_HCNT
#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX
#define regCKSVII2C_IC_FS_SCL_LCNT
#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX
#define regCKSVII2C_IC_HS_SCL_HCNT
#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX
#define regCKSVII2C_IC_HS_SCL_LCNT
#define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX
#define regCKSVII2C_IC_INTR_STAT
#define regCKSVII2C_IC_INTR_STAT_BASE_IDX
#define regCKSVII2C_IC_INTR_MASK
#define regCKSVII2C_IC_INTR_MASK_BASE_IDX
#define regCKSVII2C_IC_RAW_INTR_STAT
#define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX
#define regCKSVII2C_IC_RX_TL
#define regCKSVII2C_IC_RX_TL_BASE_IDX
#define regCKSVII2C_IC_TX_TL
#define regCKSVII2C_IC_TX_TL_BASE_IDX
#define regCKSVII2C_IC_CLR_INTR
#define regCKSVII2C_IC_CLR_INTR_BASE_IDX
#define regCKSVII2C_IC_CLR_RX_UNDER
#define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX
#define regCKSVII2C_IC_CLR_RX_OVER
#define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX
#define regCKSVII2C_IC_CLR_TX_OVER
#define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX
#define regCKSVII2C_IC_CLR_RD_REQ
#define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX
#define regCKSVII2C_IC_CLR_TX_ABRT
#define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX
#define regCKSVII2C_IC_CLR_RX_DONE
#define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX
#define regCKSVII2C_IC_CLR_ACTIVITY
#define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX
#define regCKSVII2C_IC_CLR_STOP_DET
#define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX
#define regCKSVII2C_IC_CLR_START_DET
#define regCKSVII2C_IC_CLR_START_DET_BASE_IDX
#define regCKSVII2C_IC_CLR_GEN_CALL
#define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX
#define regCKSVII2C_IC_ENABLE
#define regCKSVII2C_IC_ENABLE_BASE_IDX
#define regCKSVII2C_IC_STATUS
#define regCKSVII2C_IC_STATUS_BASE_IDX
#define regCKSVII2C_IC_TXFLR
#define regCKSVII2C_IC_TXFLR_BASE_IDX
#define regCKSVII2C_IC_RXFLR
#define regCKSVII2C_IC_RXFLR_BASE_IDX
#define regCKSVII2C_IC_SDA_HOLD
#define regCKSVII2C_IC_SDA_HOLD_BASE_IDX
#define regCKSVII2C_IC_TX_ABRT_SOURCE
#define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX
#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY
#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX
#define regCKSVII2C_IC_DMA_CR
#define regCKSVII2C_IC_DMA_CR_BASE_IDX
#define regCKSVII2C_IC_DMA_TDLR
#define regCKSVII2C_IC_DMA_TDLR_BASE_IDX
#define regCKSVII2C_IC_DMA_RDLR
#define regCKSVII2C_IC_DMA_RDLR_BASE_IDX
#define regCKSVII2C_IC_SDA_SETUP
#define regCKSVII2C_IC_SDA_SETUP_BASE_IDX
#define regCKSVII2C_IC_ACK_GENERAL_CALL
#define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX
#define regCKSVII2C_IC_ENABLE_STATUS
#define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX
#define regCKSVII2C_IC_FS_SPKLEN
#define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX
#define regCKSVII2C_IC_HS_SPKLEN
#define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX
#define regCKSVII2C_IC_CLR_RESTART_DET
#define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX
#define regCKSVII2C_IC_COMP_PARAM_1
#define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX
#define regCKSVII2C_IC_COMP_VERSION
#define regCKSVII2C_IC_COMP_VERSION_BASE_IDX
#define regCKSVII2C_IC_COMP_TYPE
#define regCKSVII2C_IC_COMP_TYPE_BASE_IDX
#define regCKSVII2C1_IC_CON
#define regCKSVII2C1_IC_CON_BASE_IDX
#define regCKSVII2C1_IC_TAR
#define regCKSVII2C1_IC_TAR_BASE_IDX
#define regCKSVII2C1_IC_SAR
#define regCKSVII2C1_IC_SAR_BASE_IDX
#define regCKSVII2C1_IC_HS_MADDR
#define regCKSVII2C1_IC_HS_MADDR_BASE_IDX
#define regCKSVII2C1_IC_DATA_CMD
#define regCKSVII2C1_IC_DATA_CMD_BASE_IDX
#define regCKSVII2C1_IC_SS_SCL_HCNT
#define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX
#define regCKSVII2C1_IC_SS_SCL_LCNT
#define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX
#define regCKSVII2C1_IC_FS_SCL_HCNT
#define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX
#define regCKSVII2C1_IC_FS_SCL_LCNT
#define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX
#define regCKSVII2C1_IC_HS_SCL_HCNT
#define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX
#define regCKSVII2C1_IC_HS_SCL_LCNT
#define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX
#define regCKSVII2C1_IC_INTR_STAT
#define regCKSVII2C1_IC_INTR_STAT_BASE_IDX
#define regCKSVII2C1_IC_INTR_MASK
#define regCKSVII2C1_IC_INTR_MASK_BASE_IDX
#define regCKSVII2C1_IC_RAW_INTR_STAT
#define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX
#define regCKSVII2C1_IC_RX_TL
#define regCKSVII2C1_IC_RX_TL_BASE_IDX
#define regCKSVII2C1_IC_TX_TL
#define regCKSVII2C1_IC_TX_TL_BASE_IDX
#define regCKSVII2C1_IC_CLR_INTR
#define regCKSVII2C1_IC_CLR_INTR_BASE_IDX
#define regCKSVII2C1_IC_CLR_RX_UNDER
#define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX
#define regCKSVII2C1_IC_CLR_RX_OVER
#define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX
#define regCKSVII2C1_IC_CLR_TX_OVER
#define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX
#define regCKSVII2C1_IC_CLR_RD_REQ
#define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX
#define regCKSVII2C1_IC_CLR_TX_ABRT
#define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX
#define regCKSVII2C1_IC_CLR_RX_DONE
#define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX
#define regCKSVII2C1_IC_CLR_ACTIVITY
#define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX
#define regCKSVII2C1_IC_CLR_STOP_DET
#define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX
#define regCKSVII2C1_IC_CLR_START_DET
#define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX
#define regCKSVII2C1_IC_CLR_GEN_CALL
#define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX
#define regCKSVII2C1_IC_ENABLE
#define regCKSVII2C1_IC_ENABLE_BASE_IDX
#define regCKSVII2C1_IC_STATUS
#define regCKSVII2C1_IC_STATUS_BASE_IDX
#define regCKSVII2C1_IC_TXFLR
#define regCKSVII2C1_IC_TXFLR_BASE_IDX
#define regCKSVII2C1_IC_RXFLR
#define regCKSVII2C1_IC_RXFLR_BASE_IDX
#define regCKSVII2C1_IC_SDA_HOLD
#define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX
#define regCKSVII2C1_IC_TX_ABRT_SOURCE
#define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX
#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY
#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX
#define regCKSVII2C1_IC_DMA_CR
#define regCKSVII2C1_IC_DMA_CR_BASE_IDX
#define regCKSVII2C1_IC_DMA_TDLR
#define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX
#define regCKSVII2C1_IC_DMA_RDLR
#define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX
#define regCKSVII2C1_IC_SDA_SETUP
#define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX
#define regCKSVII2C1_IC_ACK_GENERAL_CALL
#define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX
#define regCKSVII2C1_IC_ENABLE_STATUS
#define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX
#define regCKSVII2C1_IC_FS_SPKLEN
#define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX
#define regCKSVII2C1_IC_HS_SPKLEN
#define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX
#define regCKSVII2C1_IC_CLR_RESTART_DET
#define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX
#define regCKSVII2C1_IC_COMP_PARAM_1
#define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX
#define regCKSVII2C1_IC_COMP_VERSION
#define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX
#define regCKSVII2C1_IC_COMP_TYPE
#define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX
#define regSMUIO_MP_RESET_INTR
#define regSMUIO_MP_RESET_INTR_BASE_IDX
#define regSMUIO_SOC_HALT
#define regSMUIO_SOC_HALT_BASE_IDX
#define regSMUIO_PWRMGT
#define regSMUIO_PWRMGT_BASE_IDX
#define regSMUIO_GFX_MISC_CNTL
#define regSMUIO_GFX_MISC_CNTL_BASE_IDX
#define regROM_CNTL
#define regROM_CNTL_BASE_IDX
#define regPAGE_MIRROR_CNTL
#define regPAGE_MIRROR_CNTL_BASE_IDX
#define regROM_STATUS
#define regROM_STATUS_BASE_IDX
#define regCGTT_ROM_CLK_CTRL0
#define regCGTT_ROM_CLK_CTRL0_BASE_IDX
#define regROM_INDEX
#define regROM_INDEX_BASE_IDX
#define regROM_DATA
#define regROM_DATA_BASE_IDX
#define regROM_START
#define regROM_START_BASE_IDX
#define regROM_SW_CNTL
#define regROM_SW_CNTL_BASE_IDX
#define regROM_SW_STATUS
#define regROM_SW_STATUS_BASE_IDX
#define regROM_SW_COMMAND
#define regROM_SW_COMMAND_BASE_IDX
#define regROM_SW_DATA_1
#define regROM_SW_DATA_1_BASE_IDX
#define regROM_SW_DATA_2
#define regROM_SW_DATA_2_BASE_IDX
#define regROM_SW_DATA_3
#define regROM_SW_DATA_3_BASE_IDX
#define regROM_SW_DATA_4
#define regROM_SW_DATA_4_BASE_IDX
#define regROM_SW_DATA_5
#define regROM_SW_DATA_5_BASE_IDX
#define regROM_SW_DATA_6
#define regROM_SW_DATA_6_BASE_IDX
#define regROM_SW_DATA_7
#define regROM_SW_DATA_7_BASE_IDX
#define regROM_SW_DATA_8
#define regROM_SW_DATA_8_BASE_IDX
#define regROM_SW_DATA_9
#define regROM_SW_DATA_9_BASE_IDX
#define regROM_SW_DATA_10
#define regROM_SW_DATA_10_BASE_IDX
#define regROM_SW_DATA_11
#define regROM_SW_DATA_11_BASE_IDX
#define regROM_SW_DATA_12
#define regROM_SW_DATA_12_BASE_IDX
#define regROM_SW_DATA_13
#define regROM_SW_DATA_13_BASE_IDX
#define regROM_SW_DATA_14
#define regROM_SW_DATA_14_BASE_IDX
#define regROM_SW_DATA_15
#define regROM_SW_DATA_15_BASE_IDX
#define regROM_SW_DATA_16
#define regROM_SW_DATA_16_BASE_IDX
#define regROM_SW_DATA_17
#define regROM_SW_DATA_17_BASE_IDX
#define regROM_SW_DATA_18
#define regROM_SW_DATA_18_BASE_IDX
#define regROM_SW_DATA_19
#define regROM_SW_DATA_19_BASE_IDX
#define regROM_SW_DATA_20
#define regROM_SW_DATA_20_BASE_IDX
#define regROM_SW_DATA_21
#define regROM_SW_DATA_21_BASE_IDX
#define regROM_SW_DATA_22
#define regROM_SW_DATA_22_BASE_IDX
#define regROM_SW_DATA_23
#define regROM_SW_DATA_23_BASE_IDX
#define regROM_SW_DATA_24
#define regROM_SW_DATA_24_BASE_IDX
#define regROM_SW_DATA_25
#define regROM_SW_DATA_25_BASE_IDX
#define regROM_SW_DATA_26
#define regROM_SW_DATA_26_BASE_IDX
#define regROM_SW_DATA_27
#define regROM_SW_DATA_27_BASE_IDX
#define regROM_SW_DATA_28
#define regROM_SW_DATA_28_BASE_IDX
#define regROM_SW_DATA_29
#define regROM_SW_DATA_29_BASE_IDX
#define regROM_SW_DATA_30
#define regROM_SW_DATA_30_BASE_IDX
#define regROM_SW_DATA_31
#define regROM_SW_DATA_31_BASE_IDX
#define regROM_SW_DATA_32
#define regROM_SW_DATA_32_BASE_IDX
#define regROM_SW_DATA_33
#define regROM_SW_DATA_33_BASE_IDX
#define regROM_SW_DATA_34
#define regROM_SW_DATA_34_BASE_IDX
#define regROM_SW_DATA_35
#define regROM_SW_DATA_35_BASE_IDX
#define regROM_SW_DATA_36
#define regROM_SW_DATA_36_BASE_IDX
#define regROM_SW_DATA_37
#define regROM_SW_DATA_37_BASE_IDX
#define regROM_SW_DATA_38
#define regROM_SW_DATA_38_BASE_IDX
#define regROM_SW_DATA_39
#define regROM_SW_DATA_39_BASE_IDX
#define regROM_SW_DATA_40
#define regROM_SW_DATA_40_BASE_IDX
#define regROM_SW_DATA_41
#define regROM_SW_DATA_41_BASE_IDX
#define regROM_SW_DATA_42
#define regROM_SW_DATA_42_BASE_IDX
#define regROM_SW_DATA_43
#define regROM_SW_DATA_43_BASE_IDX
#define regROM_SW_DATA_44
#define regROM_SW_DATA_44_BASE_IDX
#define regROM_SW_DATA_45
#define regROM_SW_DATA_45_BASE_IDX
#define regROM_SW_DATA_46
#define regROM_SW_DATA_46_BASE_IDX
#define regROM_SW_DATA_47
#define regROM_SW_DATA_47_BASE_IDX
#define regROM_SW_DATA_48
#define regROM_SW_DATA_48_BASE_IDX
#define regROM_SW_DATA_49
#define regROM_SW_DATA_49_BASE_IDX
#define regROM_SW_DATA_50
#define regROM_SW_DATA_50_BASE_IDX
#define regROM_SW_DATA_51
#define regROM_SW_DATA_51_BASE_IDX
#define regROM_SW_DATA_52
#define regROM_SW_DATA_52_BASE_IDX
#define regROM_SW_DATA_53
#define regROM_SW_DATA_53_BASE_IDX
#define regROM_SW_DATA_54
#define regROM_SW_DATA_54_BASE_IDX
#define regROM_SW_DATA_55
#define regROM_SW_DATA_55_BASE_IDX
#define regROM_SW_DATA_56
#define regROM_SW_DATA_56_BASE_IDX
#define regROM_SW_DATA_57
#define regROM_SW_DATA_57_BASE_IDX
#define regROM_SW_DATA_58
#define regROM_SW_DATA_58_BASE_IDX
#define regROM_SW_DATA_59
#define regROM_SW_DATA_59_BASE_IDX
#define regROM_SW_DATA_60
#define regROM_SW_DATA_60_BASE_IDX
#define regROM_SW_DATA_61
#define regROM_SW_DATA_61_BASE_IDX
#define regROM_SW_DATA_62
#define regROM_SW_DATA_62_BASE_IDX
#define regROM_SW_DATA_63
#define regROM_SW_DATA_63_BASE_IDX
#define regROM_SW_DATA_64
#define regROM_SW_DATA_64_BASE_IDX
#define regSMU_GPIOPAD_SW_INT_STAT
#define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX
#define regSMU_GPIOPAD_MASK
#define regSMU_GPIOPAD_MASK_BASE_IDX
#define regSMU_GPIOPAD_A
#define regSMU_GPIOPAD_A_BASE_IDX
#define regSMU_GPIOPAD_TXIMPSEL
#define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX
#define regSMU_GPIOPAD_EN
#define regSMU_GPIOPAD_EN_BASE_IDX
#define regSMU_GPIOPAD_Y
#define regSMU_GPIOPAD_Y_BASE_IDX
#define regSMU_GPIOPAD_RXEN
#define regSMU_GPIOPAD_RXEN_BASE_IDX
#define regSMU_GPIOPAD_RCVR_SEL0
#define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX
#define regSMU_GPIOPAD_RCVR_SEL1
#define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX
#define regSMU_GPIOPAD_PU_EN
#define regSMU_GPIOPAD_PU_EN_BASE_IDX
#define regSMU_GPIOPAD_PD_EN
#define regSMU_GPIOPAD_PD_EN_BASE_IDX
#define regSMU_GPIOPAD_PINSTRAPS
#define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX
#define regDFT_PINSTRAPS
#define regDFT_PINSTRAPS_BASE_IDX
#define regSMU_GPIOPAD_INT_STAT_EN
#define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX
#define regSMU_GPIOPAD_INT_STAT
#define regSMU_GPIOPAD_INT_STAT_BASE_IDX
#define regSMU_GPIOPAD_INT_STAT_AK
#define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX
#define regSMU_GPIOPAD_INT_EN
#define regSMU_GPIOPAD_INT_EN_BASE_IDX
#define regSMU_GPIOPAD_INT_TYPE
#define regSMU_GPIOPAD_INT_TYPE_BASE_IDX
#define regSMU_GPIOPAD_INT_POLARITY
#define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX
#define regROM_CC_BIF_PINSTRAP
#define regROM_CC_BIF_PINSTRAP_BASE_IDX
#define regIO_SMUIO_PINSTRAP
#define regIO_SMUIO_PINSTRAP_BASE_IDX
#define regSMUIO_PCC_CONTROL
#define regSMUIO_PCC_CONTROL_BASE_IDX
#define regSMUIO_PCC_GPIO_SELECT
#define regSMUIO_PCC_GPIO_SELECT_BASE_IDX
#define regSMUIO_GPIO_INT0_SELECT
#define regSMUIO_GPIO_INT0_SELECT_BASE_IDX
#define regSMUIO_GPIO_INT1_SELECT
#define regSMUIO_GPIO_INT1_SELECT_BASE_IDX
#define regSMUIO_GPIO_INT2_SELECT
#define regSMUIO_GPIO_INT2_SELECT_BASE_IDX
#define regSMUIO_GPIO_INT3_SELECT
#define regSMUIO_GPIO_INT3_SELECT_BASE_IDX
#define regSMU_GPIOPAD_MP_INT0_STAT
#define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX
#define regSMU_GPIOPAD_MP_INT1_STAT
#define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX
#define regSMU_GPIOPAD_MP_INT2_STAT
#define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX
#define regSMU_GPIOPAD_MP_INT3_STAT
#define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX
#define regSMIO_INDEX
#define regSMIO_INDEX_BASE_IDX
#define regS0_VID_SMIO_CNTL
#define regS0_VID_SMIO_CNTL_BASE_IDX
#define regS1_VID_SMIO_CNTL
#define regS1_VID_SMIO_CNTL_BASE_IDX
#define regOPEN_DRAIN_SELECT
#define regOPEN_DRAIN_SELECT_BASE_IDX
#define regSMIO_ENABLE
#define regSMIO_ENABLE_BASE_IDX
#define regSMU_GPIOPAD_S0
#define regSMU_GPIOPAD_S0_BASE_IDX
#define regSMU_GPIOPAD_S1
#define regSMU_GPIOPAD_S1_BASE_IDX
#define regSMU_GPIOPAD_SCL_EN
#define regSMU_GPIOPAD_SCL_EN_BASE_IDX
#define regSMU_GPIOPAD_SDA_EN
#define regSMU_GPIOPAD_SDA_EN_BASE_IDX
#define regSMU_GPIOPAD_SCHMEN
#define regSMU_GPIOPAD_SCHMEN_BASE_IDX


// addressBlock: smuio_smuio_pwr_SmuSmuioDec
// base address: 0x5a800
#define regIP_DISCOVERY_VERSION
#define regIP_DISCOVERY_VERSION_BASE_IDX
#define regSOC_GAP_PWROK
#define regSOC_GAP_PWROK_BASE_IDX
#define regGFX_GAP_PWROK
#define regGFX_GAP_PWROK_BASE_IDX
#define regPWROK_REFCLK_GAP_CYCLES
#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX
#define regGOLDEN_TSC_INCREMENT_UPPER
#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX
#define regGOLDEN_TSC_INCREMENT_LOWER
#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX
#define regGOLDEN_TSC_COUNT_UPPER
#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX
#define regGOLDEN_TSC_COUNT_LOWER
#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX
#define regSOC_GOLDEN_TSC_SHADOW_UPPER
#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX
#define regSOC_GOLDEN_TSC_SHADOW_LOWER
#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX
#define regGFX_GOLDEN_TSC_SHADOW_UPPER
#define regGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX
#define regGFX_GOLDEN_TSC_SHADOW_LOWER
#define regGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX
#define regSCRATCH_REGISTER0
#define regSCRATCH_REGISTER0_BASE_IDX
#define regSCRATCH_REGISTER1
#define regSCRATCH_REGISTER1_BASE_IDX
#define regSCRATCH_REGISTER2
#define regSCRATCH_REGISTER2_BASE_IDX
#define regSCRATCH_REGISTER3
#define regSCRATCH_REGISTER3_BASE_IDX
#define regSCRATCH_REGISTER4
#define regSCRATCH_REGISTER4_BASE_IDX
#define regSCRATCH_REGISTER5
#define regSCRATCH_REGISTER5_BASE_IDX
#define regSCRATCH_REGISTER6
#define regSCRATCH_REGISTER6_BASE_IDX
#define regSCRATCH_REGISTER7
#define regSCRATCH_REGISTER7_BASE_IDX
#define regPWR_DISP_TIMER_CONTROL
#define regPWR_DISP_TIMER_CONTROL_BASE_IDX
#define regPWR_DISP_TIMER_DEBUG
#define regPWR_DISP_TIMER_DEBUG_BASE_IDX
#define regPWR_DISP_TIMER2_CONTROL
#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX
#define regPWR_DISP_TIMER2_DEBUG
#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX
#define regPWR_DISP_TIMER_GLOBAL_CONTROL
#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX
#define regPWR_IH_CONTROL
#define regPWR_IH_CONTROL_BASE_IDX

#endif