/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _smuio_13_0_3_OFFSET_HEADER #define _smuio_13_0_3_OFFSET_HEADER // addressBlock: aid_smuio_smuio_reset_SmuSmuioDec // base address: 0x5a300 #define regSMUIO_MP_RESET_INTR … #define regSMUIO_MP_RESET_INTR_BASE_IDX … #define regSMUIO_SOC_HALT … #define regSMUIO_SOC_HALT_BASE_IDX … // addressBlock: aid_smuio_smuio_tsc_SmuSmuioDec // base address: 0x5a8a0 #define regPWROK_REFCLK_GAP_CYCLES … #define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX … #define regGOLDEN_TSC_INCREMENT_UPPER … #define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX … #define regGOLDEN_TSC_INCREMENT_LOWER … #define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX … #define regGOLDEN_TSC_COUNT_UPPER … #define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX … #define regGOLDEN_TSC_COUNT_LOWER … #define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX … #define regSOC_GOLDEN_TSC_SHADOW_UPPER … #define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX … #define regSOC_GOLDEN_TSC_SHADOW_LOWER … #define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX … #define regSOC_GAP_PWROK … #define regSOC_GAP_PWROK_BASE_IDX … // addressBlock: aid_smuio_smuio_swtimer_SmuSmuioDec // base address: 0x5ac70 #define regPWR_VIRT_RESET_REQ … #define regPWR_VIRT_RESET_REQ_BASE_IDX … #define regPWR_DISP_TIMER_CONTROL … #define regPWR_DISP_TIMER_CONTROL_BASE_IDX … #define regPWR_DISP_TIMER_DEBUG … #define regPWR_DISP_TIMER_DEBUG_BASE_IDX … #define regPWR_DISP_TIMER2_CONTROL … #define regPWR_DISP_TIMER2_CONTROL_BASE_IDX … #define regPWR_DISP_TIMER2_DEBUG … #define regPWR_DISP_TIMER2_DEBUG_BASE_IDX … #define regPWR_DISP_TIMER_GLOBAL_CONTROL … #define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX … #define regPWR_IH_CONTROL … #define regPWR_IH_CONTROL_BASE_IDX … // addressBlock: aid_smuio_smuio_misc_SmuSmuioDec // base address: 0x5a000 #define regSMUIO_MCM_CONFIG … #define regSMUIO_MCM_CONFIG_BASE_IDX … #define regIP_DISCOVERY_VERSION … #define regIP_DISCOVERY_VERSION_BASE_IDX … #define regSCRATCH_REGISTER0 … #define regSCRATCH_REGISTER0_BASE_IDX … #define regSCRATCH_REGISTER1 … #define regSCRATCH_REGISTER1_BASE_IDX … #define regSCRATCH_REGISTER2 … #define regSCRATCH_REGISTER2_BASE_IDX … #define regSCRATCH_REGISTER3 … #define regSCRATCH_REGISTER3_BASE_IDX … #define regSCRATCH_REGISTER4 … #define regSCRATCH_REGISTER4_BASE_IDX … #define regSCRATCH_REGISTER5 … #define regSCRATCH_REGISTER5_BASE_IDX … #define regSCRATCH_REGISTER6 … #define regSCRATCH_REGISTER6_BASE_IDX … #define regSCRATCH_REGISTER7 … #define regSCRATCH_REGISTER7_BASE_IDX … // addressBlock: aid_smuio_smuio_gpio_SmuSmuioDec // base address: 0x5a500 #define regSMU_GPIOPAD_SW_INT_STAT … #define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX … #define regSMU_GPIOPAD_MASK … #define regSMU_GPIOPAD_MASK_BASE_IDX … #define regSMU_GPIOPAD_A … #define regSMU_GPIOPAD_A_BASE_IDX … #define regSMU_GPIOPAD_TXIMPSEL … #define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX … #define regSMU_GPIOPAD_EN … #define regSMU_GPIOPAD_EN_BASE_IDX … #define regSMU_GPIOPAD_Y … #define regSMU_GPIOPAD_Y_BASE_IDX … #define regSMU_GPIOPAD_RXEN … #define regSMU_GPIOPAD_RXEN_BASE_IDX … #define regSMU_GPIOPAD_RCVR_SEL0 … #define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX … #define regSMU_GPIOPAD_RCVR_SEL1 … #define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX … #define regSMU_GPIOPAD_PU_EN … #define regSMU_GPIOPAD_PU_EN_BASE_IDX … #define regSMU_GPIOPAD_PD_EN … #define regSMU_GPIOPAD_PD_EN_BASE_IDX … #define regSMU_GPIOPAD_PINSTRAPS … #define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX … #define regDFT_PINSTRAPS … #define regDFT_PINSTRAPS_BASE_IDX … #define regSMU_GPIOPAD_INT_STAT_EN … #define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX … #define regSMU_GPIOPAD_INT_STAT … #define regSMU_GPIOPAD_INT_STAT_BASE_IDX … #define regSMU_GPIOPAD_INT_STAT_AK … #define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX … #define regSMU_GPIOPAD_INT_EN … #define regSMU_GPIOPAD_INT_EN_BASE_IDX … #define regSMU_GPIOPAD_INT_TYPE … #define regSMU_GPIOPAD_INT_TYPE_BASE_IDX … #define regSMU_GPIOPAD_INT_POLARITY … #define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX … #define regSMUIO_PCC_GPIO_SELECT … #define regSMUIO_PCC_GPIO_SELECT_BASE_IDX … #define regSMU_GPIOPAD_S0 … #define regSMU_GPIOPAD_S0_BASE_IDX … #define regSMU_GPIOPAD_S1 … #define regSMU_GPIOPAD_S1_BASE_IDX … #define regSMU_GPIOPAD_SCHMEN … #define regSMU_GPIOPAD_SCHMEN_BASE_IDX … #define regSMU_GPIOPAD_SCL_EN … #define regSMU_GPIOPAD_SCL_EN_BASE_IDX … #define regSMU_GPIOPAD_SDA_EN … #define regSMU_GPIOPAD_SDA_EN_BASE_IDX … #define regSMUIO_GPIO_INT0_SELECT … #define regSMUIO_GPIO_INT0_SELECT_BASE_IDX … #define regSMUIO_GPIO_INT1_SELECT … #define regSMUIO_GPIO_INT1_SELECT_BASE_IDX … #define regSMUIO_GPIO_INT2_SELECT … #define regSMUIO_GPIO_INT2_SELECT_BASE_IDX … #define regSMUIO_GPIO_INT3_SELECT … #define regSMUIO_GPIO_INT3_SELECT_BASE_IDX … #define regSMU_GPIOPAD_MP_INT0_STAT … #define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX … #define regSMU_GPIOPAD_MP_INT1_STAT … #define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX … #define regSMU_GPIOPAD_MP_INT2_STAT … #define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX … #define regSMU_GPIOPAD_MP_INT3_STAT … #define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX … #define regSMIO_INDEX … #define regSMIO_INDEX_BASE_IDX … #define regS0_VID_SMIO_CNTL … #define regS0_VID_SMIO_CNTL_BASE_IDX … #define regS1_VID_SMIO_CNTL … #define regS1_VID_SMIO_CNTL_BASE_IDX … #define regOPEN_DRAIN_SELECT … #define regOPEN_DRAIN_SELECT_BASE_IDX … #define regSMIO_ENABLE … #define regSMIO_ENABLE_BASE_IDX … #endif
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