linux/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_3_sh_mask.h

/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _smuio_13_0_3_SH_MASK_HEADER
#define _smuio_13_0_3_SH_MASK_HEADER


// addressBlock: aid_smuio_smuio_reset_SmuSmuioDec
//SMUIO_MP_RESET_INTR
#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT
#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK
//SMUIO_SOC_HALT
#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT
#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT
#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK
#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK


// addressBlock: aid_smuio_smuio_tsc_SmuSmuioDec
//PWROK_REFCLK_GAP_CYCLES
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK
//GOLDEN_TSC_INCREMENT_UPPER
#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT
#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK
//GOLDEN_TSC_INCREMENT_LOWER
#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT
#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK
//GOLDEN_TSC_COUNT_UPPER
#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT
#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK
//GOLDEN_TSC_COUNT_LOWER
#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT
#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK
//SOC_GOLDEN_TSC_SHADOW_UPPER
#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT
#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK
//SOC_GOLDEN_TSC_SHADOW_LOWER
#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT
#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK
//SOC_GAP_PWROK
#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT
#define SOC_GAP_PWROK__soc_gap_pwrok_MASK


// addressBlock: aid_smuio_smuio_swtimer_SmuSmuioDec
//PWR_VIRT_RESET_REQ
#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT
#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT
#define PWR_VIRT_RESET_REQ__VF_FLR_MASK
#define PWR_VIRT_RESET_REQ__PF_FLR_MASK
//PWR_DISP_TIMER_CONTROL
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK
//PWR_DISP_TIMER_DEBUG
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK
#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK
//PWR_DISP_TIMER2_CONTROL
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK
//PWR_DISP_TIMER2_DEBUG
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK
#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK
//PWR_DISP_TIMER_GLOBAL_CONTROL
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK
//PWR_IH_CONTROL
#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT
#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT
#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT
#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT
#define PWR_IH_CONTROL__MAX_CREDIT_MASK
#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK
#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK
#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK


// addressBlock: aid_smuio_smuio_misc_SmuSmuioDec
//SMUIO_MCM_CONFIG
#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT
#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT
#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT
#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT
#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT
#define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT
#define SMUIO_MCM_CONFIG__DIE_ID_MASK
#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK
#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK
#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK
#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK
#define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK
//IP_DISCOVERY_VERSION
#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT
#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK
//SCRATCH_REGISTER0
#define SCRATCH_REGISTER0__ScratchPad0__SHIFT
#define SCRATCH_REGISTER0__ScratchPad0_MASK
//SCRATCH_REGISTER1
#define SCRATCH_REGISTER1__ScratchPad1__SHIFT
#define SCRATCH_REGISTER1__ScratchPad1_MASK
//SCRATCH_REGISTER2
#define SCRATCH_REGISTER2__ScratchPad2__SHIFT
#define SCRATCH_REGISTER2__ScratchPad2_MASK
//SCRATCH_REGISTER3
#define SCRATCH_REGISTER3__ScratchPad3__SHIFT
#define SCRATCH_REGISTER3__ScratchPad3_MASK
//SCRATCH_REGISTER4
#define SCRATCH_REGISTER4__ScratchPad4__SHIFT
#define SCRATCH_REGISTER4__ScratchPad4_MASK
//SCRATCH_REGISTER5
#define SCRATCH_REGISTER5__ScratchPad5__SHIFT
#define SCRATCH_REGISTER5__ScratchPad5_MASK
//SCRATCH_REGISTER6
#define SCRATCH_REGISTER6__ScratchPad6__SHIFT
#define SCRATCH_REGISTER6__ScratchPad6_MASK
//SCRATCH_REGISTER7
#define SCRATCH_REGISTER7__ScratchPad7__SHIFT
#define SCRATCH_REGISTER7__ScratchPad7_MASK


// addressBlock: aid_smuio_smuio_gpio_SmuSmuioDec
//SMU_GPIOPAD_SW_INT_STAT
#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT
#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK
//SMU_GPIOPAD_MASK
#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT
#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK
//SMU_GPIOPAD_A
#define SMU_GPIOPAD_A__GPIO_A__SHIFT
#define SMU_GPIOPAD_A__GPIO_A_MASK
//SMU_GPIOPAD_TXIMPSEL
#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT
#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK
//SMU_GPIOPAD_EN
#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT
#define SMU_GPIOPAD_EN__GPIO_EN_MASK
//SMU_GPIOPAD_Y
#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT
#define SMU_GPIOPAD_Y__GPIO_Y_MASK
//SMU_GPIOPAD_RXEN
#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT
#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK
//SMU_GPIOPAD_RCVR_SEL0
#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT
#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK
//SMU_GPIOPAD_RCVR_SEL1
#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT
#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK
//SMU_GPIOPAD_PU_EN
#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT
#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK
//SMU_GPIOPAD_PD_EN
#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT
#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK
//SMU_GPIOPAD_PINSTRAPS
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK
//DFT_PINSTRAPS
#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT
#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK
//SMU_GPIOPAD_INT_STAT_EN
#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT
#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT
#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK
#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK
//SMU_GPIOPAD_INT_STAT
#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT
#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT
#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK
#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK
//SMU_GPIOPAD_INT_STAT_AK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK
#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK
//SMU_GPIOPAD_INT_EN
#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT
#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT
#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK
#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK
//SMU_GPIOPAD_INT_TYPE
#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT
#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT
#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK
#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK
//SMU_GPIOPAD_INT_POLARITY
#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT
#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT
#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK
#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK
//SMUIO_PCC_GPIO_SELECT
#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT
#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK
//SMU_GPIOPAD_S0
#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT
#define SMU_GPIOPAD_S0__GPIO_S0_MASK
//SMU_GPIOPAD_S1
#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT
#define SMU_GPIOPAD_S1__GPIO_S1_MASK
//SMU_GPIOPAD_SCHMEN
#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT
#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK
//SMU_GPIOPAD_SCL_EN
#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT
#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK
//SMU_GPIOPAD_SDA_EN
#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT
#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK
//SMUIO_GPIO_INT0_SELECT
#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT
#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK
//SMUIO_GPIO_INT1_SELECT
#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT
#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK
//SMUIO_GPIO_INT2_SELECT
#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT
#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK
//SMUIO_GPIO_INT3_SELECT
#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT
#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK
//SMU_GPIOPAD_MP_INT0_STAT
#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT
#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK
//SMU_GPIOPAD_MP_INT1_STAT
#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT
#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK
//SMU_GPIOPAD_MP_INT2_STAT
#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT
#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK
//SMU_GPIOPAD_MP_INT3_STAT
#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT
#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK
//SMIO_INDEX
#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT
#define SMIO_INDEX__SW_SMIO_INDEX_MASK
//S0_VID_SMIO_CNTL
#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT
#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK
//S1_VID_SMIO_CNTL
#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT
#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK
//OPEN_DRAIN_SELECT
#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT
#define OPEN_DRAIN_SELECT__RESERVED__SHIFT
#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK
#define OPEN_DRAIN_SELECT__RESERVED_MASK
//SMIO_ENABLE
#define SMIO_ENABLE__SMIO_ENABLE__SHIFT
#define SMIO_ENABLE__SMIO_ENABLE_MASK

#endif