/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_cs.h" #include "amdgpu_vcn.h" #include "amdgpu_pm.h" #include "soc15.h" #include "soc15d.h" #include "soc15_common.h" #include "vcn/vcn_1_0_offset.h" #include "vcn/vcn_1_0_sh_mask.h" #include "mmhub/mmhub_9_1_offset.h" #include "mmhub/mmhub_9_1_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" #include "jpeg_v1_0.h" #include "vcn_v1_0.h" #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 … #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX … #define mmUVD_REG_XX_MASK_1_0 … #define mmUVD_REG_XX_MASK_1_0_BASE_IDX … static int vcn_v1_0_stop(struct amdgpu_device *adev); static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state); static void vcn_v1_0_idle_work_handler(struct work_struct *work); static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); /** * vcn_v1_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers * Load microcode from filesystem */ static int vcn_v1_0_early_init(void *handle) { … } /** * vcn_v1_0_sw_init - sw init for VCN block * * @handle: amdgpu_device pointer * * Load firmware and sw initialization */ static int vcn_v1_0_sw_init(void *handle) { … } /** * vcn_v1_0_sw_fini - sw fini for VCN block * * @handle: amdgpu_device pointer * * VCN suspend and free up sw allocation */ static int vcn_v1_0_sw_fini(void *handle) { … } /** * vcn_v1_0_hw_init - start and test VCN block * * @handle: amdgpu_device pointer * * Initialize the hardware, boot up the VCPU and do some testing */ static int vcn_v1_0_hw_init(void *handle) { … } /** * vcn_v1_0_hw_fini - stop the hardware block * * @handle: amdgpu_device pointer * * Stop the VCN block, mark ring as not ready any more */ static int vcn_v1_0_hw_fini(void *handle) { … } /** * vcn_v1_0_suspend - suspend VCN block * * @handle: amdgpu_device pointer * * HW fini and suspend VCN block */ static int vcn_v1_0_suspend(void *handle) { … } /** * vcn_v1_0_resume - resume VCN block * * @handle: amdgpu_device pointer * * Resume firmware and hw init VCN block */ static int vcn_v1_0_resume(void *handle) { … } /** * vcn_v1_0_mc_resume_spg_mode - memory controller programming * * @adev: amdgpu_device pointer * * Let the VCN memory controller know it's offsets */ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) { … } static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) { … } /** * vcn_v1_0_disable_clock_gating - disable VCN clock gating * * @adev: amdgpu_device pointer * * Disable clock gating for VCN block */ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) { … } /** * vcn_v1_0_enable_clock_gating - enable VCN clock gating * * @adev: amdgpu_device pointer * * Enable clock gating for VCN block */ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) { … } static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) { … } static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) { … } static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) { … } /** * vcn_v1_0_start_spg_mode - start VCN block * * @adev: amdgpu_device pointer * * Setup and start the VCN block */ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) { … } static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) { … } static int vcn_v1_0_start(struct amdgpu_device *adev) { … } /** * vcn_v1_0_stop_spg_mode - stop VCN block * * @adev: amdgpu_device pointer * * stop the VCN block */ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) { … } static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) { … } static int vcn_v1_0_stop(struct amdgpu_device *adev) { … } static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state) { … } static bool vcn_v1_0_is_idle(void *handle) { … } static int vcn_v1_0_wait_for_idle(void *handle) { … } static int vcn_v1_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } /** * vcn_v1_0_dec_ring_get_rptr - get read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware read pointer */ static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_dec_ring_get_wptr - get write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware write pointer */ static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_dec_ring_set_wptr - set write pointer * * @ring: amdgpu_ring pointer * * Commits the write pointer to the hardware */ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_dec_ring_insert_start - insert a start command * * @ring: amdgpu_ring pointer * * Write a start command to the ring. */ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_dec_ring_insert_end - insert a end command * * @ring: amdgpu_ring pointer * * Write a end command to the ring. */ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write a fence and a trap command to the ring. */ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrieve vmid from * @ib: indirect buffer to execute * @flags: unused * * Write ring commands to execute the indirect buffer */ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { … } static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } /** * vcn_v1_0_enc_ring_get_rptr - get enc read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc read pointer */ static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_enc_ring_get_wptr - get enc write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware enc write pointer */ static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_enc_ring_set_wptr - set enc write pointer * * @ring: amdgpu_ring pointer * * Commits the enc write pointer to the hardware */ static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command * * @ring: amdgpu_ring pointer * @addr: address * @seq: sequence number * @flags: fence related flags * * Write enc a fence and a trap command to the ring. */ static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) { … } /** * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer * * @ring: amdgpu_ring pointer * @job: job to retrive vmid from * @ib: indirect buffer to execute * @flags: unused * * Write enc ring commands to execute the indirect buffer */ static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask) { … } static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { … } static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void vcn_v1_0_idle_work_handler(struct work_struct *work) { … } static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) { … } void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) { … } void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) { … } static const struct amd_ip_funcs vcn_v1_0_ip_funcs = …; /* * It is a hardware issue that VCN can't handle a GTT TMZ buffer on * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain * before command submission as a workaround. */ static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser, struct amdgpu_job *job, uint64_t addr) { … } static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib) { … } static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = …; static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = …; static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) { … } static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = …; static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version vcn_v1_0_ip_block = …;
Codebase Browser
linux