/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_vcn.h" #include "amdgpu_pm.h" #include "amdgpu_cs.h" #include "soc15.h" #include "soc15d.h" #include "soc15_hw_ip.h" #include "vcn_v2_0.h" #include "mmsch_v4_0.h" #include "vcn_v4_0.h" #include "vcn/vcn_4_0_0_offset.h" #include "vcn/vcn_4_0_0_sh_mask.h" #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" #include <drm/drm_drv.h> #define mmUVD_DPG_LMA_CTL … #define mmUVD_DPG_LMA_CTL_BASE_IDX … #define mmUVD_DPG_LMA_DATA … #define mmUVD_DPG_LMA_DATA_BASE_IDX … #define VCN_VID_SOC_ADDRESS_2_0 … #define VCN1_VID_SOC_ADDRESS_3_0 … #define VCN_HARVEST_MMSCH … #define RDECODE_MSG_CREATE … #define RDECODE_MESSAGE_CREATE … static int amdgpu_ih_clientid_vcns[] = …; static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state); static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state); static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); /** * vcn_v4_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers * Load microcode from filesystem */ static int vcn_v4_0_early_init(void *handle) { … } static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) { … } /** * vcn_v4_0_sw_init - sw init for VCN block * * @handle: amdgpu_device pointer * * Load firmware and sw initialization */ static int vcn_v4_0_sw_init(void *handle) { … } /** * vcn_v4_0_sw_fini - sw fini for VCN block * * @handle: amdgpu_device pointer * * VCN suspend and free up sw allocation */ static int vcn_v4_0_sw_fini(void *handle) { … } /** * vcn_v4_0_hw_init - start and test VCN block * * @handle: amdgpu_device pointer * * Initialize the hardware, boot up the VCPU and do some testing */ static int vcn_v4_0_hw_init(void *handle) { … } /** * vcn_v4_0_hw_fini - stop the hardware block * * @handle: amdgpu_device pointer * * Stop the VCN block, mark ring as not ready any more */ static int vcn_v4_0_hw_fini(void *handle) { … } /** * vcn_v4_0_suspend - suspend VCN block * * @handle: amdgpu_device pointer * * HW fini and suspend VCN block */ static int vcn_v4_0_suspend(void *handle) { … } /** * vcn_v4_0_resume - resume VCN block * * @handle: amdgpu_device pointer * * Resume firmware and hw init VCN block */ static int vcn_v4_0_resume(void *handle) { … } /** * vcn_v4_0_mc_resume - memory controller programming * * @adev: amdgpu_device pointer * @inst: instance number * * Let the VCN memory controller know it's offsets */ static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) { … } /** * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode * * @adev: amdgpu_device pointer * @inst_idx: instance number index * @indirect: indirectly write sram * * Let the VCN memory controller know it's offsets with dpg mode */ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } /** * vcn_v4_0_disable_static_power_gating - disable VCN static power gating * * @adev: amdgpu_device pointer * @inst: instance number * * Disable static power gating for VCN block */ static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) { … } /** * vcn_v4_0_enable_static_power_gating - enable VCN static power gating * * @adev: amdgpu_device pointer * @inst: instance number * * Enable static power gating for VCN block */ static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) { … } /** * vcn_v4_0_disable_clock_gating - disable VCN clock gating * * @adev: amdgpu_device pointer * @inst: instance number * * Disable clock gating for VCN block */ static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) { … } /** * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode * * @adev: amdgpu_device pointer * @sram_sel: sram select * @inst_idx: instance number index * @indirect: indirectly write sram * * Disable clock gating for VCN block with dpg mode */ static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, int inst_idx, uint8_t indirect) { … } /** * vcn_v4_0_enable_clock_gating - enable VCN clock gating * * @adev: amdgpu_device pointer * @inst: instance number * * Enable clock gating for VCN block */ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) { … } static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } /** * vcn_v4_0_start_dpg_mode - VCN start with dpg mode * * @adev: amdgpu_device pointer * @inst_idx: instance number index * @indirect: indirectly write sram * * Start VCN block with dpg mode */ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) { … } /** * vcn_v4_0_start - VCN start * * @adev: amdgpu_device pointer * * Start VCN block */ static int vcn_v4_0_start(struct amdgpu_device *adev) { … } static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc) { … } static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) { … } /** * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode * * @adev: amdgpu_device pointer * @inst_idx: instance number index * * Stop VCN block with dpg mode */ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) { … } /** * vcn_v4_0_stop - VCN stop * * @adev: amdgpu_device pointer * * Stop VCN block */ static int vcn_v4_0_stop(struct amdgpu_device *adev) { … } /** * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode * * @adev: amdgpu_device pointer * @inst_idx: instance number index * @new_state: pause state * * Pause dpg mode for VCN block */ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state) { … } /** * vcn_v4_0_unified_ring_get_rptr - get unified read pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware unified read pointer */ static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) { … } /** * vcn_v4_0_unified_ring_get_wptr - get unified write pointer * * @ring: amdgpu_ring pointer * * Returns the current hardware unified write pointer */ static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) { … } /** * vcn_v4_0_unified_ring_set_wptr - set enc write pointer * * @ring: amdgpu_ring pointer * * Commits the enc write pointer to the hardware */ static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) { … } static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, struct amdgpu_job *job) { … } static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, uint64_t addr) { … } #define RADEON_VCN_ENGINE_TYPE_ENCODE … #define RADEON_VCN_ENGINE_TYPE_DECODE … #define RADEON_VCN_ENGINE_INFO … #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET … #define RENCODE_ENCODE_STANDARD_AV1 … #define RENCODE_IB_PARAM_SESSION_INIT … #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET … /* return the offset in ib if id is found, -1 otherwise * to speed up the searching we only search upto max_offset */ static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) { … } static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib) { … } static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = …; /** * vcn_v4_0_set_unified_ring_funcs - set unified ring functions * * @adev: amdgpu_device pointer * * Set unified ring functions */ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) { … } /** * vcn_v4_0_is_idle - check VCN block is idle * * @handle: amdgpu_device pointer * * Check whether VCN block is idle */ static bool vcn_v4_0_is_idle(void *handle) { … } /** * vcn_v4_0_wait_for_idle - wait for VCN block idle * * @handle: amdgpu_device pointer * * Wait for VCN block idle */ static int vcn_v4_0_wait_for_idle(void *handle) { … } /** * vcn_v4_0_set_clockgating_state - set VCN block clockgating state * * @handle: amdgpu_device pointer * @state: clock gating state * * Set VCN block clockgating state */ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } /** * vcn_v4_0_set_powergating_state - set VCN block powergating state * * @handle: amdgpu_device pointer * @state: power gating state * * Set VCN block powergating state */ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } /** * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state * * @adev: amdgpu_device pointer * @source: interrupt sources * @type: interrupt types * @state: interrupt states * * Set VCN block RAS interrupt state */ static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int type, enum amdgpu_interrupt_state state) { … } /** * vcn_v4_0_process_interrupt - process VCN block interrupt * * @adev: amdgpu_device pointer * @source: interrupt sources * @entry: interrupt entry from clients and sources * * Process VCN block interrupt */ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = …; static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = …; /** * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions * * @adev: amdgpu_device pointer * * Set VCN block interrupt irq functions */ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) { … } static const struct amd_ip_funcs vcn_v4_0_ip_funcs = …; const struct amdgpu_ip_block_version vcn_v4_0_ip_block = …; static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, uint32_t instance, uint32_t sub_block) { … } static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) { … } const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = …; static struct amdgpu_vcn_ras vcn_v4_0_ras = …; static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) { … }
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